1 /* $NetBSD: mcpcia_pci.c,v 1.4 2000/06/29 08:58:48 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1998 by Matthew Jacob 5 * NASA AMES Research Center. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 34 35 __KERNEL_RCSID(0, "$NetBSD: mcpcia_pci.c,v 1.4 2000/06/29 08:58:48 mrg Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <alpha/pci/mcpciareg.h> 47 #include <alpha/pci/mcpciavar.h> 48 49 #define KV(_addr) ((caddr_t)ALPHA_PHYS_TO_K0SEG((_addr))) 50 51 static void mcpcia_attach_hook __P((struct device *, struct device *, 52 struct pcibus_attach_args *)); 53 static int 54 mcpcia_bus_maxdevs __P((void *, int)); 55 static pcitag_t 56 mcpcia_make_tag __P((void *, int, int, int)); 57 static void 58 mcpcia_decompose_tag __P((void *, pcitag_t, int *, int *, int *)); 59 static pcireg_t 60 mcpcia_conf_read __P((void *, pcitag_t, int)); 61 static void 62 mcpcia_conf_write __P((void *, pcitag_t, int, pcireg_t)); 63 64 void 65 mcpcia_pci_init(pc, v) 66 pci_chipset_tag_t pc; 67 void *v; 68 { 69 pc->pc_conf_v = v; 70 pc->pc_attach_hook = mcpcia_attach_hook; 71 pc->pc_bus_maxdevs = mcpcia_bus_maxdevs; 72 pc->pc_make_tag = mcpcia_make_tag; 73 pc->pc_decompose_tag = mcpcia_decompose_tag; 74 pc->pc_conf_read = mcpcia_conf_read; 75 pc->pc_conf_write = mcpcia_conf_write; 76 } 77 78 static void 79 mcpcia_attach_hook(parent, self, pba) 80 struct device *parent, *self; 81 struct pcibus_attach_args *pba; 82 { 83 } 84 85 static int 86 mcpcia_bus_maxdevs(cpv, busno) 87 void *cpv; 88 int busno; 89 { 90 return (MCPCIA_MAXDEV); 91 } 92 93 static pcitag_t 94 mcpcia_make_tag(cpv, b, d, f) 95 void *cpv; 96 int b, d, f; 97 { 98 pcitag_t tag; 99 tag = (b << 21) | (d << 16) | (f << 13); 100 return (tag); 101 } 102 103 static void 104 mcpcia_decompose_tag(cpv, tag, bp, dp, fp) 105 void *cpv; 106 pcitag_t tag; 107 int *bp, *dp, *fp; 108 { 109 if (bp != NULL) 110 *bp = (tag >> 21) & 0xff; 111 if (dp != NULL) 112 *dp = (tag >> 16) & 0x1f; 113 if (fp != NULL) 114 *fp = (tag >> 13) & 0x7; 115 } 116 117 static pcireg_t 118 mcpcia_conf_read(cpv, tag, offset) 119 void *cpv; 120 pcitag_t tag; 121 int offset; 122 { 123 struct mcpcia_config *ccp = cpv; 124 pcireg_t *dp, data = (pcireg_t) -1; 125 unsigned long paddr; 126 127 /* 128 * There's nothing in slot 0 on a primary bus- don't even try. 129 */ 130 if ((tag >> 21) == 0 && ((u_int32_t) tag & 0x1f0000) == 0) 131 return (data); 132 133 if (ccp == NULL) { 134 panic("NULL ccp in mcpcia_conf_read"); 135 } 136 paddr = (unsigned long) tag; 137 paddr |= (3LL << 3); /* 32 Bit PCI byte enables */ 138 paddr |= ((unsigned long) ((offset >> 2) << 7)); 139 paddr |= MCPCIA_PCI_CONF; 140 paddr |= ccp->cc_sysbase; 141 dp = (pcireg_t *)KV(paddr); 142 if (badaddr(dp, sizeof (*dp)) == 0) { 143 data = *dp; 144 } 145 return (data); 146 } 147 148 static void 149 mcpcia_conf_write(cpv, tag, offset, data) 150 void *cpv; 151 pcitag_t tag; 152 int offset; 153 pcireg_t data; 154 { 155 struct mcpcia_config *ccp = cpv; 156 pcireg_t *dp; 157 unsigned long paddr; 158 159 /* 160 * There's nothing in slot 0 on a primary bus- don't even try. 161 */ 162 if ((tag >> 21) == 0 && ((u_int32_t) tag & 0x1f0000) == 0) 163 return; 164 165 if (ccp == NULL) { 166 panic("NULL ccp in mcpcia_conf_write"); 167 } 168 paddr = (unsigned long) tag; 169 paddr |= (3LL << 3); /* 32 Bit PCI byte enables */ 170 paddr |= ((unsigned long) ((offset >> 2) << 7)); 171 paddr |= MCPCIA_PCI_CONF; 172 paddr |= ccp->cc_sysbase; 173 174 dp = (pcireg_t *)KV(paddr); 175 *dp = data; 176 } 177