1 /* $NetBSD: pci_550.c,v 1.23 2002/05/15 16:57:42 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center, and by Andrew Gallatin. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: pci_550.c,v 1.23 2002/05/15 16:57:42 thorpej Exp $"); 70 71 #include <sys/types.h> 72 #include <sys/param.h> 73 #include <sys/time.h> 74 #include <sys/systm.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/syslog.h> 79 80 #include <uvm/uvm_extern.h> 81 82 #include <machine/autoconf.h> 83 #include <machine/rpb.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pciidereg.h> 88 #include <dev/pci/pciidevar.h> 89 90 #include <alpha/pci/ciareg.h> 91 #include <alpha/pci/ciavar.h> 92 93 #include <alpha/pci/pci_550.h> 94 95 #include "sio.h" 96 #if NSIO 97 #include <alpha/pci/siovar.h> 98 #endif 99 100 int dec_550_intr_map __P((struct pci_attach_args *, 101 pci_intr_handle_t *)); 102 const char *dec_550_intr_string __P((void *, pci_intr_handle_t)); 103 const struct evcnt *dec_550_intr_evcnt __P((void *, pci_intr_handle_t)); 104 void *dec_550_intr_establish __P((void *, pci_intr_handle_t, 105 int, int (*func)(void *), void *)); 106 void dec_550_intr_disestablish __P((void *, void *)); 107 108 void *dec_550_pciide_compat_intr_establish __P((void *, struct device *, 109 struct pci_attach_args *, int, int (*)(void *), void *)); 110 111 #define DEC_550_PCI_IRQ_BEGIN 8 112 #define DEC_550_MAX_IRQ (64 - DEC_550_PCI_IRQ_BEGIN) 113 114 /* 115 * The Miata has a Pyxis, which seems to have problems with stray 116 * interrupts. Work around this by just ignoring strays. 117 */ 118 #define PCI_STRAY_MAX 0 119 120 /* 121 * Some Miata models, notably models with a Cypress PCI-ISA bridge, have 122 * a PCI device (the OHCI USB controller) with interrupts tied to ISA IRQ 123 * lines. This IRQ is encoded as: line = FLAG | isa_irq. Usually FLAG 124 * is 0xe0, however, it can be 0xf0. We don't allow 0xf0 | irq15. 125 */ 126 #define DEC_550_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xfe) 127 #define DEC_550_LINE_ISA_IRQ(line) ((line) & 0x0f) 128 129 struct alpha_shared_intr *dec_550_pci_intr; 130 131 void dec_550_iointr __P((void *arg, unsigned long vec)); 132 void dec_550_intr_enable __P((int irq)); 133 void dec_550_intr_disable __P((int irq)); 134 135 void 136 pci_550_pickintr(ccp) 137 struct cia_config *ccp; 138 { 139 bus_space_tag_t iot = &ccp->cc_iot; 140 pci_chipset_tag_t pc = &ccp->cc_pc; 141 char *cp; 142 int i; 143 144 pc->pc_intr_v = ccp; 145 pc->pc_intr_map = dec_550_intr_map; 146 pc->pc_intr_string = dec_550_intr_string; 147 pc->pc_intr_evcnt = dec_550_intr_evcnt; 148 pc->pc_intr_establish = dec_550_intr_establish; 149 pc->pc_intr_disestablish = dec_550_intr_disestablish; 150 151 pc->pc_pciide_compat_intr_establish = 152 dec_550_pciide_compat_intr_establish; 153 154 /* 155 * DEC 550's interrupts are enabled via the Pyxis interrupt 156 * mask register. Nothing to map. 157 */ 158 159 for (i = 0; i < DEC_550_MAX_IRQ; i++) 160 dec_550_intr_disable(i); 161 162 dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ, 8); 163 for (i = 0; i < DEC_550_MAX_IRQ; i++) { 164 alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i, 165 PCI_STRAY_MAX); 166 alpha_shared_intr_set_private(dec_550_pci_intr, i, ccp); 167 168 cp = alpha_shared_intr_string(dec_550_pci_intr, i); 169 sprintf(cp, "irq %d", i); 170 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 171 dec_550_pci_intr, i), EVCNT_TYPE_INTR, NULL, 172 "dec_550", cp); 173 } 174 175 #if NSIO 176 sio_intr_setup(pc, iot); 177 #endif 178 } 179 180 int 181 dec_550_intr_map(pa, ihp) 182 struct pci_attach_args *pa; 183 pci_intr_handle_t *ihp; 184 { 185 pcitag_t bustag = pa->pa_intrtag; 186 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 187 pci_chipset_tag_t pc = pa->pa_pc; 188 int bus, device, function; 189 190 if (buspin == 0) { 191 /* No IRQ used. */ 192 return 1; 193 } 194 if (buspin > 4) { 195 printf("dec_550_intr_map: bad interrupt pin %d\n", buspin); 196 return 1; 197 } 198 199 pci_decompose_tag(pc, bustag, &bus, &device, &function); 200 201 /* 202 * There are two main variants of Miata: Miata 1 (Intel SIO) 203 * and Miata {1.5,2} (Cypress). 204 * 205 * The Miata 1 has a CMD PCI IDE wired to compatibility mode at 206 * device 4 of bus 0. This variant apparently also has the 207 * Pyxis DMA bug. 208 * 209 * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives 210 * on device 7 of bus 0. This device has PCI IDE wired to 211 * compatibility mode on functions 1 and 2. 212 * 213 * There will be no interrupt mapping for these devices, so just 214 * bail out now. 215 */ 216 if (bus == 0) { 217 if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 218 /* Miata 1 */ 219 if (device == 7) 220 panic("dec_550_intr_map: SIO device"); 221 else if (device == 4) 222 return (1); 223 } else { 224 /* Miata 1.5 or Miata 2 */ 225 if (device == 7) { 226 if (function == 0) 227 panic("dec_550_intr_map: SIO device"); 228 if (function == 1 || function == 2) 229 return (1); 230 } 231 } 232 } 233 234 /* 235 * The console places the interrupt mapping in the "line" value. 236 * A value of (char)-1 indicates there is no mapping. 237 */ 238 if (line == 0xff) { 239 printf("dec_550_intr_map: no mapping for %d/%d/%d\n", 240 bus, device, function); 241 return (1); 242 } 243 244 #if NSIO == 0 245 if (DEC_550_LINE_IS_ISA(line)) { 246 printf("dec_550_intr_map: ISA IRQ %d for %d/%d/%d\n", 247 DEC_550_LINE_ISA_IRQ(line), bus, device, function); 248 return (1); 249 } 250 #endif 251 252 if (DEC_550_LINE_IS_ISA(line) == 0 && line >= DEC_550_MAX_IRQ) { 253 printf("dec_550_intr_map: irq %d out of range %d/%d/%d\n", 254 line, bus, device, function); 255 return (1); 256 } 257 *ihp = line; 258 return (0); 259 } 260 261 const char * 262 dec_550_intr_string(ccv, ih) 263 void *ccv; 264 pci_intr_handle_t ih; 265 { 266 #if 0 267 struct cia_config *ccp = ccv; 268 #endif 269 static char irqstr[16]; /* 12 + 2 + NULL + sanity */ 270 271 #if NSIO 272 if (DEC_550_LINE_IS_ISA(ih)) 273 return (sio_intr_string(NULL /*XXX*/, 274 DEC_550_LINE_ISA_IRQ(ih))); 275 #endif 276 277 if (ih >= DEC_550_MAX_IRQ) 278 panic("dec_550_intr_string: bogus 550 IRQ 0x%lx\n", ih); 279 sprintf(irqstr, "dec 550 irq %ld", ih); 280 return (irqstr); 281 } 282 283 const struct evcnt * 284 dec_550_intr_evcnt(ccv, ih) 285 void *ccv; 286 pci_intr_handle_t ih; 287 { 288 #if 0 289 struct cia_config *ccp = ccv; 290 #endif 291 292 #if NSIO 293 if (DEC_550_LINE_IS_ISA(ih)) 294 return (sio_intr_evcnt(NULL /*XXX*/, 295 DEC_550_LINE_ISA_IRQ(ih))); 296 #endif 297 298 if (ih >= DEC_550_MAX_IRQ) 299 panic("dec_550_intr_evcnt: bogus 550 IRQ 0x%lx\n", ih); 300 301 return (alpha_shared_intr_evcnt(dec_550_pci_intr, ih)); 302 } 303 304 void * 305 dec_550_intr_establish(ccv, ih, level, func, arg) 306 void *ccv, *arg; 307 pci_intr_handle_t ih; 308 int level; 309 int (*func) __P((void *)); 310 { 311 #if 0 312 struct cia_config *ccp = ccv; 313 #endif 314 void *cookie; 315 316 #if NSIO 317 if (DEC_550_LINE_IS_ISA(ih)) 318 return (sio_intr_establish(NULL /*XXX*/, 319 DEC_550_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg)); 320 #endif 321 322 if (ih >= DEC_550_MAX_IRQ) 323 panic("dec_550_intr_establish: bogus dec 550 IRQ 0x%lx\n", ih); 324 325 cookie = alpha_shared_intr_establish(dec_550_pci_intr, ih, IST_LEVEL, 326 level, func, arg, "dec 550 irq"); 327 328 if (cookie != NULL && 329 alpha_shared_intr_firstactive(dec_550_pci_intr, ih)) { 330 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_550_iointr, NULL); 331 dec_550_intr_enable(ih); 332 } 333 return (cookie); 334 } 335 336 void 337 dec_550_intr_disestablish(ccv, cookie) 338 void *ccv, *cookie; 339 { 340 struct cia_config *ccp = ccv; 341 struct alpha_shared_intrhand *ih = cookie; 342 unsigned int irq = ih->ih_num; 343 int s; 344 345 #if NSIO 346 /* 347 * We have to determine if this is an ISA IRQ or not! We do this 348 * by checking to see if the intrhand points back to an intrhead 349 * that points to our cia_config. If not, it's an ISA IRQ. Pretty 350 * disgusting, eh? 351 */ 352 if (ih->ih_intrhead->intr_private != ccp) { 353 sio_intr_disestablish(NULL /*XXX*/, cookie); 354 return; 355 } 356 #endif 357 358 s = splhigh(); 359 360 alpha_shared_intr_disestablish(dec_550_pci_intr, cookie, 361 "dec 550 irq"); 362 if (alpha_shared_intr_isactive(dec_550_pci_intr, irq) == 0) { 363 dec_550_intr_disable(irq); 364 alpha_shared_intr_set_dfltsharetype(dec_550_pci_intr, irq, 365 IST_NONE); 366 scb_free(0x900 + SCB_IDXTOVEC(irq)); 367 } 368 369 splx(s); 370 } 371 372 void * 373 dec_550_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 374 void *v; 375 struct device *dev; 376 struct pci_attach_args *pa; 377 int chan; 378 int (*func) __P((void *)); 379 void *arg; 380 { 381 pci_chipset_tag_t pc = pa->pa_pc; 382 void *cookie = NULL; 383 int bus, irq; 384 385 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 386 387 /* 388 * If this isn't PCI bus #0, all bets are off. 389 */ 390 if (bus != 0) 391 return (NULL); 392 393 irq = PCIIDE_COMPAT_IRQ(chan); 394 #if NSIO 395 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 396 func, arg); 397 if (cookie == NULL) 398 return (NULL); 399 printf("%s: %s channel interrupting at %s\n", dev->dv_xname, 400 PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq)); 401 #endif 402 return (cookie); 403 } 404 405 void 406 dec_550_iointr(arg, vec) 407 void *arg; 408 unsigned long vec; 409 { 410 int irq; 411 412 irq = SCB_VECTOIDX(vec - 0x900); 413 414 if (irq >= DEC_550_MAX_IRQ) 415 panic("550_iointr: vec 0x%lx out of range\n", vec); 416 417 if (!alpha_shared_intr_dispatch(dec_550_pci_intr, irq)) { 418 alpha_shared_intr_stray(dec_550_pci_intr, irq, 419 "dec 550 irq"); 420 if (ALPHA_SHARED_INTR_DISABLE(dec_550_pci_intr, irq)) 421 dec_550_intr_disable(irq); 422 } 423 } 424 425 void 426 dec_550_intr_enable(irq) 427 int irq; 428 { 429 430 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 1); 431 } 432 433 void 434 dec_550_intr_disable(irq) 435 int irq; 436 { 437 438 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 0); 439 } 440