1 /* $NetBSD: pci_6600.c,v 1.9 2002/05/15 16:57:42 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 by Ross Harvey. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Ross Harvey. 17 * 4. The name of Ross Harvey may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS 21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE 23 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY 24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #include <sys/cdefs.h> 35 36 __KERNEL_RCSID(0, "$NetBSD: pci_6600.c,v 1.9 2002/05/15 16:57:42 thorpej Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/autoconf.h> 47 #define _ALPHA_BUS_DMA_PRIVATE 48 #include <machine/bus.h> 49 #include <machine/rpb.h> 50 #include <machine/alpha.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pciidereg.h> 55 #include <dev/pci/pciidevar.h> 56 57 #include <alpha/pci/tsreg.h> 58 #include <alpha/pci/tsvar.h> 59 #include <alpha/pci/pci_6600.h> 60 61 #define pci_6600() { Generate ctags(1) key. } 62 63 #include "sio.h" 64 #if NSIO 65 #include <alpha/pci/siovar.h> 66 #endif 67 68 #define PCI_NIRQ 64 69 #define PCI_STRAY_MAX 5 70 71 /* 72 * Some Tsunami models have a PCI device (the USB controller) with interrupts 73 * tied to ISA IRQ lines. The IRQ is encoded as: 74 * 75 * line = 0xe0 | isa_irq; 76 */ 77 #define DEC_6600_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xef) 78 #define DEC_6600_LINE_ISA_IRQ(line) ((line) & 0x0f) 79 80 static char *irqtype = "6600 irq"; 81 static struct tsp_config *sioprimary; 82 83 void dec_6600_intr_disestablish __P((void *, void *)); 84 void *dec_6600_intr_establish __P(( 85 void *, pci_intr_handle_t, int, int (*func)(void *), void *)); 86 const char *dec_6600_intr_string __P((void *, pci_intr_handle_t)); 87 const struct evcnt *dec_6600_intr_evcnt __P((void *, pci_intr_handle_t)); 88 int dec_6600_intr_map __P((struct pci_attach_args *, pci_intr_handle_t *)); 89 void *dec_6600_pciide_compat_intr_establish __P((void *, struct device *, 90 struct pci_attach_args *, int, int (*)(void *), void *)); 91 92 struct alpha_shared_intr *dec_6600_pci_intr; 93 94 void dec_6600_iointr __P((void *arg, unsigned long vec)); 95 extern void dec_6600_intr_enable __P((int irq)); 96 extern void dec_6600_intr_disable __P((int irq)); 97 98 void 99 pci_6600_pickintr(pcp) 100 struct tsp_config *pcp; 101 { 102 bus_space_tag_t iot = &pcp->pc_iot; 103 pci_chipset_tag_t pc = &pcp->pc_pc; 104 char *cp; 105 int i; 106 107 pc->pc_intr_v = pcp; 108 pc->pc_intr_map = dec_6600_intr_map; 109 pc->pc_intr_string = dec_6600_intr_string; 110 pc->pc_intr_evcnt = dec_6600_intr_evcnt; 111 pc->pc_intr_establish = dec_6600_intr_establish; 112 pc->pc_intr_disestablish = dec_6600_intr_disestablish; 113 pc->pc_pciide_compat_intr_establish = NULL; 114 115 /* 116 * System-wide and Pchip-0-only logic... 117 */ 118 if (dec_6600_pci_intr == NULL) { 119 sioprimary = pcp; 120 pc->pc_pciide_compat_intr_establish = 121 dec_6600_pciide_compat_intr_establish; 122 dec_6600_pci_intr = alpha_shared_intr_alloc(PCI_NIRQ, 8); 123 for (i = 0; i < PCI_NIRQ; i++) { 124 alpha_shared_intr_set_maxstrays(dec_6600_pci_intr, i, 125 PCI_STRAY_MAX); 126 alpha_shared_intr_set_private(dec_6600_pci_intr, i, 127 sioprimary); 128 129 cp = alpha_shared_intr_string(dec_6600_pci_intr, i); 130 sprintf(cp, "irq %d", i); 131 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 132 dec_6600_pci_intr, 1), EVCNT_TYPE_INTR, NULL, 133 "dec_6600", cp); 134 } 135 #if NSIO 136 sio_intr_setup(pc, iot); 137 dec_6600_intr_enable(55); /* irq line for sio */ 138 #endif 139 } 140 } 141 142 int 143 dec_6600_intr_map(pa, ihp) 144 struct pci_attach_args *pa; 145 pci_intr_handle_t *ihp; 146 { 147 pcitag_t bustag = pa->pa_intrtag; 148 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 149 pci_chipset_tag_t pc = pa->pa_pc; 150 int bus, device, function; 151 152 if (buspin == 0) { 153 /* No IRQ used. */ 154 return 1; 155 } 156 if (buspin > 4) { 157 printf("intr_map: bad interrupt pin %d\n", buspin); 158 return 1; 159 } 160 161 pci_decompose_tag(pc, bustag, &bus, &device, &function); 162 163 /* 164 * The console places the interrupt mapping in the "line" value. 165 * A value of (char)-1 indicates there is no mapping. 166 */ 167 if (line == 0xff) { 168 printf("dec_6600_intr_map: no mapping for %d/%d/%d\n", 169 bus, device, function); 170 return (1); 171 } 172 173 #if NSIO == 0 174 if (DEC_6600_LINE_IS_ISA(line)) { 175 printf("dec_6600_intr_map: ISA IRQ %d for %d/%d/%d\n", 176 DEC_6600_LINE_ISA_IRQ(line), bus, device, function); 177 return (1); 178 } 179 #endif 180 181 if (DEC_6600_LINE_IS_ISA(line) == 0 && line >= PCI_NIRQ) 182 panic("dec_6600_intr_map: dec 6600 irq too large (%d)\n", 183 line); 184 185 *ihp = line; 186 return (0); 187 } 188 189 const char * 190 dec_6600_intr_string(acv, ih) 191 void *acv; 192 pci_intr_handle_t ih; 193 { 194 195 static const char irqfmt[] = "dec 6600 irq %ld"; 196 static char irqstr[sizeof irqfmt]; 197 198 #if NSIO 199 if (DEC_6600_LINE_IS_ISA(ih)) 200 return (sio_intr_string(NULL /*XXX*/, 201 DEC_6600_LINE_ISA_IRQ(ih))); 202 #endif 203 204 snprintf(irqstr, sizeof irqstr, irqfmt, ih); 205 return (irqstr); 206 } 207 208 const struct evcnt * 209 dec_6600_intr_evcnt(acv, ih) 210 void *acv; 211 pci_intr_handle_t ih; 212 { 213 214 #if NSIO 215 if (DEC_6600_LINE_IS_ISA(ih)) 216 return (sio_intr_evcnt(NULL /*XXX*/, 217 DEC_6600_LINE_ISA_IRQ(ih))); 218 #endif 219 220 return (alpha_shared_intr_evcnt(dec_6600_pci_intr, ih)); 221 } 222 223 void * 224 dec_6600_intr_establish(acv, ih, level, func, arg) 225 void *acv, *arg; 226 pci_intr_handle_t ih; 227 int level; 228 int (*func) __P((void *)); 229 { 230 void *cookie; 231 232 #if NSIO 233 if (DEC_6600_LINE_IS_ISA(ih)) 234 return (sio_intr_establish(NULL /*XXX*/, 235 DEC_6600_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg)); 236 #endif 237 238 if (ih >= PCI_NIRQ) 239 panic("dec_6600_intr_establish: bogus dec 6600 IRQ 0x%lx\n", 240 ih); 241 242 cookie = alpha_shared_intr_establish(dec_6600_pci_intr, ih, IST_LEVEL, 243 level, func, arg, irqtype); 244 245 if (cookie != NULL && 246 alpha_shared_intr_firstactive(dec_6600_pci_intr, ih)) { 247 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_6600_iointr, NULL); 248 dec_6600_intr_enable(ih); 249 } 250 return (cookie); 251 } 252 253 void 254 dec_6600_intr_disestablish(acv, cookie) 255 void *acv, *cookie; 256 { 257 struct alpha_shared_intrhand *ih = cookie; 258 unsigned int irq = ih->ih_num; 259 int s; 260 261 #if NSIO 262 /* 263 * We have to determine if this is an ISA IRQ or not! We do this 264 * by checking to see if the intrhand points back to an intrhead 265 * that points to the sioprimary TSP. If not, it's an ISA IRQ. 266 * Pretty disgusting, eh? 267 */ 268 if (ih->ih_intrhead->intr_private != sioprimary) { 269 sio_intr_disestablish(NULL /*XXX*/, cookie); 270 return; 271 } 272 #endif 273 274 s = splhigh(); 275 276 alpha_shared_intr_disestablish(dec_6600_pci_intr, cookie, irqtype); 277 if (alpha_shared_intr_isactive(dec_6600_pci_intr, irq) == 0) { 278 dec_6600_intr_disable(irq); 279 alpha_shared_intr_set_dfltsharetype(dec_6600_pci_intr, irq, 280 IST_NONE); 281 scb_free(0x900 + SCB_IDXTOVEC(irq)); 282 } 283 284 splx(s); 285 } 286 287 void 288 dec_6600_iointr(arg, vec) 289 void *arg; 290 unsigned long vec; 291 { 292 int irq; 293 294 irq = SCB_VECTOIDX(vec - 0x900); 295 296 if (irq >= PCI_NIRQ) 297 panic("iointr: irq %d is too high", irq); 298 299 if (!alpha_shared_intr_dispatch(dec_6600_pci_intr, irq)) { 300 alpha_shared_intr_stray(dec_6600_pci_intr, irq, 301 irqtype); 302 if (ALPHA_SHARED_INTR_DISABLE(dec_6600_pci_intr, irq)) 303 dec_6600_intr_disable(irq); 304 } 305 } 306 307 void 308 dec_6600_intr_enable(irq) 309 int irq; 310 { 311 alpha_mb(); 312 STQP(TS_C_DIM0) |= 1UL << irq; 313 alpha_mb(); 314 } 315 316 void 317 dec_6600_intr_disable(irq) 318 int irq; 319 { 320 alpha_mb(); 321 STQP(TS_C_DIM0) &= ~(1UL << irq); 322 alpha_mb(); 323 } 324 325 void * 326 dec_6600_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 327 void *v; 328 struct device *dev; 329 struct pci_attach_args *pa; 330 int chan; 331 int (*func) __P((void *)); 332 void *arg; 333 { 334 pci_chipset_tag_t pc = pa->pa_pc; 335 void *cookie = NULL; 336 int bus, irq; 337 338 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 339 340 /* 341 * If this isn't PCI bus #0 on the TSP that holds the PCI-ISA 342 * bridge, all bets are off. 343 */ 344 if (bus != 0 || pc->pc_intr_v != sioprimary) 345 return (NULL); 346 347 irq = PCIIDE_COMPAT_IRQ(chan); 348 #if NSIO 349 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 350 func, arg); 351 if (cookie == NULL) 352 return (NULL); 353 printf("%s: %s channel interrupting at %s\n", dev->dv_xname, 354 PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq)); 355 #endif 356 return (cookie); 357 } 358