1 /* $NetBSD: pci_eb164.c,v 1.32 2002/09/27 15:35:38 provos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: pci_eb164.c,v 1.32 2002/09/27 15:35:38 provos Exp $"); 70 71 #include <sys/types.h> 72 #include <sys/param.h> 73 #include <sys/time.h> 74 #include <sys/systm.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/syslog.h> 79 80 #include <uvm/uvm_extern.h> 81 82 #include <machine/autoconf.h> 83 #include <machine/rpb.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pciidereg.h> 88 #include <dev/pci/pciidevar.h> 89 90 #include <alpha/pci/ciareg.h> 91 #include <alpha/pci/ciavar.h> 92 93 #include <alpha/pci/pci_eb164.h> 94 95 #include "sio.h" 96 #if NSIO 97 #include <alpha/pci/siovar.h> 98 #endif 99 100 int dec_eb164_intr_map __P((struct pci_attach_args *, pci_intr_handle_t *)); 101 const char *dec_eb164_intr_string __P((void *, pci_intr_handle_t)); 102 const struct evcnt *dec_eb164_intr_evcnt __P((void *, pci_intr_handle_t)); 103 void *dec_eb164_intr_establish __P((void *, pci_intr_handle_t, 104 int, int (*func)(void *), void *)); 105 void dec_eb164_intr_disestablish __P((void *, void *)); 106 107 void *dec_eb164_pciide_compat_intr_establish __P((void *, struct device *, 108 struct pci_attach_args *, int, int (*)(void *), void *)); 109 110 #define EB164_SIO_IRQ 4 111 #define EB164_MAX_IRQ 24 112 #define PCI_STRAY_MAX 5 113 114 struct alpha_shared_intr *eb164_pci_intr; 115 116 bus_space_tag_t eb164_intrgate_iot; 117 bus_space_handle_t eb164_intrgate_ioh; 118 119 void eb164_iointr __P((void *arg, unsigned long vec)); 120 extern void eb164_intr_enable __P((int irq)); /* pci_eb164_intr.S */ 121 extern void eb164_intr_disable __P((int irq)); /* pci_eb164_intr.S */ 122 123 void 124 pci_eb164_pickintr(ccp) 125 struct cia_config *ccp; 126 { 127 bus_space_tag_t iot = &ccp->cc_iot; 128 pci_chipset_tag_t pc = &ccp->cc_pc; 129 char *cp; 130 int i; 131 132 pc->pc_intr_v = ccp; 133 pc->pc_intr_map = dec_eb164_intr_map; 134 pc->pc_intr_string = dec_eb164_intr_string; 135 pc->pc_intr_evcnt = dec_eb164_intr_evcnt; 136 pc->pc_intr_establish = dec_eb164_intr_establish; 137 pc->pc_intr_disestablish = dec_eb164_intr_disestablish; 138 139 pc->pc_pciide_compat_intr_establish = 140 dec_eb164_pciide_compat_intr_establish; 141 142 eb164_intrgate_iot = iot; 143 if (bus_space_map(eb164_intrgate_iot, 0x804, 3, 0, 144 &eb164_intrgate_ioh) != 0) 145 panic("pci_eb164_pickintr: couldn't map interrupt PLD"); 146 for (i = 0; i < EB164_MAX_IRQ; i++) 147 eb164_intr_disable(i); 148 149 eb164_pci_intr = alpha_shared_intr_alloc(EB164_MAX_IRQ, 8); 150 for (i = 0; i < EB164_MAX_IRQ; i++) { 151 /* 152 * Systems with a Pyxis seem to have problems with 153 * stray interrupts, so just ignore them. Sigh, 154 * I hate buggy hardware. 155 */ 156 alpha_shared_intr_set_maxstrays(eb164_pci_intr, i, 157 (ccp->cc_flags & CCF_ISPYXIS) ? 0 : PCI_STRAY_MAX); 158 159 cp = alpha_shared_intr_string(eb164_pci_intr, i); 160 sprintf(cp, "irq %d", i); 161 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 162 eb164_pci_intr, i), EVCNT_TYPE_INTR, NULL, 163 "eb164", cp); 164 } 165 166 #if NSIO 167 sio_intr_setup(pc, iot); 168 eb164_intr_enable(EB164_SIO_IRQ); 169 #endif 170 } 171 172 int 173 dec_eb164_intr_map(pa, ihp) 174 struct pci_attach_args *pa; 175 pci_intr_handle_t *ihp; 176 { 177 pcitag_t bustag = pa->pa_intrtag; 178 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 179 pci_chipset_tag_t pc = pa->pa_pc; 180 int bus, device, function; 181 u_int64_t variation; 182 183 if (buspin == 0) { 184 /* No IRQ used. */ 185 return 1; 186 } 187 if (buspin > 4) { 188 printf("dec_eb164_intr_map: bad interrupt pin %d\n", buspin); 189 return 1; 190 } 191 192 pci_decompose_tag(pc, bustag, &bus, &device, &function); 193 194 variation = hwrpb->rpb_variation & SV_ST_MASK; 195 196 /* 197 * 198 * The AlphaPC 164 and AlphaPC 164LX have a CMD PCI IDE controller 199 * at bus 0 device 11. These are wired to compatibility mode, 200 * so do not map their interrupts. 201 * 202 * The AlphaPC 164SX has PCI IDE on functions 1 and 2 of the 203 * Cypress PCI-ISA bridge at bus 0 device 8. These, too, are 204 * wired to compatibility mode. 205 * 206 * Real EB164s have ISA IDE on the Super I/O chip. 207 */ 208 if (bus == 0) { 209 if (variation >= SV_ST_ALPHAPC164_366 && 210 variation <= SV_ST_ALPHAPC164LX_600) { 211 if (device == 8) 212 panic("dec_eb164_intr_map: SIO device"); 213 if (device == 11) 214 return (1); 215 } else if (variation >= SV_ST_ALPHAPC164SX_400 && 216 variation <= SV_ST_ALPHAPC164SX_600) { 217 if (device == 8) { 218 if (function == 0) 219 panic("dec_eb164_intr_map: SIO device"); 220 return (1); 221 } 222 } else { 223 if (device == 8) 224 panic("dec_eb164_intr_map: SIO device"); 225 } 226 } 227 228 /* 229 * The console places the interrupt mapping in the "line" value. 230 * A value of (char)-1 indicates there is no mapping. 231 */ 232 if (line == 0xff) { 233 printf("dec_eb164_intr_map: no mapping for %d/%d/%d\n", 234 bus, device, function); 235 return (1); 236 } 237 238 if (line > EB164_MAX_IRQ) 239 panic("dec_eb164_intr_map: eb164 irq too large (%d)", 240 line); 241 242 *ihp = line; 243 return (0); 244 } 245 246 const char * 247 dec_eb164_intr_string(ccv, ih) 248 void *ccv; 249 pci_intr_handle_t ih; 250 { 251 #if 0 252 struct cia_config *ccp = ccv; 253 #endif 254 static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 255 256 if (ih > EB164_MAX_IRQ) 257 panic("dec_eb164_intr_string: bogus eb164 IRQ 0x%lx", ih); 258 sprintf(irqstr, "eb164 irq %ld", ih); 259 return (irqstr); 260 } 261 262 const struct evcnt * 263 dec_eb164_intr_evcnt(ccv, ih) 264 void *ccv; 265 pci_intr_handle_t ih; 266 { 267 #if 0 268 struct cia_config *ccp = ccv; 269 #endif 270 271 if (ih > EB164_MAX_IRQ) 272 panic("dec_eb164_intr_string: bogus eb164 IRQ 0x%lx", ih); 273 return (alpha_shared_intr_evcnt(eb164_pci_intr, ih)); 274 } 275 276 void * 277 dec_eb164_intr_establish(ccv, ih, level, func, arg) 278 void *ccv, *arg; 279 pci_intr_handle_t ih; 280 int level; 281 int (*func) __P((void *)); 282 { 283 #if 0 284 struct cia_config *ccp = ccv; 285 #endif 286 void *cookie; 287 288 if (ih > EB164_MAX_IRQ) 289 panic("dec_eb164_intr_establish: bogus eb164 IRQ 0x%lx", ih); 290 291 cookie = alpha_shared_intr_establish(eb164_pci_intr, ih, IST_LEVEL, 292 level, func, arg, "eb164 irq"); 293 294 if (cookie != NULL && 295 alpha_shared_intr_firstactive(eb164_pci_intr, ih)) { 296 scb_set(0x900 + SCB_IDXTOVEC(ih), eb164_iointr, NULL); 297 eb164_intr_enable(ih); 298 } 299 return (cookie); 300 } 301 302 void 303 dec_eb164_intr_disestablish(ccv, cookie) 304 void *ccv, *cookie; 305 { 306 #if 0 307 struct cia_config *ccp = ccv; 308 #endif 309 struct alpha_shared_intrhand *ih = cookie; 310 unsigned int irq = ih->ih_num; 311 int s; 312 313 s = splhigh(); 314 315 alpha_shared_intr_disestablish(eb164_pci_intr, cookie, 316 "eb164 irq"); 317 if (alpha_shared_intr_isactive(eb164_pci_intr, irq) == 0) { 318 eb164_intr_disable(irq); 319 alpha_shared_intr_set_dfltsharetype(eb164_pci_intr, irq, 320 IST_NONE); 321 scb_free(0x900 + SCB_IDXTOVEC(irq)); 322 } 323 324 splx(s); 325 } 326 327 void * 328 dec_eb164_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 329 void *v; 330 struct device *dev; 331 struct pci_attach_args *pa; 332 int chan; 333 int (*func) __P((void *)); 334 void *arg; 335 { 336 pci_chipset_tag_t pc = pa->pa_pc; 337 void *cookie = NULL; 338 int bus, irq; 339 340 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 341 342 /* 343 * If this isn't PCI bus #0, all bets are off. 344 */ 345 if (bus != 0) 346 return (NULL); 347 348 irq = PCIIDE_COMPAT_IRQ(chan); 349 #if NSIO 350 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 351 func, arg); 352 if (cookie == NULL) 353 return (NULL); 354 printf("%s: %s channel interrupting at %s\n", dev->dv_xname, 355 PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq)); 356 #endif 357 return (cookie); 358 } 359 360 void 361 eb164_iointr(arg, vec) 362 void *arg; 363 unsigned long vec; 364 { 365 int irq; 366 367 irq = SCB_VECTOIDX(vec - 0x900); 368 369 if (!alpha_shared_intr_dispatch(eb164_pci_intr, irq)) { 370 alpha_shared_intr_stray(eb164_pci_intr, irq, 371 "eb164 irq"); 372 if (ALPHA_SHARED_INTR_DISABLE(eb164_pci_intr, irq)) 373 eb164_intr_disable(irq); 374 } 375 } 376 377 #if 0 /* THIS DOES NOT WORK! see pci_eb164_intr.S. */ 378 u_int8_t eb164_intr_mask[3] = { 0xff, 0xff, 0xff }; 379 380 void 381 eb164_intr_enable(irq) 382 int irq; 383 { 384 int byte = (irq / 8), bit = (irq % 8); 385 386 #if 1 387 printf("eb164_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 388 #endif 389 eb164_intr_mask[byte] &= ~(1 << bit); 390 391 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 392 eb164_intr_mask[byte]); 393 } 394 395 void 396 eb164_intr_disable(irq) 397 int irq; 398 { 399 int byte = (irq / 8), bit = (irq % 8); 400 401 #if 1 402 printf("eb164_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 403 #endif 404 eb164_intr_mask[byte] |= (1 << bit); 405 406 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 407 eb164_intr_mask[byte]); 408 } 409 #endif 410