1 /* $NetBSD: pci_swiz_bus_mem_chipdep.c,v 1.43 2009/03/18 07:41:54 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 34 * All rights reserved. 35 * 36 * Author: Chris G. Demetriou 37 * 38 * Permission to use, copy, modify and distribute this software and 39 * its documentation is hereby granted, provided that both the copyright 40 * notice and this permission notice appear in all copies of the 41 * software, derivative works or modified versions, and any portions 42 * thereof, and that both notices appear in supporting documentation. 43 * 44 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 45 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 46 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 47 * 48 * Carnegie Mellon requests users of this software to return to 49 * 50 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 51 * School of Computer Science 52 * Carnegie Mellon University 53 * Pittsburgh PA 15213-3890 54 * 55 * any improvements or extensions that they make and grant Carnegie the 56 * rights to redistribute these changes. 57 */ 58 59 /* 60 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 61 * deal with only a single PCI interface chip in a machine. 62 * 63 * uses: 64 * CHIP name of the 'chip' it's being compiled for. 65 * CHIP_D_MEM_W1_SYS_START Dense Mem space base to use. 66 * CHIP_D_MEM_EX_STORE 67 * If defined, device-provided static storage area 68 * for the dense memory space extent. If this is 69 * defined, CHIP_D_MEM_EX_STORE_SIZE must also be 70 * defined. If this is not defined, a static area 71 * will be declared. 72 * CHIP_D_MEM_EX_STORE_SIZE 73 * Size of the device-provided static storage area 74 * for the dense memory space extent. 75 * CHIP_S_MEM_BASE Sparse Mem space base to use. 76 * CHIP_S_MEM_EX_STORE 77 * If defined, device-provided static storage area 78 * for the sparse memory space extent. If this is 79 * defined, CHIP_S_MEM_EX_STORE_SIZE must also be 80 * defined. If this is not defined, a static area 81 * will be declared. 82 * CHIP_S_MEM_EX_STORE_SIZE 83 * Size of the device-provided static storage area 84 * for the sparse memory space extent. 85 */ 86 87 #include <sys/cdefs.h> 88 __KERNEL_RCSID(1, "$NetBSD: pci_swiz_bus_mem_chipdep.c,v 1.43 2009/03/18 07:41:54 cegger Exp $"); 89 90 #include <sys/extent.h> 91 92 #define __C(A,B) __CONCAT(A,B) 93 #define __S(S) __STRING(S) 94 95 /* mapping/unmapping */ 96 int __C(CHIP,_mem_map)(void *, bus_addr_t, bus_size_t, int, 97 bus_space_handle_t *, int); 98 void __C(CHIP,_mem_unmap)(void *, bus_space_handle_t, 99 bus_size_t, int); 100 int __C(CHIP,_mem_subregion)(void *, bus_space_handle_t, 101 bus_size_t, bus_size_t, bus_space_handle_t *); 102 103 int __C(CHIP,_mem_translate)(void *, bus_addr_t, bus_size_t, 104 int, struct alpha_bus_space_translation *); 105 int __C(CHIP,_mem_get_window)(void *, int, 106 struct alpha_bus_space_translation *); 107 108 /* allocation/deallocation */ 109 int __C(CHIP,_mem_alloc)(void *, bus_addr_t, bus_addr_t, 110 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 111 bus_space_handle_t *); 112 void __C(CHIP,_mem_free)(void *, bus_space_handle_t, 113 bus_size_t); 114 115 /* get kernel virtual address */ 116 void * __C(CHIP,_mem_vaddr)(void *, bus_space_handle_t); 117 118 /* mmap for user */ 119 paddr_t __C(CHIP,_mem_mmap)(void *, bus_addr_t, off_t, int, int); 120 121 /* barrier */ 122 inline void __C(CHIP,_mem_barrier)(void *, bus_space_handle_t, 123 bus_size_t, bus_size_t, int); 124 125 /* read (single) */ 126 inline u_int8_t __C(CHIP,_mem_read_1)(void *, bus_space_handle_t, 127 bus_size_t); 128 inline u_int16_t __C(CHIP,_mem_read_2)(void *, bus_space_handle_t, 129 bus_size_t); 130 inline u_int32_t __C(CHIP,_mem_read_4)(void *, bus_space_handle_t, 131 bus_size_t); 132 inline u_int64_t __C(CHIP,_mem_read_8)(void *, bus_space_handle_t, 133 bus_size_t); 134 135 /* read multiple */ 136 void __C(CHIP,_mem_read_multi_1)(void *, bus_space_handle_t, 137 bus_size_t, u_int8_t *, bus_size_t); 138 void __C(CHIP,_mem_read_multi_2)(void *, bus_space_handle_t, 139 bus_size_t, u_int16_t *, bus_size_t); 140 void __C(CHIP,_mem_read_multi_4)(void *, bus_space_handle_t, 141 bus_size_t, u_int32_t *, bus_size_t); 142 void __C(CHIP,_mem_read_multi_8)(void *, bus_space_handle_t, 143 bus_size_t, u_int64_t *, bus_size_t); 144 145 /* read region */ 146 void __C(CHIP,_mem_read_region_1)(void *, bus_space_handle_t, 147 bus_size_t, u_int8_t *, bus_size_t); 148 void __C(CHIP,_mem_read_region_2)(void *, bus_space_handle_t, 149 bus_size_t, u_int16_t *, bus_size_t); 150 void __C(CHIP,_mem_read_region_4)(void *, bus_space_handle_t, 151 bus_size_t, u_int32_t *, bus_size_t); 152 void __C(CHIP,_mem_read_region_8)(void *, bus_space_handle_t, 153 bus_size_t, u_int64_t *, bus_size_t); 154 155 /* write (single) */ 156 inline void __C(CHIP,_mem_write_1)(void *, bus_space_handle_t, 157 bus_size_t, u_int8_t); 158 inline void __C(CHIP,_mem_write_2)(void *, bus_space_handle_t, 159 bus_size_t, u_int16_t); 160 inline void __C(CHIP,_mem_write_4)(void *, bus_space_handle_t, 161 bus_size_t, u_int32_t); 162 inline void __C(CHIP,_mem_write_8)(void *, bus_space_handle_t, 163 bus_size_t, u_int64_t); 164 165 /* write multiple */ 166 void __C(CHIP,_mem_write_multi_1)(void *, bus_space_handle_t, 167 bus_size_t, const u_int8_t *, bus_size_t); 168 void __C(CHIP,_mem_write_multi_2)(void *, bus_space_handle_t, 169 bus_size_t, const u_int16_t *, bus_size_t); 170 void __C(CHIP,_mem_write_multi_4)(void *, bus_space_handle_t, 171 bus_size_t, const u_int32_t *, bus_size_t); 172 void __C(CHIP,_mem_write_multi_8)(void *, bus_space_handle_t, 173 bus_size_t, const u_int64_t *, bus_size_t); 174 175 /* write region */ 176 void __C(CHIP,_mem_write_region_1)(void *, bus_space_handle_t, 177 bus_size_t, const u_int8_t *, bus_size_t); 178 void __C(CHIP,_mem_write_region_2)(void *, bus_space_handle_t, 179 bus_size_t, const u_int16_t *, bus_size_t); 180 void __C(CHIP,_mem_write_region_4)(void *, bus_space_handle_t, 181 bus_size_t, const u_int32_t *, bus_size_t); 182 void __C(CHIP,_mem_write_region_8)(void *, bus_space_handle_t, 183 bus_size_t, const u_int64_t *, bus_size_t); 184 185 /* set multiple */ 186 void __C(CHIP,_mem_set_multi_1)(void *, bus_space_handle_t, 187 bus_size_t, u_int8_t, bus_size_t); 188 void __C(CHIP,_mem_set_multi_2)(void *, bus_space_handle_t, 189 bus_size_t, u_int16_t, bus_size_t); 190 void __C(CHIP,_mem_set_multi_4)(void *, bus_space_handle_t, 191 bus_size_t, u_int32_t, bus_size_t); 192 void __C(CHIP,_mem_set_multi_8)(void *, bus_space_handle_t, 193 bus_size_t, u_int64_t, bus_size_t); 194 195 /* set region */ 196 void __C(CHIP,_mem_set_region_1)(void *, bus_space_handle_t, 197 bus_size_t, u_int8_t, bus_size_t); 198 void __C(CHIP,_mem_set_region_2)(void *, bus_space_handle_t, 199 bus_size_t, u_int16_t, bus_size_t); 200 void __C(CHIP,_mem_set_region_4)(void *, bus_space_handle_t, 201 bus_size_t, u_int32_t, bus_size_t); 202 void __C(CHIP,_mem_set_region_8)(void *, bus_space_handle_t, 203 bus_size_t, u_int64_t, bus_size_t); 204 205 /* copy */ 206 void __C(CHIP,_mem_copy_region_1)(void *, bus_space_handle_t, 207 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 208 void __C(CHIP,_mem_copy_region_2)(void *, bus_space_handle_t, 209 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 210 void __C(CHIP,_mem_copy_region_4)(void *, bus_space_handle_t, 211 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 212 void __C(CHIP,_mem_copy_region_8)(void *, bus_space_handle_t, 213 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 214 215 #ifdef CHIP_D_MEM_W1_SYS_START 216 #ifndef CHIP_D_MEM_EX_STORE 217 static long 218 __C(CHIP,_dmem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 219 #define CHIP_D_MEM_EX_STORE(v) (__C(CHIP,_dmem_ex_storage)) 220 #define CHIP_D_MEM_EX_STORE_SIZE(v) (sizeof __C(CHIP,_dmem_ex_storage)) 221 #endif 222 #endif /* CHIP_D_MEM_W1_SYS_START */ 223 224 #ifndef CHIP_S_MEM_EX_STORE 225 static long 226 __C(CHIP,_smem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 227 #define CHIP_S_MEM_EX_STORE(v) (__C(CHIP,_smem_ex_storage)) 228 #define CHIP_S_MEM_EX_STORE_SIZE(v) (sizeof __C(CHIP,_smem_ex_storage)) 229 #endif 230 231 #ifndef CHIP_ADDR_SHIFT 232 #define CHIP_ADDR_SHIFT 5 233 #endif 234 235 #ifndef CHIP_SIZE_SHIFT 236 #define CHIP_SIZE_SHIFT 3 237 #endif 238 239 void 240 __C(CHIP,_bus_mem_init)(bus_space_tag_t t, void *v) 241 { 242 #ifdef CHIP_D_MEM_W1_SYS_START 243 struct extent *dex; 244 #endif 245 struct extent *sex; 246 247 /* 248 * Initialize the bus space tag. 249 */ 250 251 /* cookie */ 252 t->abs_cookie = v; 253 254 /* mapping/unmapping */ 255 t->abs_map = __C(CHIP,_mem_map); 256 t->abs_unmap = __C(CHIP,_mem_unmap); 257 t->abs_subregion = __C(CHIP,_mem_subregion); 258 259 t->abs_translate = __C(CHIP,_mem_translate); 260 t->abs_get_window = __C(CHIP,_mem_get_window); 261 262 /* allocation/deallocation */ 263 t->abs_alloc = __C(CHIP,_mem_alloc); 264 t->abs_free = __C(CHIP,_mem_free); 265 266 /* get kernel virtual address */ 267 t->abs_vaddr = __C(CHIP,_mem_vaddr); 268 269 /* mmap for user */ 270 t->abs_mmap = __C(CHIP,_mem_mmap); 271 272 /* barrier */ 273 t->abs_barrier = __C(CHIP,_mem_barrier); 274 275 /* read (single) */ 276 t->abs_r_1 = __C(CHIP,_mem_read_1); 277 t->abs_r_2 = __C(CHIP,_mem_read_2); 278 t->abs_r_4 = __C(CHIP,_mem_read_4); 279 t->abs_r_8 = __C(CHIP,_mem_read_8); 280 281 /* read multiple */ 282 t->abs_rm_1 = __C(CHIP,_mem_read_multi_1); 283 t->abs_rm_2 = __C(CHIP,_mem_read_multi_2); 284 t->abs_rm_4 = __C(CHIP,_mem_read_multi_4); 285 t->abs_rm_8 = __C(CHIP,_mem_read_multi_8); 286 287 /* read region */ 288 t->abs_rr_1 = __C(CHIP,_mem_read_region_1); 289 t->abs_rr_2 = __C(CHIP,_mem_read_region_2); 290 t->abs_rr_4 = __C(CHIP,_mem_read_region_4); 291 t->abs_rr_8 = __C(CHIP,_mem_read_region_8); 292 293 /* write (single) */ 294 t->abs_w_1 = __C(CHIP,_mem_write_1); 295 t->abs_w_2 = __C(CHIP,_mem_write_2); 296 t->abs_w_4 = __C(CHIP,_mem_write_4); 297 t->abs_w_8 = __C(CHIP,_mem_write_8); 298 299 /* write multiple */ 300 t->abs_wm_1 = __C(CHIP,_mem_write_multi_1); 301 t->abs_wm_2 = __C(CHIP,_mem_write_multi_2); 302 t->abs_wm_4 = __C(CHIP,_mem_write_multi_4); 303 t->abs_wm_8 = __C(CHIP,_mem_write_multi_8); 304 305 /* write region */ 306 t->abs_wr_1 = __C(CHIP,_mem_write_region_1); 307 t->abs_wr_2 = __C(CHIP,_mem_write_region_2); 308 t->abs_wr_4 = __C(CHIP,_mem_write_region_4); 309 t->abs_wr_8 = __C(CHIP,_mem_write_region_8); 310 311 /* set multiple */ 312 t->abs_sm_1 = __C(CHIP,_mem_set_multi_1); 313 t->abs_sm_2 = __C(CHIP,_mem_set_multi_2); 314 t->abs_sm_4 = __C(CHIP,_mem_set_multi_4); 315 t->abs_sm_8 = __C(CHIP,_mem_set_multi_8); 316 317 /* set region */ 318 t->abs_sr_1 = __C(CHIP,_mem_set_region_1); 319 t->abs_sr_2 = __C(CHIP,_mem_set_region_2); 320 t->abs_sr_4 = __C(CHIP,_mem_set_region_4); 321 t->abs_sr_8 = __C(CHIP,_mem_set_region_8); 322 323 /* copy */ 324 t->abs_c_1 = __C(CHIP,_mem_copy_region_1); 325 t->abs_c_2 = __C(CHIP,_mem_copy_region_2); 326 t->abs_c_4 = __C(CHIP,_mem_copy_region_4); 327 t->abs_c_8 = __C(CHIP,_mem_copy_region_8); 328 329 #ifdef CHIP_D_MEM_W1_SYS_START 330 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 331 dex = extent_create(__S(__C(CHIP,_bus_dmem)), 0x0UL, 332 0xffffffffffffffffUL, M_DEVBUF, 333 (void *)CHIP_D_MEM_EX_STORE(v), CHIP_D_MEM_EX_STORE_SIZE(v), 334 EX_NOWAIT); 335 extent_alloc_region(dex, 0, 0xffffffffffffffffUL, EX_NOWAIT); 336 337 #ifdef CHIP_D_MEM_W1_BUS_START 338 #ifdef EXTENT_DEBUG 339 printf("dmem: freeing from 0x%lx to 0x%lx\n", 340 CHIP_D_MEM_W1_BUS_START(v), CHIP_D_MEM_W1_BUS_END(v)); 341 #endif 342 extent_free(dex, CHIP_D_MEM_W1_BUS_START(v), 343 CHIP_D_MEM_W1_BUS_END(v) - CHIP_D_MEM_W1_BUS_START(v) + 1, 344 EX_NOWAIT); 345 #endif 346 347 #ifdef EXTENT_DEBUG 348 extent_print(dex); 349 #endif 350 CHIP_D_MEM_EXTENT(v) = dex; 351 #endif /* CHIP_D_MEM_W1_SYS_START */ 352 353 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 354 sex = extent_create(__S(__C(CHIP,_bus_smem)), 0x0UL, 355 0xffffffffffffffffUL, M_DEVBUF, 356 (void *)CHIP_S_MEM_EX_STORE(v), CHIP_S_MEM_EX_STORE_SIZE(v), 357 EX_NOWAIT); 358 extent_alloc_region(sex, 0, 0xffffffffffffffffUL, EX_NOWAIT); 359 360 #ifdef CHIP_S_MEM_W1_BUS_START 361 #ifdef EXTENT_DEBUG 362 printf("smem: freeing from 0x%lx to 0x%lx\n", 363 CHIP_S_MEM_W1_BUS_START(v), CHIP_S_MEM_W1_BUS_END(v)); 364 #endif 365 extent_free(sex, CHIP_S_MEM_W1_BUS_START(v), 366 CHIP_S_MEM_W1_BUS_END(v) - CHIP_S_MEM_W1_BUS_START(v) + 1, 367 EX_NOWAIT); 368 #endif 369 #ifdef CHIP_S_MEM_W2_BUS_START 370 if (CHIP_S_MEM_W2_BUS_START(v) != CHIP_S_MEM_W1_BUS_START(v)) { 371 #ifdef EXTENT_DEBUG 372 printf("smem: freeing from 0x%lx to 0x%lx\n", 373 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v)); 374 #endif 375 extent_free(sex, CHIP_S_MEM_W2_BUS_START(v), 376 CHIP_S_MEM_W2_BUS_END(v) - CHIP_S_MEM_W2_BUS_START(v) + 1, 377 EX_NOWAIT); 378 } else { 379 #ifdef EXTENT_DEBUG 380 printf("smem: window 2 (0x%lx to 0x%lx) overlaps window 1\n", 381 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v)); 382 #endif 383 } 384 #endif 385 #ifdef CHIP_S_MEM_W3_BUS_START 386 if (CHIP_S_MEM_W3_BUS_START(v) != CHIP_S_MEM_W1_BUS_START(v) && 387 CHIP_S_MEM_W3_BUS_START(v) != CHIP_S_MEM_W2_BUS_START(v)) { 388 #ifdef EXTENT_DEBUG 389 printf("smem: freeing from 0x%lx to 0x%lx\n", 390 CHIP_S_MEM_W3_BUS_START(v), CHIP_S_MEM_W3_BUS_END(v)); 391 #endif 392 extent_free(sex, CHIP_S_MEM_W3_BUS_START(v), 393 CHIP_S_MEM_W3_BUS_END(v) - CHIP_S_MEM_W3_BUS_START(v) + 1, 394 EX_NOWAIT); 395 } else { 396 #ifdef EXTENT_DEBUG 397 printf("smem: window 2 (0x%lx to 0x%lx) overlaps window 1\n", 398 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v)); 399 #endif 400 } 401 #endif 402 403 #ifdef EXTENT_DEBUG 404 extent_print(sex); 405 #endif 406 CHIP_S_MEM_EXTENT(v) = sex; 407 } 408 409 #ifdef CHIP_D_MEM_W1_SYS_START 410 static int __C(CHIP,_xlate_addr_to_dense_handle)(void *, 411 bus_addr_t, bus_space_handle_t *); 412 static int __C(CHIP,_xlate_dense_handle_to_addr)(void *, 413 bus_space_handle_t, bus_addr_t *); 414 #endif /* CHIP_D_MEM_W1_SYS_START */ 415 static int __C(CHIP,_xlate_addr_to_sparse_handle)(void *, 416 bus_addr_t, bus_space_handle_t *); 417 static int __C(CHIP,_xlate_sparse_handle_to_addr)(void *, 418 bus_space_handle_t, bus_addr_t *); 419 420 #ifdef CHIP_D_MEM_W1_SYS_START 421 static int 422 __C(CHIP,_xlate_addr_to_dense_handle)(void *v, bus_addr_t memaddr, 423 bus_space_handle_t *memhp) 424 { 425 #ifdef CHIP_D_MEM_W1_BUS_START 426 if (memaddr >= CHIP_D_MEM_W1_BUS_START(v) && 427 memaddr <= CHIP_D_MEM_W1_BUS_END(v)) { 428 if (memhp != NULL) 429 *memhp = 430 ALPHA_PHYS_TO_K0SEG(CHIP_D_MEM_W1_SYS_START(v)) + 431 (memaddr - CHIP_D_MEM_W1_BUS_START(v)); 432 return (1); 433 } else 434 #endif 435 return (0); 436 } 437 438 static int 439 __C(CHIP,_xlate_dense_handle_to_addr)(void *v, bus_space_handle_t memh, 440 bus_addr_t *memaddrp) 441 { 442 443 memh = ALPHA_K0SEG_TO_PHYS(memh); 444 445 #ifdef CHIP_D_MEM_W1_BUS_START 446 if (memh >= CHIP_D_MEM_W1_SYS_START(v) && 447 memh <= CHIP_D_MEM_W1_SYS_END(v)) { 448 *memaddrp = CHIP_D_MEM_W1_BUS_START(v) + 449 (memh - CHIP_D_MEM_W1_SYS_START(v)); 450 return (1); 451 } else 452 #endif 453 return (0); 454 } 455 #endif /* CHIP_D_MEM_W1_SYS_START */ 456 457 static int 458 __C(CHIP,_xlate_addr_to_sparse_handle)(void *v, bus_addr_t memaddr, 459 bus_space_handle_t *memhp) 460 { 461 462 #ifdef CHIP_S_MEM_W1_BUS_START 463 if (memaddr >= CHIP_S_MEM_W1_BUS_START(v) && 464 memaddr <= CHIP_S_MEM_W1_BUS_END(v)) { 465 if (memhp != NULL) 466 *memhp = 467 (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W1_SYS_START(v)) >> 468 CHIP_ADDR_SHIFT) + 469 (memaddr - CHIP_S_MEM_W1_BUS_START(v)); 470 return (1); 471 } else 472 #endif 473 #ifdef CHIP_S_MEM_W2_BUS_START 474 if (memaddr >= CHIP_S_MEM_W2_BUS_START(v) && 475 memaddr <= CHIP_S_MEM_W2_BUS_END(v)) { 476 if (memhp != NULL) 477 *memhp = 478 (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W2_SYS_START(v)) >> 479 CHIP_ADDR_SHIFT) + 480 (memaddr - CHIP_S_MEM_W2_BUS_START(v)); 481 return (1); 482 } else 483 #endif 484 #ifdef CHIP_S_MEM_W3_BUS_START 485 if (memaddr >= CHIP_S_MEM_W3_BUS_START(v) && 486 memaddr <= CHIP_S_MEM_W3_BUS_END(v)) { 487 if (memhp != NULL) 488 *memhp = 489 (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W3_SYS_START(v)) >> 490 CHIP_ADDR_SHIFT) + 491 (memaddr - CHIP_S_MEM_W3_BUS_START(v)); 492 return (1); 493 } else 494 #endif 495 return (0); 496 } 497 498 static int 499 __C(CHIP,_xlate_sparse_handle_to_addr)(void *v, bus_space_handle_t memh, 500 bus_addr_t *memaddrp) 501 { 502 503 memh = ALPHA_K0SEG_TO_PHYS(memh << CHIP_ADDR_SHIFT) >> CHIP_ADDR_SHIFT; 504 505 #ifdef CHIP_S_MEM_W1_BUS_START 506 if ((memh << CHIP_ADDR_SHIFT) >= CHIP_S_MEM_W1_SYS_START(v) && 507 (memh << CHIP_ADDR_SHIFT) <= CHIP_S_MEM_W1_SYS_END(v)) { 508 *memaddrp = CHIP_S_MEM_W1_BUS_START(v) + 509 (memh - (CHIP_S_MEM_W1_SYS_START(v) >> CHIP_ADDR_SHIFT)); 510 return (1); 511 } else 512 #endif 513 #ifdef CHIP_S_MEM_W2_BUS_START 514 if ((memh << CHIP_ADDR_SHIFT) >= CHIP_S_MEM_W2_SYS_START(v) && 515 (memh << CHIP_ADDR_SHIFT) <= CHIP_S_MEM_W2_SYS_END(v)) { 516 *memaddrp = CHIP_S_MEM_W2_BUS_START(v) + 517 (memh - (CHIP_S_MEM_W2_SYS_START(v) >> CHIP_ADDR_SHIFT)); 518 return (1); 519 } else 520 #endif 521 #ifdef CHIP_S_MEM_W3_BUS_START 522 if ((memh << CHIP_ADDR_SHIFT) >= CHIP_S_MEM_W3_SYS_START(v) && 523 (memh << CHIP_ADDR_SHIFT) <= CHIP_S_MEM_W3_SYS_END(v)) { 524 *memaddrp = CHIP_S_MEM_W3_BUS_START(v) + 525 (memh - (CHIP_S_MEM_W3_SYS_START(v) >> CHIP_ADDR_SHIFT)); 526 return (1); 527 } else 528 #endif 529 return (0); 530 } 531 532 int 533 __C(CHIP,_mem_translate)(void *v, bus_addr_t memaddr, bus_size_t memlen, 534 int flags, struct alpha_bus_space_translation *abst) 535 { 536 537 /* XXX */ 538 return (EOPNOTSUPP); 539 } 540 541 int 542 __C(CHIP,_mem_get_window)(void *v, int window, 543 struct alpha_bus_space_translation *abst) 544 { 545 546 #ifdef CHIP_D_MEM_W1_BUS_START 547 #define FIRST_SPARSE 1 548 #else 549 #define FIRST_SPARSE 0 550 #endif 551 552 switch (window) { 553 #ifdef CHIP_D_MEM_W1_BUS_START 554 case 0: 555 abst->abst_bus_start = CHIP_D_MEM_W1_BUS_START(v); 556 abst->abst_bus_end = CHIP_D_MEM_W1_BUS_END(v); 557 abst->abst_sys_start = CHIP_D_MEM_W1_SYS_START(v); 558 abst->abst_sys_end = CHIP_D_MEM_W1_SYS_END(v); 559 abst->abst_addr_shift = 0; 560 abst->abst_size_shift = 0; 561 abst->abst_flags = ABST_DENSE; 562 break; 563 #endif 564 565 #ifdef CHIP_S_MEM_W1_BUS_START 566 case (FIRST_SPARSE): 567 abst->abst_bus_start = CHIP_S_MEM_W1_BUS_START(v); 568 abst->abst_bus_end = CHIP_S_MEM_W1_BUS_END(v); 569 abst->abst_sys_start = CHIP_S_MEM_W1_SYS_START(v); 570 abst->abst_sys_end = CHIP_S_MEM_W1_SYS_END(v); 571 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 572 abst->abst_size_shift = CHIP_SIZE_SHIFT; 573 abst->abst_flags = 0; 574 break; 575 #endif 576 577 #ifdef CHIP_S_MEM_W2_BUS_START 578 case (FIRST_SPARSE + 1): 579 abst->abst_bus_start = CHIP_S_MEM_W2_BUS_START(v); 580 abst->abst_bus_end = CHIP_S_MEM_W2_BUS_END(v); 581 abst->abst_sys_start = CHIP_S_MEM_W2_SYS_START(v); 582 abst->abst_sys_end = CHIP_S_MEM_W2_SYS_END(v); 583 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 584 abst->abst_size_shift = CHIP_SIZE_SHIFT; 585 abst->abst_flags = 0; 586 break; 587 #endif 588 589 #ifdef CHIP_S_MEM_W3_BUS_START 590 case (FIRST_SPARSE + 2): 591 abst->abst_bus_start = CHIP_S_MEM_W3_BUS_START(v); 592 abst->abst_bus_end = CHIP_S_MEM_W3_BUS_END(v); 593 abst->abst_sys_start = CHIP_S_MEM_W3_SYS_START(v); 594 abst->abst_sys_end = CHIP_S_MEM_W3_SYS_END(v); 595 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 596 abst->abst_size_shift = CHIP_SIZE_SHIFT; 597 abst->abst_flags = 0; 598 break; 599 #endif 600 } 601 602 #undef FIRST_SPARSE 603 604 return (0); 605 } 606 607 int 608 __C(CHIP,_mem_map)(void *v, bus_addr_t memaddr, bus_size_t memsize, 609 int flags, bus_space_handle_t *memhp, int acct) 610 { 611 bus_space_handle_t dh = 0, sh = 0; /* XXX -Wuninitialized */ 612 int didd, dids, errord, errors, mustd, musts; 613 int prefectchable = flags & BUS_SPACE_MAP_PREFETCHABLE; 614 int linear = flags & BUS_SPACE_MAP_LINEAR; 615 616 /* 617 * XXX Too hairy to not do accounting in this space. Nothing 618 * XXX much uses this anyhow (only ISA PnP does, and only via 619 * XXX a machine-dependent hook), so we don't have to care. 620 */ 621 if (acct == 0) 622 return (EOPNOTSUPP); 623 624 #ifdef CHIP_D_MEM_W1_SYS_START 625 mustd = 1; 626 if (!__C(CHIP,_xlate_addr_to_dense_handle)(v, memaddr, NULL)) { 627 /* 628 * This address isn't mapped into dense space; don't 629 * require it. 630 */ 631 mustd = 0; 632 } 633 #else 634 mustd = 0; 635 #endif 636 637 /* No prefectchable space without dense. */ 638 if (mustd == 0) 639 prefectchable = 0; 640 641 /* 642 * We must have dense space to map memory linearly. 643 */ 644 if (linear && !prefectchable) 645 return (EOPNOTSUPP); 646 647 musts = (prefectchable == 0); 648 if (!__C(CHIP,_xlate_addr_to_sparse_handle)(v, memaddr, NULL)) { 649 /* 650 * This address isn't mapped into sparse space; don't 651 * require it. 652 */ 653 musts = 0; 654 } 655 656 /* 657 * If this address isn't mapped into dense or sparse, we lose. 658 */ 659 if (mustd == 0 && musts == 0) { 660 #ifdef EXTENT_DEBUG 661 printf("mem: address 0x%lx not in dense or sparse space\n", 662 memaddr); 663 #endif 664 return (EINVAL); 665 } 666 667 #ifdef EXTENT_DEBUG 668 printf("mem: allocating 0x%lx to 0x%lx\n", memaddr, 669 memaddr + memsize - 1); 670 printf("mem: %s dense, %s sparse\n", mustd ? "need" : "want", 671 musts ? "need" : "want"); 672 #endif 673 #ifdef CHIP_D_MEM_W1_SYS_START 674 errord = extent_alloc_region(CHIP_D_MEM_EXTENT(v), memaddr, memsize, 675 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 676 #else 677 errord = EINVAL; 678 #endif 679 didd = (errord == 0); 680 errors = extent_alloc_region(CHIP_S_MEM_EXTENT(v), memaddr, memsize, 681 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 682 dids = (errors == 0); 683 684 #ifdef EXTENT_DEBUG 685 if (!didd) 686 printf("mem: failed to get dense (%d)\n", errord); 687 if (!dids) 688 printf("mem: failed to get sparse (%d)\n", errors); 689 #endif 690 691 if ((mustd && !didd) || (musts && !dids)) 692 goto bad; 693 694 #ifdef CHIP_D_MEM_W1_SYS_START 695 if (didd && !__C(CHIP,_xlate_addr_to_dense_handle)(v, memaddr, &dh)) { 696 printf("\n"); 697 #ifdef CHIP_D_MEM_W1_BUS_START 698 printf("%s: window[1]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)), 699 CHIP_D_MEM_W1_BUS_START(v), CHIP_D_MEM_W1_BUS_END(v)); 700 #endif 701 panic("%s: don't know how to map %lx prefectchable", 702 __S(__C(CHIP,_mem_map)), memaddr); 703 } 704 #endif /* CHIP_D_MEM_W1_SYS_START */ 705 706 if (dids && !__C(CHIP,_xlate_addr_to_sparse_handle)(v, memaddr, &sh)) { 707 printf("\n"); 708 #ifdef CHIP_S_MEM_W1_BUS_START 709 printf("%s: window[1]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)), 710 CHIP_S_MEM_W1_BUS_START(v), CHIP_S_MEM_W1_BUS_END(v)); 711 #endif 712 #ifdef CHIP_S_MEM_W2_BUS_START 713 printf("%s: window[2]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)), 714 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v)); 715 #endif 716 #ifdef CHIP_S_MEM_W3_BUS_START 717 printf("%s: window[3]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)), 718 CHIP_S_MEM_W3_BUS_START(v), CHIP_S_MEM_W3_BUS_END(v)); 719 #endif 720 panic("%s: don't know how to map %lx non-prefectchable", 721 __S(__C(CHIP,_mem_map)), memaddr); 722 } 723 724 if (prefectchable) 725 *memhp = dh; 726 else 727 *memhp = sh; 728 return (0); 729 730 bad: 731 #ifdef EXTENT_DEBUG 732 printf("mem: failed\n"); 733 #endif 734 #ifdef CHIP_D_MEM_W1_SYS_START 735 if (didd) { 736 #ifdef EXTENT_DEBUG 737 printf("mem: freeing dense\n"); 738 #endif 739 if (extent_free(CHIP_D_MEM_EXTENT(v), memaddr, memsize, 740 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)) != 0) { 741 printf("%s: WARNING: couldn't free dense 0x%lx-0x%lx\n", 742 __S(__C(CHIP,_mem_map)), memaddr, 743 memaddr + memsize - 1); 744 } 745 } 746 #endif /* CHIP_D_MEM_W1_SYS_START */ 747 if (dids) { 748 #ifdef EXTENT_DEBUG 749 printf("mem: freeing sparse\n"); 750 #endif 751 if (extent_free(CHIP_S_MEM_EXTENT(v), memaddr, memsize, 752 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)) != 0) { 753 printf("%s: WARNING: couldn't free sparse 0x%lx-0x%lx\n", 754 __S(__C(CHIP,_mem_map)), memaddr, 755 memaddr + memsize - 1); 756 } 757 } 758 759 #ifdef EXTENT_DEBUG 760 #ifdef CHIP_D_MEM_W1_SYS_START 761 extent_print(CHIP_D_MEM_EXTENT(v)); 762 #endif 763 extent_print(CHIP_S_MEM_EXTENT(v)); 764 #endif 765 766 /* 767 * return dense error if we needed it but couldn't get it, else 768 * sparse error. The error _has_ to be one of the two... 769 */ 770 return (mustd && !didd ? errord : (musts && !dids ? errors : EINVAL)); 771 } 772 773 void 774 __C(CHIP,_mem_unmap)(void *v, bus_space_handle_t memh, 775 bus_size_t memsize, int acct) 776 { 777 bus_addr_t memaddr; 778 #ifdef CHIP_D_MEM_W1_SYS_START 779 bus_space_handle_t temph; 780 #endif 781 int sparse, haves, haved; 782 783 if (acct == 0) 784 return; 785 786 #ifdef EXTENT_DEBUG 787 printf("mem: freeing handle 0x%lx for 0x%lx\n", memh, memsize); 788 #endif 789 790 /* 791 * Find out what space we're in. 792 */ 793 sparse = ((memh >> 63) == 0); 794 795 /* 796 * Find out what address we're in in that space. 797 */ 798 haves = haved = 0; 799 if (sparse) 800 haves = __C(CHIP,_xlate_sparse_handle_to_addr)(v, memh, 801 &memaddr); 802 #ifdef CHIP_D_MEM_W1_SYS_START 803 else 804 haved = __C(CHIP,_xlate_dense_handle_to_addr)(v, memh, 805 &memaddr); 806 #endif /* CHIP_D_MEM_W1_SYS_START */ 807 808 if (!haves && !haved) 809 panic("%s: couldn't get addr from %s handle 0x%lx", 810 __S(__C(CHIP,_mem_unmap)), sparse ? "sparse" : "dense", 811 memh); 812 813 #ifdef CHIP_D_MEM_W1_SYS_START 814 /* 815 * Find out were/if that address lives in the other space. 816 */ 817 if (sparse) 818 haved = __C(CHIP,_xlate_addr_to_dense_handle)(v, memaddr, 819 &temph); 820 else 821 haves = __C(CHIP,_xlate_addr_to_sparse_handle)(v, memaddr, 822 &temph); 823 #endif /* CHIP_D_MEM_W1_SYS_START */ 824 825 /* 826 * Free any ranges we have. 827 */ 828 #ifdef EXTENT_DEBUG 829 printf("mem: it's at 0x%lx (%sdense, %ssparse)\n", memaddr, 830 haved ? "" : "not ", haves ? "" : "not "); 831 #endif 832 #ifdef CHIP_D_MEM_W1_SYS_START 833 if (haved && extent_free(CHIP_D_MEM_EXTENT(v), memaddr, memsize, 834 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)) != 0) { 835 printf("%s: WARNING: couldn't free dense 0x%lx-0x%lx\n", 836 __S(__C(CHIP,_mem_map)), memaddr, 837 memaddr + memsize - 1); 838 } 839 #endif 840 if (haves && extent_free(CHIP_S_MEM_EXTENT(v), memaddr, memsize, 841 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)) != 0) { 842 printf("%s: WARNING: couldn't free sparse 0x%lx-0x%lx\n", 843 __S(__C(CHIP,_mem_map)), memaddr, 844 memaddr + memsize - 1); 845 } 846 } 847 848 int 849 __C(CHIP,_mem_subregion)(void *v, bus_space_handle_t memh, 850 bus_size_t offset, bus_size_t size, bus_space_handle_t *nmemh) 851 { 852 853 *nmemh = memh + offset; 854 return (0); 855 } 856 857 int 858 __C(CHIP,_mem_alloc)(void *v, bus_addr_t rstart, bus_addr_t rend, 859 bus_size_t size, bus_size_t align, bus_size_t boundary, int flags, 860 bus_addr_t *addrp, bus_space_handle_t *bshp) 861 { 862 863 /* XXX XXX XXX XXX XXX XXX */ 864 panic("%s not implemented", __S(__C(CHIP,_mem_alloc))); 865 } 866 867 void 868 __C(CHIP,_mem_free)(void *v, bus_space_handle_t bsh, bus_size_t size) 869 { 870 871 /* XXX XXX XXX XXX XXX XXX */ 872 panic("%s not implemented", __S(__C(CHIP,_mem_free))); 873 } 874 875 void * 876 __C(CHIP,_mem_vaddr)(void *v, bus_space_handle_t bsh) 877 { 878 #ifdef CHIP_D_MEM_W1_SYS_START 879 /* 880 * XXX should check that the range was mapped 881 * with BUS_SPACE_MAP_LINEAR for sanity 882 */ 883 if ((bsh >> 63) != 0) 884 return ((void *)bsh); 885 #endif 886 return (0); 887 } 888 889 paddr_t 890 __C(CHIP,_mem_mmap)(void *v, bus_addr_t addr, off_t off, int prot, int flags) 891 { 892 bus_space_handle_t dh = 0, sh = 0; /* XXX -Wuninitialized */ 893 int linear = flags & BUS_SPACE_MAP_LINEAR; 894 int haved = 0, haves = 0; 895 896 #ifdef CHIP_D_MEM_W1_SYS_START 897 if (__C(CHIP,_xlate_addr_to_dense_handle)(v, addr + off, &dh)) { 898 haved = 1; 899 dh = ALPHA_K0SEG_TO_PHYS(dh); 900 } 901 #endif 902 if (__C(CHIP,_xlate_addr_to_sparse_handle)(v, addr + off, &sh)) { 903 haves = 1; 904 sh = ALPHA_K0SEG_TO_PHYS(sh); 905 } 906 907 if (linear) { 908 if (haved == 0) 909 return (-1); 910 return (alpha_btop(dh)); 911 } 912 913 if (haves == 0) 914 return (-1); 915 return (alpha_btop(sh)); 916 } 917 918 inline void 919 __C(CHIP,_mem_barrier)(void *v, bus_space_handle_t h, 920 bus_size_t o, bus_size_t l, int f) 921 { 922 923 if ((f & BUS_SPACE_BARRIER_READ) != 0) 924 alpha_mb(); 925 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 926 alpha_wmb(); 927 } 928 929 inline u_int8_t 930 __C(CHIP,_mem_read_1)(void *v, bus_space_handle_t memh, bus_size_t off) 931 { 932 register bus_space_handle_t tmpmemh; 933 register u_int32_t *port, val; 934 register u_int8_t rval; 935 register int offset; 936 937 alpha_mb(); 938 939 #ifdef CHIP_D_MEM_W1_SYS_START 940 if ((memh >> 63) != 0) 941 return (*(u_int8_t *)(memh + off)); 942 #endif 943 944 tmpmemh = memh + off; 945 offset = tmpmemh & 3; 946 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 947 (0 << CHIP_SIZE_SHIFT)); 948 val = *port; 949 rval = ((val) >> (8 * offset)) & 0xff; 950 951 return rval; 952 } 953 954 inline u_int16_t 955 __C(CHIP,_mem_read_2)(void *v, bus_space_handle_t memh, bus_size_t off) 956 { 957 register bus_space_handle_t tmpmemh; 958 register u_int32_t *port, val; 959 register u_int16_t rval; 960 register int offset; 961 962 alpha_mb(); 963 964 #ifdef CHIP_D_MEM_W1_SYS_START 965 if ((memh >> 63) != 0) 966 return (*(u_int16_t *)(memh + off)); 967 #endif 968 969 tmpmemh = memh + off; 970 offset = tmpmemh & 3; 971 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 972 (1 << CHIP_SIZE_SHIFT)); 973 val = *port; 974 rval = ((val) >> (8 * offset)) & 0xffff; 975 976 return rval; 977 } 978 979 inline u_int32_t 980 __C(CHIP,_mem_read_4)(void *v, bus_space_handle_t memh, bus_size_t off) 981 { 982 register bus_space_handle_t tmpmemh; 983 register u_int32_t *port, val; 984 register u_int32_t rval; 985 register int offset; 986 987 alpha_mb(); 988 989 #ifdef CHIP_D_MEM_W1_SYS_START 990 if ((memh >> 63) != 0) 991 return (*(u_int32_t *)(memh + off)); 992 #endif 993 994 tmpmemh = memh + off; 995 offset = tmpmemh & 3; 996 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 997 (3 << CHIP_SIZE_SHIFT)); 998 val = *port; 999 #if 0 1000 rval = ((val) >> (8 * offset)) & 0xffffffff; 1001 #else 1002 rval = val; 1003 #endif 1004 1005 return rval; 1006 } 1007 1008 inline u_int64_t 1009 __C(CHIP,_mem_read_8)(void *v, bus_space_handle_t memh, bus_size_t off) 1010 { 1011 1012 alpha_mb(); 1013 1014 #ifdef CHIP_D_MEM_W1_SYS_START 1015 if ((memh >> 63) != 0) 1016 return (*(u_int64_t *)(memh + off)); 1017 #endif 1018 1019 /* XXX XXX XXX */ 1020 panic("%s not implemented", __S(__C(CHIP,_mem_read_8))); 1021 } 1022 1023 #define CHIP_mem_read_multi_N(BYTES,TYPE) \ 1024 void \ 1025 __C(__C(CHIP,_mem_read_multi_),BYTES)(void *v, bus_space_handle_t h, bus_size_t o, TYPE *a, bus_size_t c) \ 1026 { \ 1027 \ 1028 while (c-- > 0) { \ 1029 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 1030 BUS_SPACE_BARRIER_READ); \ 1031 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 1032 } \ 1033 } 1034 CHIP_mem_read_multi_N(1,u_int8_t) 1035 CHIP_mem_read_multi_N(2,u_int16_t) 1036 CHIP_mem_read_multi_N(4,u_int32_t) 1037 CHIP_mem_read_multi_N(8,u_int64_t) 1038 1039 #define CHIP_mem_read_region_N(BYTES,TYPE) \ 1040 void \ 1041 __C(__C(CHIP,_mem_read_region_),BYTES)(void *v, bus_space_handle_t h, bus_size_t o, TYPE *a, bus_size_t c) \ 1042 { \ 1043 \ 1044 while (c-- > 0) { \ 1045 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 1046 o += sizeof *a; \ 1047 } \ 1048 } 1049 CHIP_mem_read_region_N(1,u_int8_t) 1050 CHIP_mem_read_region_N(2,u_int16_t) 1051 CHIP_mem_read_region_N(4,u_int32_t) 1052 CHIP_mem_read_region_N(8,u_int64_t) 1053 1054 inline void 1055 __C(CHIP,_mem_write_1)(void *v, bus_space_handle_t memh, bus_size_t off, uint8_t val) 1056 { 1057 register bus_space_handle_t tmpmemh; 1058 register u_int32_t *port, nval; 1059 register int offset; 1060 1061 #ifdef CHIP_D_MEM_W1_SYS_START 1062 if ((memh >> 63) != 0) 1063 (*(u_int8_t *)(memh + off)) = val; 1064 else 1065 #endif 1066 { 1067 tmpmemh = memh + off; 1068 offset = tmpmemh & 3; 1069 nval = val << (8 * offset); 1070 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 1071 (0 << CHIP_SIZE_SHIFT)); 1072 *port = nval; 1073 } 1074 alpha_mb(); 1075 } 1076 1077 inline void 1078 __C(CHIP,_mem_write_2)(void *v, bus_space_handle_t memh, bus_size_t off, uint16_t val) 1079 { 1080 register bus_space_handle_t tmpmemh; 1081 register u_int32_t *port, nval; 1082 register int offset; 1083 1084 #ifdef CHIP_D_MEM_W1_SYS_START 1085 if ((memh >> 63) != 0) 1086 (*(u_int16_t *)(memh + off)) = val; 1087 else 1088 #endif 1089 { 1090 tmpmemh = memh + off; 1091 offset = tmpmemh & 3; 1092 nval = val << (8 * offset); 1093 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 1094 (1 << CHIP_SIZE_SHIFT)); 1095 *port = nval; 1096 } 1097 alpha_mb(); 1098 } 1099 1100 inline void 1101 __C(CHIP,_mem_write_4)(void *v, bus_space_handle_t memh, bus_size_t off, uint32_t val) 1102 { 1103 register bus_space_handle_t tmpmemh; 1104 register u_int32_t *port, nval; 1105 register int offset; 1106 1107 #ifdef CHIP_D_MEM_W1_SYS_START 1108 if ((memh >> 63) != 0) 1109 (*(u_int32_t *)(memh + off)) = val; 1110 else 1111 #endif 1112 { 1113 tmpmemh = memh + off; 1114 offset = tmpmemh & 3; 1115 nval = val /*<< (8 * offset)*/; 1116 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 1117 (3 << CHIP_SIZE_SHIFT)); 1118 *port = nval; 1119 } 1120 alpha_mb(); 1121 } 1122 1123 inline void 1124 __C(CHIP,_mem_write_8)(void *v, bus_space_handle_t memh, bus_size_t off, uint64_t val) 1125 { 1126 1127 #ifdef CHIP_D_MEM_W1_SYS_START 1128 if ((memh >> 63) != 0) 1129 (*(u_int64_t *)(memh + off)) = val; 1130 else 1131 #endif 1132 { 1133 /* XXX XXX XXX */ 1134 panic("%s not implemented", 1135 __S(__C(CHIP,_mem_write_8))); 1136 } 1137 alpha_mb(); 1138 } 1139 1140 #define CHIP_mem_write_multi_N(BYTES,TYPE) \ 1141 void \ 1142 __C(__C(CHIP,_mem_write_multi_),BYTES)(void *v, bus_space_handle_t h, bus_size_t o, const TYPE *a, bus_size_t c) \ 1143 { \ 1144 \ 1145 while (c-- > 0) { \ 1146 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 1147 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 1148 BUS_SPACE_BARRIER_WRITE); \ 1149 } \ 1150 } 1151 CHIP_mem_write_multi_N(1,u_int8_t) 1152 CHIP_mem_write_multi_N(2,u_int16_t) 1153 CHIP_mem_write_multi_N(4,u_int32_t) 1154 CHIP_mem_write_multi_N(8,u_int64_t) 1155 1156 #define CHIP_mem_write_region_N(BYTES,TYPE) \ 1157 void \ 1158 __C(__C(CHIP,_mem_write_region_),BYTES)(void *v, bus_space_handle_t h, bus_size_t o, const TYPE *a, bus_size_t c) \ 1159 { \ 1160 \ 1161 while (c-- > 0) { \ 1162 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 1163 o += sizeof *a; \ 1164 } \ 1165 } 1166 CHIP_mem_write_region_N(1,u_int8_t) 1167 CHIP_mem_write_region_N(2,u_int16_t) 1168 CHIP_mem_write_region_N(4,u_int32_t) 1169 CHIP_mem_write_region_N(8,u_int64_t) 1170 1171 #define CHIP_mem_set_multi_N(BYTES,TYPE) \ 1172 void \ 1173 __C(__C(CHIP,_mem_set_multi_),BYTES)(void *v, bus_space_handle_t h, bus_size_t o, TYPE val, bus_size_t c) \ 1174 { \ 1175 \ 1176 while (c-- > 0) { \ 1177 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 1178 __C(CHIP,_mem_barrier)(v, h, o, sizeof val, \ 1179 BUS_SPACE_BARRIER_WRITE); \ 1180 } \ 1181 } 1182 CHIP_mem_set_multi_N(1,u_int8_t) 1183 CHIP_mem_set_multi_N(2,u_int16_t) 1184 CHIP_mem_set_multi_N(4,u_int32_t) 1185 CHIP_mem_set_multi_N(8,u_int64_t) 1186 1187 #define CHIP_mem_set_region_N(BYTES,TYPE) \ 1188 void \ 1189 __C(__C(CHIP,_mem_set_region_),BYTES)(void *v, bus_space_handle_t h, bus_size_t o, TYPE val, bus_size_t c) \ 1190 { \ 1191 \ 1192 while (c-- > 0) { \ 1193 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 1194 o += sizeof val; \ 1195 } \ 1196 } 1197 CHIP_mem_set_region_N(1,u_int8_t) 1198 CHIP_mem_set_region_N(2,u_int16_t) 1199 CHIP_mem_set_region_N(4,u_int32_t) 1200 CHIP_mem_set_region_N(8,u_int64_t) 1201 1202 #define CHIP_mem_copy_region_N(BYTES) \ 1203 void \ 1204 __C(__C(CHIP,_mem_copy_region_),BYTES)(void *v, bus_space_handle_t h1, bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c) \ 1205 { \ 1206 bus_size_t o; \ 1207 \ 1208 if ((h1 >> 63) != 0 && (h2 >> 63) != 0) { \ 1209 memmove((void *)(h2 + o2), (void *)(h1 + o1), c * BYTES); \ 1210 return; \ 1211 } \ 1212 \ 1213 if ((h1 + o1) >= (h2 + o2)) { \ 1214 /* src after dest: copy forward */ \ 1215 for (o = 0; c != 0; c--, o += BYTES) \ 1216 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 1217 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 1218 } else { \ 1219 /* dest after src: copy backwards */ \ 1220 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \ 1221 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 1222 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 1223 } \ 1224 } 1225 CHIP_mem_copy_region_N(1) 1226 CHIP_mem_copy_region_N(2) 1227 CHIP_mem_copy_region_N(4) 1228 CHIP_mem_copy_region_N(8) 1229