1 /* $NetBSD: pci_swiz_bus_mem_chipdep.c,v 1.37 2002/07/22 20:05:23 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 41 * All rights reserved. 42 * 43 * Author: Chris G. Demetriou 44 * 45 * Permission to use, copy, modify and distribute this software and 46 * its documentation is hereby granted, provided that both the copyright 47 * notice and this permission notice appear in all copies of the 48 * software, derivative works or modified versions, and any portions 49 * thereof, and that both notices appear in supporting documentation. 50 * 51 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 52 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 53 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 54 * 55 * Carnegie Mellon requests users of this software to return to 56 * 57 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 58 * School of Computer Science 59 * Carnegie Mellon University 60 * Pittsburgh PA 15213-3890 61 * 62 * any improvements or extensions that they make and grant Carnegie the 63 * rights to redistribute these changes. 64 */ 65 66 /* 67 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 68 * deal with only a single PCI interface chip in a machine. 69 * 70 * uses: 71 * CHIP name of the 'chip' it's being compiled for. 72 * CHIP_D_MEM_W1_SYS_START Dense Mem space base to use. 73 * CHIP_D_MEM_EX_STORE 74 * If defined, device-provided static storage area 75 * for the dense memory space extent. If this is 76 * defined, CHIP_D_MEM_EX_STORE_SIZE must also be 77 * defined. If this is not defined, a static area 78 * will be declared. 79 * CHIP_D_MEM_EX_STORE_SIZE 80 * Size of the device-provided static storage area 81 * for the dense memory space extent. 82 * CHIP_S_MEM_BASE Sparse Mem space base to use. 83 * CHIP_S_MEM_EX_STORE 84 * If defined, device-provided static storage area 85 * for the sparse memory space extent. If this is 86 * defined, CHIP_S_MEM_EX_STORE_SIZE must also be 87 * defined. If this is not defined, a static area 88 * will be declared. 89 * CHIP_S_MEM_EX_STORE_SIZE 90 * Size of the device-provided static storage area 91 * for the sparse memory space extent. 92 */ 93 94 #include <sys/extent.h> 95 96 #define __C(A,B) __CONCAT(A,B) 97 #define __S(S) __STRING(S) 98 99 /* mapping/unmapping */ 100 int __C(CHIP,_mem_map) __P((void *, bus_addr_t, bus_size_t, int, 101 bus_space_handle_t *, int)); 102 void __C(CHIP,_mem_unmap) __P((void *, bus_space_handle_t, 103 bus_size_t, int)); 104 int __C(CHIP,_mem_subregion) __P((void *, bus_space_handle_t, 105 bus_size_t, bus_size_t, bus_space_handle_t *)); 106 107 int __C(CHIP,_mem_translate) __P((void *, bus_addr_t, bus_size_t, 108 int, struct alpha_bus_space_translation *)); 109 int __C(CHIP,_mem_get_window) __P((void *, int, 110 struct alpha_bus_space_translation *)); 111 112 /* allocation/deallocation */ 113 int __C(CHIP,_mem_alloc) __P((void *, bus_addr_t, bus_addr_t, 114 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 115 bus_space_handle_t *)); 116 void __C(CHIP,_mem_free) __P((void *, bus_space_handle_t, 117 bus_size_t)); 118 119 /* get kernel virtual address */ 120 void * __C(CHIP,_mem_vaddr) __P((void *, bus_space_handle_t)); 121 122 /* mmap for user */ 123 paddr_t __C(CHIP,_mem_mmap) __P((void *, bus_addr_t, off_t, int, int)); 124 125 /* barrier */ 126 inline void __C(CHIP,_mem_barrier) __P((void *, bus_space_handle_t, 127 bus_size_t, bus_size_t, int)); 128 129 /* read (single) */ 130 inline u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_space_handle_t, 131 bus_size_t)); 132 inline u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_space_handle_t, 133 bus_size_t)); 134 inline u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_space_handle_t, 135 bus_size_t)); 136 inline u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_space_handle_t, 137 bus_size_t)); 138 139 /* read multiple */ 140 void __C(CHIP,_mem_read_multi_1) __P((void *, bus_space_handle_t, 141 bus_size_t, u_int8_t *, bus_size_t)); 142 void __C(CHIP,_mem_read_multi_2) __P((void *, bus_space_handle_t, 143 bus_size_t, u_int16_t *, bus_size_t)); 144 void __C(CHIP,_mem_read_multi_4) __P((void *, bus_space_handle_t, 145 bus_size_t, u_int32_t *, bus_size_t)); 146 void __C(CHIP,_mem_read_multi_8) __P((void *, bus_space_handle_t, 147 bus_size_t, u_int64_t *, bus_size_t)); 148 149 /* read region */ 150 void __C(CHIP,_mem_read_region_1) __P((void *, bus_space_handle_t, 151 bus_size_t, u_int8_t *, bus_size_t)); 152 void __C(CHIP,_mem_read_region_2) __P((void *, bus_space_handle_t, 153 bus_size_t, u_int16_t *, bus_size_t)); 154 void __C(CHIP,_mem_read_region_4) __P((void *, bus_space_handle_t, 155 bus_size_t, u_int32_t *, bus_size_t)); 156 void __C(CHIP,_mem_read_region_8) __P((void *, bus_space_handle_t, 157 bus_size_t, u_int64_t *, bus_size_t)); 158 159 /* write (single) */ 160 inline void __C(CHIP,_mem_write_1) __P((void *, bus_space_handle_t, 161 bus_size_t, u_int8_t)); 162 inline void __C(CHIP,_mem_write_2) __P((void *, bus_space_handle_t, 163 bus_size_t, u_int16_t)); 164 inline void __C(CHIP,_mem_write_4) __P((void *, bus_space_handle_t, 165 bus_size_t, u_int32_t)); 166 inline void __C(CHIP,_mem_write_8) __P((void *, bus_space_handle_t, 167 bus_size_t, u_int64_t)); 168 169 /* write multiple */ 170 void __C(CHIP,_mem_write_multi_1) __P((void *, bus_space_handle_t, 171 bus_size_t, const u_int8_t *, bus_size_t)); 172 void __C(CHIP,_mem_write_multi_2) __P((void *, bus_space_handle_t, 173 bus_size_t, const u_int16_t *, bus_size_t)); 174 void __C(CHIP,_mem_write_multi_4) __P((void *, bus_space_handle_t, 175 bus_size_t, const u_int32_t *, bus_size_t)); 176 void __C(CHIP,_mem_write_multi_8) __P((void *, bus_space_handle_t, 177 bus_size_t, const u_int64_t *, bus_size_t)); 178 179 /* write region */ 180 void __C(CHIP,_mem_write_region_1) __P((void *, bus_space_handle_t, 181 bus_size_t, const u_int8_t *, bus_size_t)); 182 void __C(CHIP,_mem_write_region_2) __P((void *, bus_space_handle_t, 183 bus_size_t, const u_int16_t *, bus_size_t)); 184 void __C(CHIP,_mem_write_region_4) __P((void *, bus_space_handle_t, 185 bus_size_t, const u_int32_t *, bus_size_t)); 186 void __C(CHIP,_mem_write_region_8) __P((void *, bus_space_handle_t, 187 bus_size_t, const u_int64_t *, bus_size_t)); 188 189 /* set multiple */ 190 void __C(CHIP,_mem_set_multi_1) __P((void *, bus_space_handle_t, 191 bus_size_t, u_int8_t, bus_size_t)); 192 void __C(CHIP,_mem_set_multi_2) __P((void *, bus_space_handle_t, 193 bus_size_t, u_int16_t, bus_size_t)); 194 void __C(CHIP,_mem_set_multi_4) __P((void *, bus_space_handle_t, 195 bus_size_t, u_int32_t, bus_size_t)); 196 void __C(CHIP,_mem_set_multi_8) __P((void *, bus_space_handle_t, 197 bus_size_t, u_int64_t, bus_size_t)); 198 199 /* set region */ 200 void __C(CHIP,_mem_set_region_1) __P((void *, bus_space_handle_t, 201 bus_size_t, u_int8_t, bus_size_t)); 202 void __C(CHIP,_mem_set_region_2) __P((void *, bus_space_handle_t, 203 bus_size_t, u_int16_t, bus_size_t)); 204 void __C(CHIP,_mem_set_region_4) __P((void *, bus_space_handle_t, 205 bus_size_t, u_int32_t, bus_size_t)); 206 void __C(CHIP,_mem_set_region_8) __P((void *, bus_space_handle_t, 207 bus_size_t, u_int64_t, bus_size_t)); 208 209 /* copy */ 210 void __C(CHIP,_mem_copy_region_1) __P((void *, bus_space_handle_t, 211 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 212 void __C(CHIP,_mem_copy_region_2) __P((void *, bus_space_handle_t, 213 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 214 void __C(CHIP,_mem_copy_region_4) __P((void *, bus_space_handle_t, 215 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 216 void __C(CHIP,_mem_copy_region_8) __P((void *, bus_space_handle_t, 217 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 218 219 #ifdef CHIP_D_MEM_W1_SYS_START 220 #ifndef CHIP_D_MEM_EX_STORE 221 static long 222 __C(CHIP,_dmem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 223 #define CHIP_D_MEM_EX_STORE(v) (__C(CHIP,_dmem_ex_storage)) 224 #define CHIP_D_MEM_EX_STORE_SIZE(v) (sizeof __C(CHIP,_dmem_ex_storage)) 225 #endif 226 #endif /* CHIP_D_MEM_W1_SYS_START */ 227 228 #ifndef CHIP_S_MEM_EX_STORE 229 static long 230 __C(CHIP,_smem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 231 #define CHIP_S_MEM_EX_STORE(v) (__C(CHIP,_smem_ex_storage)) 232 #define CHIP_S_MEM_EX_STORE_SIZE(v) (sizeof __C(CHIP,_smem_ex_storage)) 233 #endif 234 235 #ifndef CHIP_ADDR_SHIFT 236 #define CHIP_ADDR_SHIFT 5 237 #endif 238 239 #ifndef CHIP_SIZE_SHIFT 240 #define CHIP_SIZE_SHIFT 3 241 #endif 242 243 void 244 __C(CHIP,_bus_mem_init)(t, v) 245 bus_space_tag_t t; 246 void *v; 247 { 248 #ifdef CHIP_D_MEM_W1_SYS_START 249 struct extent *dex; 250 #endif 251 struct extent *sex; 252 253 /* 254 * Initialize the bus space tag. 255 */ 256 257 /* cookie */ 258 t->abs_cookie = v; 259 260 /* mapping/unmapping */ 261 t->abs_map = __C(CHIP,_mem_map); 262 t->abs_unmap = __C(CHIP,_mem_unmap); 263 t->abs_subregion = __C(CHIP,_mem_subregion); 264 265 t->abs_translate = __C(CHIP,_mem_translate); 266 t->abs_get_window = __C(CHIP,_mem_get_window); 267 268 /* allocation/deallocation */ 269 t->abs_alloc = __C(CHIP,_mem_alloc); 270 t->abs_free = __C(CHIP,_mem_free); 271 272 /* get kernel virtual address */ 273 t->abs_vaddr = __C(CHIP,_mem_vaddr); 274 275 /* mmap for user */ 276 t->abs_mmap = __C(CHIP,_mem_mmap); 277 278 /* barrier */ 279 t->abs_barrier = __C(CHIP,_mem_barrier); 280 281 /* read (single) */ 282 t->abs_r_1 = __C(CHIP,_mem_read_1); 283 t->abs_r_2 = __C(CHIP,_mem_read_2); 284 t->abs_r_4 = __C(CHIP,_mem_read_4); 285 t->abs_r_8 = __C(CHIP,_mem_read_8); 286 287 /* read multiple */ 288 t->abs_rm_1 = __C(CHIP,_mem_read_multi_1); 289 t->abs_rm_2 = __C(CHIP,_mem_read_multi_2); 290 t->abs_rm_4 = __C(CHIP,_mem_read_multi_4); 291 t->abs_rm_8 = __C(CHIP,_mem_read_multi_8); 292 293 /* read region */ 294 t->abs_rr_1 = __C(CHIP,_mem_read_region_1); 295 t->abs_rr_2 = __C(CHIP,_mem_read_region_2); 296 t->abs_rr_4 = __C(CHIP,_mem_read_region_4); 297 t->abs_rr_8 = __C(CHIP,_mem_read_region_8); 298 299 /* write (single) */ 300 t->abs_w_1 = __C(CHIP,_mem_write_1); 301 t->abs_w_2 = __C(CHIP,_mem_write_2); 302 t->abs_w_4 = __C(CHIP,_mem_write_4); 303 t->abs_w_8 = __C(CHIP,_mem_write_8); 304 305 /* write multiple */ 306 t->abs_wm_1 = __C(CHIP,_mem_write_multi_1); 307 t->abs_wm_2 = __C(CHIP,_mem_write_multi_2); 308 t->abs_wm_4 = __C(CHIP,_mem_write_multi_4); 309 t->abs_wm_8 = __C(CHIP,_mem_write_multi_8); 310 311 /* write region */ 312 t->abs_wr_1 = __C(CHIP,_mem_write_region_1); 313 t->abs_wr_2 = __C(CHIP,_mem_write_region_2); 314 t->abs_wr_4 = __C(CHIP,_mem_write_region_4); 315 t->abs_wr_8 = __C(CHIP,_mem_write_region_8); 316 317 /* set multiple */ 318 t->abs_sm_1 = __C(CHIP,_mem_set_multi_1); 319 t->abs_sm_2 = __C(CHIP,_mem_set_multi_2); 320 t->abs_sm_4 = __C(CHIP,_mem_set_multi_4); 321 t->abs_sm_8 = __C(CHIP,_mem_set_multi_8); 322 323 /* set region */ 324 t->abs_sr_1 = __C(CHIP,_mem_set_region_1); 325 t->abs_sr_2 = __C(CHIP,_mem_set_region_2); 326 t->abs_sr_4 = __C(CHIP,_mem_set_region_4); 327 t->abs_sr_8 = __C(CHIP,_mem_set_region_8); 328 329 /* copy */ 330 t->abs_c_1 = __C(CHIP,_mem_copy_region_1); 331 t->abs_c_2 = __C(CHIP,_mem_copy_region_2); 332 t->abs_c_4 = __C(CHIP,_mem_copy_region_4); 333 t->abs_c_8 = __C(CHIP,_mem_copy_region_8); 334 335 #ifdef CHIP_D_MEM_W1_SYS_START 336 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 337 dex = extent_create(__S(__C(CHIP,_bus_dmem)), 0x0UL, 338 0xffffffffffffffffUL, M_DEVBUF, 339 (caddr_t)CHIP_D_MEM_EX_STORE(v), CHIP_D_MEM_EX_STORE_SIZE(v), 340 EX_NOWAIT); 341 extent_alloc_region(dex, 0, 0xffffffffffffffffUL, EX_NOWAIT); 342 343 #ifdef CHIP_D_MEM_W1_BUS_START 344 #ifdef EXTENT_DEBUG 345 printf("dmem: freeing from 0x%lx to 0x%lx\n", 346 CHIP_D_MEM_W1_BUS_START(v), CHIP_D_MEM_W1_BUS_END(v)); 347 #endif 348 extent_free(dex, CHIP_D_MEM_W1_BUS_START(v), 349 CHIP_D_MEM_W1_BUS_END(v) - CHIP_D_MEM_W1_BUS_START(v) + 1, 350 EX_NOWAIT); 351 #endif 352 353 #ifdef EXTENT_DEBUG 354 extent_print(dex); 355 #endif 356 CHIP_D_MEM_EXTENT(v) = dex; 357 #endif /* CHIP_D_MEM_W1_SYS_START */ 358 359 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 360 sex = extent_create(__S(__C(CHIP,_bus_smem)), 0x0UL, 361 0xffffffffffffffffUL, M_DEVBUF, 362 (caddr_t)CHIP_S_MEM_EX_STORE(v), CHIP_S_MEM_EX_STORE_SIZE(v), 363 EX_NOWAIT); 364 extent_alloc_region(sex, 0, 0xffffffffffffffffUL, EX_NOWAIT); 365 366 #ifdef CHIP_S_MEM_W1_BUS_START 367 #ifdef EXTENT_DEBUG 368 printf("smem: freeing from 0x%lx to 0x%lx\n", 369 CHIP_S_MEM_W1_BUS_START(v), CHIP_S_MEM_W1_BUS_END(v)); 370 #endif 371 extent_free(sex, CHIP_S_MEM_W1_BUS_START(v), 372 CHIP_S_MEM_W1_BUS_END(v) - CHIP_S_MEM_W1_BUS_START(v) + 1, 373 EX_NOWAIT); 374 #endif 375 #ifdef CHIP_S_MEM_W2_BUS_START 376 if (CHIP_S_MEM_W2_BUS_START(v) != CHIP_S_MEM_W1_BUS_START(v)) { 377 #ifdef EXTENT_DEBUG 378 printf("smem: freeing from 0x%lx to 0x%lx\n", 379 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v)); 380 #endif 381 extent_free(sex, CHIP_S_MEM_W2_BUS_START(v), 382 CHIP_S_MEM_W2_BUS_END(v) - CHIP_S_MEM_W2_BUS_START(v) + 1, 383 EX_NOWAIT); 384 } else { 385 #ifdef EXTENT_DEBUG 386 printf("smem: window 2 (0x%lx to 0x%lx) overlaps window 1\n", 387 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v)); 388 #endif 389 } 390 #endif 391 #ifdef CHIP_S_MEM_W3_BUS_START 392 if (CHIP_S_MEM_W3_BUS_START(v) != CHIP_S_MEM_W1_BUS_START(v) && 393 CHIP_S_MEM_W3_BUS_START(v) != CHIP_S_MEM_W2_BUS_START(v)) { 394 #ifdef EXTENT_DEBUG 395 printf("smem: freeing from 0x%lx to 0x%lx\n", 396 CHIP_S_MEM_W3_BUS_START(v), CHIP_S_MEM_W3_BUS_END(v)); 397 #endif 398 extent_free(sex, CHIP_S_MEM_W3_BUS_START(v), 399 CHIP_S_MEM_W3_BUS_END(v) - CHIP_S_MEM_W3_BUS_START(v) + 1, 400 EX_NOWAIT); 401 } else { 402 #ifdef EXTENT_DEBUG 403 printf("smem: window 2 (0x%lx to 0x%lx) overlaps window 1\n", 404 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v)); 405 #endif 406 } 407 #endif 408 409 #ifdef EXTENT_DEBUG 410 extent_print(sex); 411 #endif 412 CHIP_S_MEM_EXTENT(v) = sex; 413 } 414 415 #ifdef CHIP_D_MEM_W1_SYS_START 416 static int __C(CHIP,_xlate_addr_to_dense_handle) __P((void *, 417 bus_addr_t, bus_space_handle_t *)); 418 static int __C(CHIP,_xlate_dense_handle_to_addr) __P((void *, 419 bus_space_handle_t, bus_addr_t *)); 420 #endif /* CHIP_D_MEM_W1_SYS_START */ 421 static int __C(CHIP,_xlate_addr_to_sparse_handle) __P((void *, 422 bus_addr_t, bus_space_handle_t *)); 423 static int __C(CHIP,_xlate_sparse_handle_to_addr) __P((void *, 424 bus_space_handle_t, bus_addr_t *)); 425 426 #ifdef CHIP_D_MEM_W1_SYS_START 427 static int 428 __C(CHIP,_xlate_addr_to_dense_handle)(v, memaddr, memhp) 429 void *v; 430 bus_addr_t memaddr; 431 bus_space_handle_t *memhp; 432 { 433 #ifdef CHIP_D_MEM_W1_BUS_START 434 if (memaddr >= CHIP_D_MEM_W1_BUS_START(v) && 435 memaddr <= CHIP_D_MEM_W1_BUS_END(v)) { 436 if (memhp != NULL) 437 *memhp = 438 ALPHA_PHYS_TO_K0SEG(CHIP_D_MEM_W1_SYS_START(v)) + 439 (memaddr - CHIP_D_MEM_W1_BUS_START(v)); 440 return (1); 441 } else 442 #endif 443 return (0); 444 } 445 446 static int 447 __C(CHIP,_xlate_dense_handle_to_addr)(v, memh, memaddrp) 448 void *v; 449 bus_space_handle_t memh; 450 bus_addr_t *memaddrp; 451 { 452 453 memh = ALPHA_K0SEG_TO_PHYS(memh); 454 455 #ifdef CHIP_D_MEM_W1_BUS_START 456 if (memh >= CHIP_D_MEM_W1_SYS_START(v) && 457 memh <= CHIP_D_MEM_W1_SYS_END(v)) { 458 *memaddrp = CHIP_D_MEM_W1_BUS_START(v) + 459 (memh - CHIP_D_MEM_W1_SYS_START(v)); 460 return (1); 461 } else 462 #endif 463 return (0); 464 } 465 #endif /* CHIP_D_MEM_W1_SYS_START */ 466 467 static int 468 __C(CHIP,_xlate_addr_to_sparse_handle)(v, memaddr, memhp) 469 void *v; 470 bus_addr_t memaddr; 471 bus_space_handle_t *memhp; 472 { 473 474 #ifdef CHIP_S_MEM_W1_BUS_START 475 if (memaddr >= CHIP_S_MEM_W1_BUS_START(v) && 476 memaddr <= CHIP_S_MEM_W1_BUS_END(v)) { 477 if (memhp != NULL) 478 *memhp = 479 (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W1_SYS_START(v)) >> 480 CHIP_ADDR_SHIFT) + 481 (memaddr - CHIP_S_MEM_W1_BUS_START(v)); 482 return (1); 483 } else 484 #endif 485 #ifdef CHIP_S_MEM_W2_BUS_START 486 if (memaddr >= CHIP_S_MEM_W2_BUS_START(v) && 487 memaddr <= CHIP_S_MEM_W2_BUS_END(v)) { 488 if (memhp != NULL) 489 *memhp = 490 (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W2_SYS_START(v)) >> 491 CHIP_ADDR_SHIFT) + 492 (memaddr - CHIP_S_MEM_W2_BUS_START(v)); 493 return (1); 494 } else 495 #endif 496 #ifdef CHIP_S_MEM_W3_BUS_START 497 if (memaddr >= CHIP_S_MEM_W3_BUS_START(v) && 498 memaddr <= CHIP_S_MEM_W3_BUS_END(v)) { 499 if (memhp != NULL) 500 *memhp = 501 (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W3_SYS_START(v)) >> 502 CHIP_ADDR_SHIFT) + 503 (memaddr - CHIP_S_MEM_W3_BUS_START(v)); 504 return (1); 505 } else 506 #endif 507 return (0); 508 } 509 510 static int 511 __C(CHIP,_xlate_sparse_handle_to_addr)(v, memh, memaddrp) 512 void *v; 513 bus_space_handle_t memh; 514 bus_addr_t *memaddrp; 515 { 516 517 memh = ALPHA_K0SEG_TO_PHYS(memh << CHIP_ADDR_SHIFT) >> CHIP_ADDR_SHIFT; 518 519 #ifdef CHIP_S_MEM_W1_BUS_START 520 if ((memh << CHIP_ADDR_SHIFT) >= CHIP_S_MEM_W1_SYS_START(v) && 521 (memh << CHIP_ADDR_SHIFT) <= CHIP_S_MEM_W1_SYS_END(v)) { 522 *memaddrp = CHIP_S_MEM_W1_BUS_START(v) + 523 (memh - (CHIP_S_MEM_W1_SYS_START(v) >> CHIP_ADDR_SHIFT)); 524 return (1); 525 } else 526 #endif 527 #ifdef CHIP_S_MEM_W2_BUS_START 528 if ((memh << CHIP_ADDR_SHIFT) >= CHIP_S_MEM_W2_SYS_START(v) && 529 (memh << CHIP_ADDR_SHIFT) <= CHIP_S_MEM_W2_SYS_END(v)) { 530 *memaddrp = CHIP_S_MEM_W2_BUS_START(v) + 531 (memh - (CHIP_S_MEM_W2_SYS_START(v) >> CHIP_ADDR_SHIFT)); 532 return (1); 533 } else 534 #endif 535 #ifdef CHIP_S_MEM_W3_BUS_START 536 if ((memh << CHIP_ADDR_SHIFT) >= CHIP_S_MEM_W3_SYS_START(v) && 537 (memh << CHIP_ADDR_SHIFT) <= CHIP_S_MEM_W3_SYS_END(v)) { 538 *memaddrp = CHIP_S_MEM_W3_BUS_START(v) + 539 (memh - (CHIP_S_MEM_W3_SYS_START(v) >> CHIP_ADDR_SHIFT)); 540 return (1); 541 } else 542 #endif 543 return (0); 544 } 545 546 int 547 __C(CHIP,_mem_translate)(v, memaddr, memlen, flags, abst) 548 void *v; 549 bus_addr_t memaddr; 550 bus_size_t memlen; 551 int flags; 552 struct alpha_bus_space_translation *abst; 553 { 554 555 /* XXX */ 556 return (EOPNOTSUPP); 557 } 558 559 int 560 __C(CHIP,_mem_get_window)(v, window, abst) 561 void *v; 562 int window; 563 struct alpha_bus_space_translation *abst; 564 { 565 566 #ifdef CHIP_D_MEM_W1_BUS_START 567 #define FIRST_SPARSE 1 568 #else 569 #define FIRST_SPARSE 0 570 #endif 571 572 switch (window) { 573 #ifdef CHIP_D_MEM_W1_BUS_START 574 case 0: 575 abst->abst_bus_start = CHIP_D_MEM_W1_BUS_START(v); 576 abst->abst_bus_end = CHIP_D_MEM_W1_BUS_END(v); 577 abst->abst_sys_start = CHIP_D_MEM_W1_SYS_START(v); 578 abst->abst_sys_end = CHIP_D_MEM_W1_SYS_END(v); 579 abst->abst_addr_shift = 0; 580 abst->abst_size_shift = 0; 581 abst->abst_flags = ABST_DENSE; 582 break; 583 #endif 584 585 #ifdef CHIP_S_MEM_W1_BUS_START 586 case (FIRST_SPARSE): 587 abst->abst_bus_start = CHIP_S_MEM_W1_BUS_START(v); 588 abst->abst_bus_end = CHIP_S_MEM_W1_BUS_END(v); 589 abst->abst_sys_start = CHIP_S_MEM_W1_SYS_START(v); 590 abst->abst_sys_end = CHIP_S_MEM_W1_SYS_END(v); 591 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 592 abst->abst_size_shift = CHIP_SIZE_SHIFT; 593 abst->abst_flags = 0; 594 break; 595 #endif 596 597 #ifdef CHIP_S_MEM_W2_BUS_START 598 case (FIRST_SPARSE + 1): 599 abst->abst_bus_start = CHIP_S_MEM_W2_BUS_START(v); 600 abst->abst_bus_end = CHIP_S_MEM_W2_BUS_END(v); 601 abst->abst_sys_start = CHIP_S_MEM_W2_SYS_START(v); 602 abst->abst_sys_end = CHIP_S_MEM_W2_SYS_END(v); 603 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 604 abst->abst_size_shift = CHIP_SIZE_SHIFT; 605 abst->abst_flags = 0; 606 break; 607 #endif 608 609 #ifdef CHIP_S_MEM_W3_BUS_START 610 case (FIRST_SPARSE + 2): 611 abst->abst_bus_start = CHIP_S_MEM_W3_BUS_START(v); 612 abst->abst_bus_end = CHIP_S_MEM_W3_BUS_END(v); 613 abst->abst_sys_start = CHIP_S_MEM_W3_SYS_START(v); 614 abst->abst_sys_end = CHIP_S_MEM_W3_SYS_END(v); 615 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 616 abst->abst_size_shift = CHIP_SIZE_SHIFT; 617 abst->abst_flags = 0; 618 break; 619 #endif 620 } 621 622 #undef FIRST_SPARSE 623 624 return (0); 625 } 626 627 int 628 __C(CHIP,_mem_map)(v, memaddr, memsize, flags, memhp, acct) 629 void *v; 630 bus_addr_t memaddr; 631 bus_size_t memsize; 632 int flags; 633 bus_space_handle_t *memhp; 634 int acct; 635 { 636 bus_space_handle_t dh = 0, sh = 0; /* XXX -Wuninitialized */ 637 int didd, dids, errord, errors, mustd, musts; 638 int prefectchable = flags & BUS_SPACE_MAP_PREFETCHABLE; 639 int linear = flags & BUS_SPACE_MAP_LINEAR; 640 641 /* 642 * XXX Too hairy to not do accounting in this space. Nothing 643 * XXX much uses this anyhow (only ISA PnP does, and only via 644 * XXX a machine-dependent hook), so we don't have to care. 645 */ 646 if (acct == 0) 647 return (EOPNOTSUPP); 648 649 #ifdef CHIP_D_MEM_W1_SYS_START 650 mustd = 1; 651 if (!__C(CHIP,_xlate_addr_to_dense_handle)(v, memaddr, NULL)) { 652 /* 653 * This address isn't mapped into dense space; don't 654 * require it. 655 */ 656 mustd = 0; 657 } 658 #else 659 mustd = 0; 660 #endif 661 662 /* No prefectchable space without dense. */ 663 if (mustd == 0) 664 prefectchable = 0; 665 666 /* 667 * We must have dense space to map memory linearly. 668 */ 669 if (linear && !prefectchable) 670 return (EOPNOTSUPP); 671 672 musts = (prefectchable == 0); 673 if (!__C(CHIP,_xlate_addr_to_sparse_handle)(v, memaddr, NULL)) { 674 /* 675 * This address isn't mapped into sparse space; don't 676 * require it. 677 */ 678 musts = 0; 679 } 680 681 /* 682 * If this address isn't mapped into dense or sparse, we lose. 683 */ 684 if (mustd == 0 && musts == 0) { 685 #ifdef EXTENT_DEBUG 686 printf("mem: address 0x%lx not in dense or sparse space\n", 687 memaddr); 688 #endif 689 return (EINVAL); 690 } 691 692 #ifdef EXTENT_DEBUG 693 printf("mem: allocating 0x%lx to 0x%lx\n", memaddr, 694 memaddr + memsize - 1); 695 printf("mem: %s dense, %s sparse\n", mustd ? "need" : "want", 696 musts ? "need" : "want"); 697 #endif 698 #ifdef CHIP_D_MEM_W1_SYS_START 699 errord = extent_alloc_region(CHIP_D_MEM_EXTENT(v), memaddr, memsize, 700 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 701 #else 702 errord = EINVAL; 703 #endif 704 didd = (errord == 0); 705 errors = extent_alloc_region(CHIP_S_MEM_EXTENT(v), memaddr, memsize, 706 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 707 dids = (errors == 0); 708 709 #ifdef EXTENT_DEBUG 710 if (!didd) 711 printf("mem: failed to get dense (%d)\n", errord); 712 if (!dids) 713 printf("mem: failed to get sparse (%d)\n", errors); 714 #endif 715 716 if ((mustd && !didd) || (musts && !dids)) 717 goto bad; 718 719 #ifdef CHIP_D_MEM_W1_SYS_START 720 if (didd && !__C(CHIP,_xlate_addr_to_dense_handle)(v, memaddr, &dh)) { 721 printf("\n"); 722 #ifdef CHIP_D_MEM_W1_BUS_START 723 printf("%s: window[1]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)), 724 CHIP_D_MEM_W1_BUS_START(v), CHIP_D_MEM_W1_BUS_END(v)); 725 #endif 726 panic("%s: don't know how to map %lx prefectchable", 727 __S(__C(CHIP,_mem_map)), memaddr); 728 } 729 #endif /* CHIP_D_MEM_W1_SYS_START */ 730 731 if (dids && !__C(CHIP,_xlate_addr_to_sparse_handle)(v, memaddr, &sh)) { 732 printf("\n"); 733 #ifdef CHIP_S_MEM_W1_BUS_START 734 printf("%s: window[1]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)), 735 CHIP_S_MEM_W1_BUS_START(v), CHIP_S_MEM_W1_BUS_END(v)); 736 #endif 737 #ifdef CHIP_S_MEM_W2_BUS_START 738 printf("%s: window[2]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)), 739 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v)); 740 #endif 741 #ifdef CHIP_S_MEM_W3_BUS_START 742 printf("%s: window[3]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)), 743 CHIP_S_MEM_W3_BUS_START(v), CHIP_S_MEM_W3_BUS_END(v)); 744 #endif 745 panic("%s: don't know how to map %lx non-prefectchable", 746 __S(__C(CHIP,_mem_map)), memaddr); 747 } 748 749 if (prefectchable) 750 *memhp = dh; 751 else 752 *memhp = sh; 753 return (0); 754 755 bad: 756 #ifdef EXTENT_DEBUG 757 printf("mem: failed\n"); 758 #endif 759 #ifdef CHIP_D_MEM_W1_SYS_START 760 if (didd) { 761 #ifdef EXTENT_DEBUG 762 printf("mem: freeing dense\n"); 763 #endif 764 if (extent_free(CHIP_D_MEM_EXTENT(v), memaddr, memsize, 765 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)) != 0) { 766 printf("%s: WARNING: couldn't free dense 0x%lx-0x%lx\n", 767 __S(__C(CHIP,_mem_map)), memaddr, 768 memaddr + memsize - 1); 769 } 770 } 771 #endif /* CHIP_D_MEM_W1_SYS_START */ 772 if (dids) { 773 #ifdef EXTENT_DEBUG 774 printf("mem: freeing sparse\n"); 775 #endif 776 if (extent_free(CHIP_S_MEM_EXTENT(v), memaddr, memsize, 777 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)) != 0) { 778 printf("%s: WARNING: couldn't free sparse 0x%lx-0x%lx\n", 779 __S(__C(CHIP,_mem_map)), memaddr, 780 memaddr + memsize - 1); 781 } 782 } 783 784 #ifdef EXTENT_DEBUG 785 #ifdef CHIP_D_MEM_W1_SYS_START 786 extent_print(CHIP_D_MEM_EXTENT(v)); 787 #endif 788 extent_print(CHIP_S_MEM_EXTENT(v)); 789 #endif 790 791 /* 792 * return dense error if we needed it but couldn't get it, else 793 * sparse error. The error _has_ to be one of the two... 794 */ 795 return (mustd && !didd ? errord : (musts && !dids ? errors : EINVAL)); 796 } 797 798 void 799 __C(CHIP,_mem_unmap)(v, memh, memsize, acct) 800 void *v; 801 bus_space_handle_t memh; 802 bus_size_t memsize; 803 int acct; 804 { 805 bus_addr_t memaddr; 806 #ifdef CHIP_D_MEM_W1_SYS_START 807 bus_space_handle_t temph; 808 #endif 809 int sparse, haves, haved; 810 811 if (acct == 0) 812 return; 813 814 #ifdef EXTENT_DEBUG 815 printf("mem: freeing handle 0x%lx for 0x%lx\n", memh, memsize); 816 #endif 817 818 /* 819 * Find out what space we're in. 820 */ 821 sparse = ((memh >> 63) == 0); 822 823 /* 824 * Find out what address we're in in that space. 825 */ 826 haves = haved = 0; 827 if (sparse) 828 haves = __C(CHIP,_xlate_sparse_handle_to_addr)(v, memh, 829 &memaddr); 830 #ifdef CHIP_D_MEM_W1_SYS_START 831 else 832 haved = __C(CHIP,_xlate_dense_handle_to_addr)(v, memh, 833 &memaddr); 834 #endif /* CHIP_D_MEM_W1_SYS_START */ 835 836 if (!haves && !haved) 837 panic("%s: couldn't get addr from %s handle 0x%lx", 838 __S(__C(CHIP,_mem_unmap)), sparse ? "sparse" : "dense", 839 memh); 840 841 #ifdef CHIP_D_MEM_W1_SYS_START 842 /* 843 * Find out were/if that address lives in the other space. 844 */ 845 if (sparse) 846 haved = __C(CHIP,_xlate_addr_to_dense_handle)(v, memaddr, 847 &temph); 848 else 849 haves = __C(CHIP,_xlate_addr_to_sparse_handle)(v, memaddr, 850 &temph); 851 #endif /* CHIP_D_MEM_W1_SYS_START */ 852 853 /* 854 * Free any ranges we have. 855 */ 856 #ifdef EXTENT_DEBUG 857 printf("mem: it's at 0x%lx (%sdense, %ssparse)\n", memaddr, 858 haved ? "" : "not ", haves ? "" : "not "); 859 #endif 860 #ifdef CHIP_D_MEM_W1_SYS_START 861 if (haved && extent_free(CHIP_D_MEM_EXTENT(v), memaddr, memsize, 862 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)) != 0) { 863 printf("%s: WARNING: couldn't free dense 0x%lx-0x%lx\n", 864 __S(__C(CHIP,_mem_map)), memaddr, 865 memaddr + memsize - 1); 866 } 867 #endif 868 if (haves && extent_free(CHIP_S_MEM_EXTENT(v), memaddr, memsize, 869 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)) != 0) { 870 printf("%s: WARNING: couldn't free sparse 0x%lx-0x%lx\n", 871 __S(__C(CHIP,_mem_map)), memaddr, 872 memaddr + memsize - 1); 873 } 874 } 875 876 int 877 __C(CHIP,_mem_subregion)(v, memh, offset, size, nmemh) 878 void *v; 879 bus_space_handle_t memh, *nmemh; 880 bus_size_t offset, size; 881 { 882 883 *nmemh = memh + offset; 884 return (0); 885 } 886 887 int 888 __C(CHIP,_mem_alloc)(v, rstart, rend, size, align, boundary, flags, 889 addrp, bshp) 890 void *v; 891 bus_addr_t rstart, rend, *addrp; 892 bus_size_t size, align, boundary; 893 int flags; 894 bus_space_handle_t *bshp; 895 { 896 897 /* XXX XXX XXX XXX XXX XXX */ 898 panic("%s not implemented", __S(__C(CHIP,_mem_alloc))); 899 } 900 901 void 902 __C(CHIP,_mem_free)(v, bsh, size) 903 void *v; 904 bus_space_handle_t bsh; 905 bus_size_t size; 906 { 907 908 /* XXX XXX XXX XXX XXX XXX */ 909 panic("%s not implemented", __S(__C(CHIP,_mem_free))); 910 } 911 912 void * 913 __C(CHIP,_mem_vaddr)(v, bsh) 914 void *v; 915 bus_space_handle_t bsh; 916 { 917 #ifdef CHIP_D_MEM_W1_SYS_START 918 /* 919 * XXX should check that the range was mapped 920 * with BUS_SPACE_MAP_LINEAR for sanity 921 */ 922 if ((bsh >> 63) != 0) 923 return ((void *)bsh); 924 #endif 925 return (0); 926 } 927 928 paddr_t 929 __C(CHIP,_mem_mmap)(v, addr, off, prot, flags) 930 void *v; 931 bus_addr_t addr; 932 off_t off; 933 int prot; 934 int flags; 935 { 936 bus_space_handle_t dh = 0, sh = 0; /* XXX -Wuninitialized */ 937 int linear = flags & BUS_SPACE_MAP_LINEAR; 938 int haved = 0, haves = 0; 939 940 #ifdef CHIP_D_MEM_W1_SYS_START 941 if (__C(CHIP,_xlate_addr_to_dense_handle)(v, addr + off, &dh)) { 942 haved = 1; 943 dh = ALPHA_K0SEG_TO_PHYS(dh); 944 } 945 #endif 946 if (__C(CHIP,_xlate_addr_to_sparse_handle)(v, addr + off, &sh)) { 947 haves = 1; 948 sh = ALPHA_K0SEG_TO_PHYS(sh); 949 } 950 951 if (linear) { 952 if (haved == 0) 953 return (-1); 954 return (alpha_btop(dh)); 955 } 956 957 if (haves == 0) 958 return (-1); 959 return (alpha_btop(sh)); 960 } 961 962 inline void 963 __C(CHIP,_mem_barrier)(v, h, o, l, f) 964 void *v; 965 bus_space_handle_t h; 966 bus_size_t o, l; 967 int f; 968 { 969 970 if ((f & BUS_SPACE_BARRIER_READ) != 0) 971 alpha_mb(); 972 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 973 alpha_wmb(); 974 } 975 976 inline u_int8_t 977 __C(CHIP,_mem_read_1)(v, memh, off) 978 void *v; 979 bus_space_handle_t memh; 980 bus_size_t off; 981 { 982 register bus_space_handle_t tmpmemh; 983 register u_int32_t *port, val; 984 register u_int8_t rval; 985 register int offset; 986 987 alpha_mb(); 988 989 #ifdef CHIP_D_MEM_W1_SYS_START 990 if ((memh >> 63) != 0) 991 return (*(u_int8_t *)(memh + off)); 992 #endif 993 994 tmpmemh = memh + off; 995 offset = tmpmemh & 3; 996 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 997 (0 << CHIP_SIZE_SHIFT)); 998 val = *port; 999 rval = ((val) >> (8 * offset)) & 0xff; 1000 1001 return rval; 1002 } 1003 1004 inline u_int16_t 1005 __C(CHIP,_mem_read_2)(v, memh, off) 1006 void *v; 1007 bus_space_handle_t memh; 1008 bus_size_t off; 1009 { 1010 register bus_space_handle_t tmpmemh; 1011 register u_int32_t *port, val; 1012 register u_int16_t rval; 1013 register int offset; 1014 1015 alpha_mb(); 1016 1017 #ifdef CHIP_D_MEM_W1_SYS_START 1018 if ((memh >> 63) != 0) 1019 return (*(u_int16_t *)(memh + off)); 1020 #endif 1021 1022 tmpmemh = memh + off; 1023 offset = tmpmemh & 3; 1024 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 1025 (1 << CHIP_SIZE_SHIFT)); 1026 val = *port; 1027 rval = ((val) >> (8 * offset)) & 0xffff; 1028 1029 return rval; 1030 } 1031 1032 inline u_int32_t 1033 __C(CHIP,_mem_read_4)(v, memh, off) 1034 void *v; 1035 bus_space_handle_t memh; 1036 bus_size_t off; 1037 { 1038 register bus_space_handle_t tmpmemh; 1039 register u_int32_t *port, val; 1040 register u_int32_t rval; 1041 register int offset; 1042 1043 alpha_mb(); 1044 1045 #ifdef CHIP_D_MEM_W1_SYS_START 1046 if ((memh >> 63) != 0) 1047 return (*(u_int32_t *)(memh + off)); 1048 #endif 1049 1050 tmpmemh = memh + off; 1051 offset = tmpmemh & 3; 1052 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 1053 (3 << CHIP_SIZE_SHIFT)); 1054 val = *port; 1055 #if 0 1056 rval = ((val) >> (8 * offset)) & 0xffffffff; 1057 #else 1058 rval = val; 1059 #endif 1060 1061 return rval; 1062 } 1063 1064 inline u_int64_t 1065 __C(CHIP,_mem_read_8)(v, memh, off) 1066 void *v; 1067 bus_space_handle_t memh; 1068 bus_size_t off; 1069 { 1070 1071 alpha_mb(); 1072 1073 #ifdef CHIP_D_MEM_W1_SYS_START 1074 if ((memh >> 63) != 0) 1075 return (*(u_int64_t *)(memh + off)); 1076 #endif 1077 1078 /* XXX XXX XXX */ 1079 panic("%s not implemented", __S(__C(CHIP,_mem_read_8))); 1080 } 1081 1082 #define CHIP_mem_read_multi_N(BYTES,TYPE) \ 1083 void \ 1084 __C(__C(CHIP,_mem_read_multi_),BYTES)(v, h, o, a, c) \ 1085 void *v; \ 1086 bus_space_handle_t h; \ 1087 bus_size_t o, c; \ 1088 TYPE *a; \ 1089 { \ 1090 \ 1091 while (c-- > 0) { \ 1092 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 1093 BUS_SPACE_BARRIER_READ); \ 1094 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 1095 } \ 1096 } 1097 CHIP_mem_read_multi_N(1,u_int8_t) 1098 CHIP_mem_read_multi_N(2,u_int16_t) 1099 CHIP_mem_read_multi_N(4,u_int32_t) 1100 CHIP_mem_read_multi_N(8,u_int64_t) 1101 1102 #define CHIP_mem_read_region_N(BYTES,TYPE) \ 1103 void \ 1104 __C(__C(CHIP,_mem_read_region_),BYTES)(v, h, o, a, c) \ 1105 void *v; \ 1106 bus_space_handle_t h; \ 1107 bus_size_t o, c; \ 1108 TYPE *a; \ 1109 { \ 1110 \ 1111 while (c-- > 0) { \ 1112 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 1113 o += sizeof *a; \ 1114 } \ 1115 } 1116 CHIP_mem_read_region_N(1,u_int8_t) 1117 CHIP_mem_read_region_N(2,u_int16_t) 1118 CHIP_mem_read_region_N(4,u_int32_t) 1119 CHIP_mem_read_region_N(8,u_int64_t) 1120 1121 inline void 1122 __C(CHIP,_mem_write_1)(v, memh, off, val) 1123 void *v; 1124 bus_space_handle_t memh; 1125 bus_size_t off; 1126 u_int8_t val; 1127 { 1128 register bus_space_handle_t tmpmemh; 1129 register u_int32_t *port, nval; 1130 register int offset; 1131 1132 #ifdef CHIP_D_MEM_W1_SYS_START 1133 if ((memh >> 63) != 0) 1134 (*(u_int8_t *)(memh + off)) = val; 1135 else 1136 #endif 1137 { 1138 tmpmemh = memh + off; 1139 offset = tmpmemh & 3; 1140 nval = val << (8 * offset); 1141 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 1142 (0 << CHIP_SIZE_SHIFT)); 1143 *port = nval; 1144 } 1145 alpha_mb(); 1146 } 1147 1148 inline void 1149 __C(CHIP,_mem_write_2)(v, memh, off, val) 1150 void *v; 1151 bus_space_handle_t memh; 1152 bus_size_t off; 1153 u_int16_t val; 1154 { 1155 register bus_space_handle_t tmpmemh; 1156 register u_int32_t *port, nval; 1157 register int offset; 1158 1159 #ifdef CHIP_D_MEM_W1_SYS_START 1160 if ((memh >> 63) != 0) 1161 (*(u_int16_t *)(memh + off)) = val; 1162 else 1163 #endif 1164 { 1165 tmpmemh = memh + off; 1166 offset = tmpmemh & 3; 1167 nval = val << (8 * offset); 1168 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 1169 (1 << CHIP_SIZE_SHIFT)); 1170 *port = nval; 1171 } 1172 alpha_mb(); 1173 } 1174 1175 inline void 1176 __C(CHIP,_mem_write_4)(v, memh, off, val) 1177 void *v; 1178 bus_space_handle_t memh; 1179 bus_size_t off; 1180 u_int32_t val; 1181 { 1182 register bus_space_handle_t tmpmemh; 1183 register u_int32_t *port, nval; 1184 register int offset; 1185 1186 #ifdef CHIP_D_MEM_W1_SYS_START 1187 if ((memh >> 63) != 0) 1188 (*(u_int32_t *)(memh + off)) = val; 1189 else 1190 #endif 1191 { 1192 tmpmemh = memh + off; 1193 offset = tmpmemh & 3; 1194 nval = val /*<< (8 * offset)*/; 1195 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 1196 (3 << CHIP_SIZE_SHIFT)); 1197 *port = nval; 1198 } 1199 alpha_mb(); 1200 } 1201 1202 inline void 1203 __C(CHIP,_mem_write_8)(v, memh, off, val) 1204 void *v; 1205 bus_space_handle_t memh; 1206 bus_size_t off; 1207 u_int64_t val; 1208 { 1209 1210 #ifdef CHIP_D_MEM_W1_SYS_START 1211 if ((memh >> 63) != 0) 1212 (*(u_int64_t *)(memh + off)) = val; 1213 else 1214 #endif 1215 { 1216 /* XXX XXX XXX */ 1217 panic("%s not implemented", 1218 __S(__C(CHIP,_mem_write_8))); 1219 } 1220 alpha_mb(); 1221 } 1222 1223 #define CHIP_mem_write_multi_N(BYTES,TYPE) \ 1224 void \ 1225 __C(__C(CHIP,_mem_write_multi_),BYTES)(v, h, o, a, c) \ 1226 void *v; \ 1227 bus_space_handle_t h; \ 1228 bus_size_t o, c; \ 1229 const TYPE *a; \ 1230 { \ 1231 \ 1232 while (c-- > 0) { \ 1233 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 1234 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 1235 BUS_SPACE_BARRIER_WRITE); \ 1236 } \ 1237 } 1238 CHIP_mem_write_multi_N(1,u_int8_t) 1239 CHIP_mem_write_multi_N(2,u_int16_t) 1240 CHIP_mem_write_multi_N(4,u_int32_t) 1241 CHIP_mem_write_multi_N(8,u_int64_t) 1242 1243 #define CHIP_mem_write_region_N(BYTES,TYPE) \ 1244 void \ 1245 __C(__C(CHIP,_mem_write_region_),BYTES)(v, h, o, a, c) \ 1246 void *v; \ 1247 bus_space_handle_t h; \ 1248 bus_size_t o, c; \ 1249 const TYPE *a; \ 1250 { \ 1251 \ 1252 while (c-- > 0) { \ 1253 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 1254 o += sizeof *a; \ 1255 } \ 1256 } 1257 CHIP_mem_write_region_N(1,u_int8_t) 1258 CHIP_mem_write_region_N(2,u_int16_t) 1259 CHIP_mem_write_region_N(4,u_int32_t) 1260 CHIP_mem_write_region_N(8,u_int64_t) 1261 1262 #define CHIP_mem_set_multi_N(BYTES,TYPE) \ 1263 void \ 1264 __C(__C(CHIP,_mem_set_multi_),BYTES)(v, h, o, val, c) \ 1265 void *v; \ 1266 bus_space_handle_t h; \ 1267 bus_size_t o, c; \ 1268 TYPE val; \ 1269 { \ 1270 \ 1271 while (c-- > 0) { \ 1272 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 1273 __C(CHIP,_mem_barrier)(v, h, o, sizeof val, \ 1274 BUS_SPACE_BARRIER_WRITE); \ 1275 } \ 1276 } 1277 CHIP_mem_set_multi_N(1,u_int8_t) 1278 CHIP_mem_set_multi_N(2,u_int16_t) 1279 CHIP_mem_set_multi_N(4,u_int32_t) 1280 CHIP_mem_set_multi_N(8,u_int64_t) 1281 1282 #define CHIP_mem_set_region_N(BYTES,TYPE) \ 1283 void \ 1284 __C(__C(CHIP,_mem_set_region_),BYTES)(v, h, o, val, c) \ 1285 void *v; \ 1286 bus_space_handle_t h; \ 1287 bus_size_t o, c; \ 1288 TYPE val; \ 1289 { \ 1290 \ 1291 while (c-- > 0) { \ 1292 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 1293 o += sizeof val; \ 1294 } \ 1295 } 1296 CHIP_mem_set_region_N(1,u_int8_t) 1297 CHIP_mem_set_region_N(2,u_int16_t) 1298 CHIP_mem_set_region_N(4,u_int32_t) 1299 CHIP_mem_set_region_N(8,u_int64_t) 1300 1301 #define CHIP_mem_copy_region_N(BYTES) \ 1302 void \ 1303 __C(__C(CHIP,_mem_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 1304 void *v; \ 1305 bus_space_handle_t h1, h2; \ 1306 bus_size_t o1, o2, c; \ 1307 { \ 1308 bus_size_t o; \ 1309 \ 1310 if ((h1 >> 63) != 0 && (h2 >> 63) != 0) { \ 1311 memmove((void *)(h2 + o2), (void *)(h1 + o1), c * BYTES); \ 1312 return; \ 1313 } \ 1314 \ 1315 if ((h1 + o1) >= (h2 + o2)) { \ 1316 /* src after dest: copy forward */ \ 1317 for (o = 0; c != 0; c--, o += BYTES) \ 1318 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 1319 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 1320 } else { \ 1321 /* dest after src: copy backwards */ \ 1322 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \ 1323 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 1324 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 1325 } \ 1326 } 1327 CHIP_mem_copy_region_N(1) 1328 CHIP_mem_copy_region_N(2) 1329 CHIP_mem_copy_region_N(4) 1330 CHIP_mem_copy_region_N(8) 1331