1 /* $NetBSD: tc_3000_500.h,v 1.4 1998/10/22 01:03:09 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * TurboChannel-specific functions and structures for 3000_500. 32 */ 33 34 /* 35 * TURBOchannel Interface Registers. 36 * 37 * XXX 38 * Writing to TC_3000_500_TCRESET appears to kill the 400 we're using. 39 */ 40 #define TC_3000_500_IOSLOT KV(0x00000001c2000000) /* Dense */ 41 #define TC_3000_500_TCCONFIG KV(0x00000001c2000008) /* Dense */ 42 #define TC_3000_500_FADR KV(0x00000001c2000010) /* Dense */ 43 #define TC_3000_500_TCEREG KV(0x00000001c2000018) /* Dense */ 44 #define TC_3000_500_MEMCONF KV(0x00000001c2200000) /* Dense */ 45 #define TC_3000_500_IMR_READ KV(0x00000001c2400000) /* Dense */ 46 #define TC_3000_500_IMR_WRITE KV(0x00000001c281fffc) /* Dense */ 47 #define TC_3000_500_TCRESET KV(0x00000001c2a00000) /* Dense */ 48 #define TC_3000_500_IR KV(0x00000001d4800000) /* Sparse */ 49 #define TC_3000_500_IR_CLEAR KV(0x00000001d4c00000) /* Sparse */ 50 #define TC_3000_500_SCMAP KV(0x00000001d5000000) /* Sparse */ 51 52 /* Interrupt bits. */ 53 #define TC_3000_500_IR_OPT0 0x00000001 /* TC Option 0 */ 54 #define TC_3000_500_IR_OPT1 0x00000002 /* TC Option 1 */ 55 #define TC_3000_500_IR_OPT2 0x00000004 /* TC Option 2 */ 56 #define TC_3000_500_IR_OPT3 0x00000008 /* TC Option 3 */ 57 #define TC_3000_500_IR_OPT4 0x00000010 /* TC Option 4 */ 58 #define TC_3000_500_IR_OPT5 0x00000020 /* TC Option 5 */ 59 #define TC_3000_500_IR_TCDS 0x00000040 /* TC Dual SCSI */ 60 #define TC_3000_500_IR_IOASIC 0x00000080 /* TC IOASIC */ 61 #define TC_3000_500_IR_CXTURBO 0x00000100 /* TC CXTURBO */ 62 #define TC_3000_500_IR_ERR2 0x00080000 /* Second error */ 63 #define TC_3000_500_IR_DMABE 0x00100000 /* DMA buffer error */ 64 #define TC_3000_500_IR_DMA2K 0x00200000 /* DMA 2K boundary */ 65 #define TC_3000_500_IR_TCRESET 0x00400000 /* TC reset in prog. */ 66 #define TC_3000_500_IR_TCPAR 0x00800000 /* TC parity error */ 67 #define TC_3000_500_IR_DMATAG 0x01000000 /* DMA tag error */ 68 #define TC_3000_500_IR_DMASBE 0x02000000 /* Single-bit error */ 69 #define TC_3000_500_IR_DMADBE 0x04000000 /* Double-bit error */ 70 #define TC_3000_500_IR_TCTIMEOUT 0x08000000 /* TC timeout on I/O */ 71 #define TC_3000_500_IR_DMABLOCK 0x10000000 /* DMA block too long */ 72 #define TC_3000_500_IR_IOADDR 0x20000000 /* Invalid I/O addr */ 73 #define TC_3000_500_IR_DMASG 0x40000000 /* SG invalid */ 74 #define TC_3000_500_IR_SGPAR 0x80000000 /* SG parity error */ 75 76 /* I/O Slot Configuration (IOSLOT) bits. */ 77 #define IOSLOT_P 0x04 /* Parity enable. */ 78 #define IOSLOT_B 0x02 /* Block-mode write. */ 79 #define IOSLOT_S 0x01 /* DMA scatter/gather mode. */ 80 81 /* I/O Slot Configuration (IOSLOT) offsets. */ 82 #define TC_IOSLOT_OPT0 0 /* Option 0 PBS offset. */ 83 #define TC_IOSLOT_OPT1 1 /* Option 1 PBS offset. */ 84 #define TC_IOSLOT_OPT2 2 /* Option 2 PBS offset. */ 85 #define TC_IOSLOT_OPT3 3 /* Option 3 PBS offset. */ 86 #define TC_IOSLOT_OPT4 4 /* Option 4 PBS offset. */ 87 #define TC_IOSLOT_OPT5 5 /* Option 5 PBS offset. */ 88 #define TC_IOSLOT_SCSI 6 /* Option SCSI PBS offset. */ 89 #define TC_IOSLOT_IOASIC 7 /* Option IOASIC PBS offset. */ 90 #define TC_IOSLOT_CXTURBO 8 /* Option CXTURBO PBS offset. */ 91 92 /* Device number "cookies." */ 93 #define TC_3000_500_DEV_OPT0 0 94 #define TC_3000_500_DEV_OPT1 1 95 #define TC_3000_500_DEV_OPT2 2 96 #define TC_3000_500_DEV_OPT3 3 97 #define TC_3000_500_DEV_OPT4 4 98 #define TC_3000_500_DEV_OPT5 5 99 #define TC_3000_500_DEV_TCDS 6 100 #define TC_3000_500_DEV_IOASIC 7 101 #define TC_3000_500_DEV_CXTURBO 8 102 103 #define TC_3000_500_DEV_BOGUS -1 104 105 #define TC_3000_500_NCOOKIES 9 106 107 extern int tc_3000_500_fb_cnattach __P((u_int64_t)); 108