1 /* $NetBSD: tc_bus_mem.c,v 1.31 2010/12/15 01:29:37 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common TurboChannel Chipset "bus memory" functions. 32 */ 33 34 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 35 36 __KERNEL_RCSID(0, "$NetBSD: tc_bus_mem.c,v 1.31 2010/12/15 01:29:37 matt Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/syslog.h> 42 #include <sys/device.h> 43 44 #include <machine/bus.h> 45 #include <dev/tc/tcvar.h> 46 47 #define __C(A,B) __CONCAT(A,B) 48 49 /* mapping/unmapping */ 50 int tc_mem_map(void *, bus_addr_t, bus_size_t, int, 51 bus_space_handle_t *, int); 52 void tc_mem_unmap(void *, bus_space_handle_t, bus_size_t, int); 53 int tc_mem_subregion(void *, bus_space_handle_t, bus_size_t, 54 bus_size_t, bus_space_handle_t *); 55 56 int tc_mem_translate(void *, bus_addr_t, bus_size_t, 57 int, struct alpha_bus_space_translation *); 58 int tc_mem_get_window(void *, int, 59 struct alpha_bus_space_translation *); 60 61 /* allocation/deallocation */ 62 int tc_mem_alloc(void *, bus_addr_t, bus_addr_t, bus_size_t, 63 bus_size_t, bus_addr_t, int, bus_addr_t *, 64 bus_space_handle_t *); 65 void tc_mem_free(void *, bus_space_handle_t, bus_size_t); 66 67 /* get kernel virtual address */ 68 void * tc_mem_vaddr(void *, bus_space_handle_t); 69 70 /* mmap for user */ 71 paddr_t tc_mem_mmap(void *, bus_addr_t, off_t, int, int); 72 73 /* barrier */ 74 inline void tc_mem_barrier(void *, bus_space_handle_t, 75 bus_size_t, bus_size_t, int); 76 77 /* read (single) */ 78 inline u_int8_t tc_mem_read_1(void *, bus_space_handle_t, bus_size_t); 79 inline u_int16_t tc_mem_read_2(void *, bus_space_handle_t, bus_size_t); 80 inline u_int32_t tc_mem_read_4(void *, bus_space_handle_t, bus_size_t); 81 inline u_int64_t tc_mem_read_8(void *, bus_space_handle_t, bus_size_t); 82 83 /* read multiple */ 84 void tc_mem_read_multi_1(void *, bus_space_handle_t, 85 bus_size_t, u_int8_t *, bus_size_t); 86 void tc_mem_read_multi_2(void *, bus_space_handle_t, 87 bus_size_t, u_int16_t *, bus_size_t); 88 void tc_mem_read_multi_4(void *, bus_space_handle_t, 89 bus_size_t, u_int32_t *, bus_size_t); 90 void tc_mem_read_multi_8(void *, bus_space_handle_t, 91 bus_size_t, u_int64_t *, bus_size_t); 92 93 /* read region */ 94 void tc_mem_read_region_1(void *, bus_space_handle_t, 95 bus_size_t, u_int8_t *, bus_size_t); 96 void tc_mem_read_region_2(void *, bus_space_handle_t, 97 bus_size_t, u_int16_t *, bus_size_t); 98 void tc_mem_read_region_4(void *, bus_space_handle_t, 99 bus_size_t, u_int32_t *, bus_size_t); 100 void tc_mem_read_region_8(void *, bus_space_handle_t, 101 bus_size_t, u_int64_t *, bus_size_t); 102 103 /* write (single) */ 104 inline void tc_mem_write_1(void *, bus_space_handle_t, bus_size_t, 105 u_int8_t); 106 inline void tc_mem_write_2(void *, bus_space_handle_t, bus_size_t, 107 u_int16_t); 108 inline void tc_mem_write_4(void *, bus_space_handle_t, bus_size_t, 109 u_int32_t); 110 inline void tc_mem_write_8(void *, bus_space_handle_t, bus_size_t, 111 u_int64_t); 112 113 /* write multiple */ 114 void tc_mem_write_multi_1(void *, bus_space_handle_t, 115 bus_size_t, const u_int8_t *, bus_size_t); 116 void tc_mem_write_multi_2(void *, bus_space_handle_t, 117 bus_size_t, const u_int16_t *, bus_size_t); 118 void tc_mem_write_multi_4(void *, bus_space_handle_t, 119 bus_size_t, const u_int32_t *, bus_size_t); 120 void tc_mem_write_multi_8(void *, bus_space_handle_t, 121 bus_size_t, const u_int64_t *, bus_size_t); 122 123 /* write region */ 124 void tc_mem_write_region_1(void *, bus_space_handle_t, 125 bus_size_t, const u_int8_t *, bus_size_t); 126 void tc_mem_write_region_2(void *, bus_space_handle_t, 127 bus_size_t, const u_int16_t *, bus_size_t); 128 void tc_mem_write_region_4(void *, bus_space_handle_t, 129 bus_size_t, const u_int32_t *, bus_size_t); 130 void tc_mem_write_region_8(void *, bus_space_handle_t, 131 bus_size_t, const u_int64_t *, bus_size_t); 132 133 /* set multiple */ 134 void tc_mem_set_multi_1(void *, bus_space_handle_t, 135 bus_size_t, u_int8_t, bus_size_t); 136 void tc_mem_set_multi_2(void *, bus_space_handle_t, 137 bus_size_t, u_int16_t, bus_size_t); 138 void tc_mem_set_multi_4(void *, bus_space_handle_t, 139 bus_size_t, u_int32_t, bus_size_t); 140 void tc_mem_set_multi_8(void *, bus_space_handle_t, 141 bus_size_t, u_int64_t, bus_size_t); 142 143 /* set region */ 144 void tc_mem_set_region_1(void *, bus_space_handle_t, 145 bus_size_t, u_int8_t, bus_size_t); 146 void tc_mem_set_region_2(void *, bus_space_handle_t, 147 bus_size_t, u_int16_t, bus_size_t); 148 void tc_mem_set_region_4(void *, bus_space_handle_t, 149 bus_size_t, u_int32_t, bus_size_t); 150 void tc_mem_set_region_8(void *, bus_space_handle_t, 151 bus_size_t, u_int64_t, bus_size_t); 152 153 /* copy */ 154 void tc_mem_copy_region_1(void *, bus_space_handle_t, 155 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 156 void tc_mem_copy_region_2(void *, bus_space_handle_t, 157 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 158 void tc_mem_copy_region_4(void *, bus_space_handle_t, 159 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 160 void tc_mem_copy_region_8(void *, bus_space_handle_t, 161 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 162 163 static struct alpha_bus_space tc_mem_space = { 164 /* cookie */ 165 NULL, 166 167 /* mapping/unmapping */ 168 tc_mem_map, 169 tc_mem_unmap, 170 tc_mem_subregion, 171 172 tc_mem_translate, 173 tc_mem_get_window, 174 175 /* allocation/deallocation */ 176 tc_mem_alloc, 177 tc_mem_free, 178 179 /* get kernel virtual address */ 180 tc_mem_vaddr, 181 182 /* mmap for user */ 183 tc_mem_mmap, 184 185 /* barrier */ 186 tc_mem_barrier, 187 188 /* read (single) */ 189 tc_mem_read_1, 190 tc_mem_read_2, 191 tc_mem_read_4, 192 tc_mem_read_8, 193 194 /* read multiple */ 195 tc_mem_read_multi_1, 196 tc_mem_read_multi_2, 197 tc_mem_read_multi_4, 198 tc_mem_read_multi_8, 199 200 /* read region */ 201 tc_mem_read_region_1, 202 tc_mem_read_region_2, 203 tc_mem_read_region_4, 204 tc_mem_read_region_8, 205 206 /* write (single) */ 207 tc_mem_write_1, 208 tc_mem_write_2, 209 tc_mem_write_4, 210 tc_mem_write_8, 211 212 /* write multiple */ 213 tc_mem_write_multi_1, 214 tc_mem_write_multi_2, 215 tc_mem_write_multi_4, 216 tc_mem_write_multi_8, 217 218 /* write region */ 219 tc_mem_write_region_1, 220 tc_mem_write_region_2, 221 tc_mem_write_region_4, 222 tc_mem_write_region_8, 223 224 /* set multiple */ 225 tc_mem_set_multi_1, 226 tc_mem_set_multi_2, 227 tc_mem_set_multi_4, 228 tc_mem_set_multi_8, 229 230 /* set region */ 231 tc_mem_set_region_1, 232 tc_mem_set_region_2, 233 tc_mem_set_region_4, 234 tc_mem_set_region_8, 235 236 /* copy */ 237 tc_mem_copy_region_1, 238 tc_mem_copy_region_2, 239 tc_mem_copy_region_4, 240 tc_mem_copy_region_8, 241 }; 242 243 bus_space_tag_t 244 tc_bus_mem_init(void *memv) 245 { 246 bus_space_tag_t h = &tc_mem_space; 247 248 h->abs_cookie = memv; 249 return (h); 250 } 251 252 /* ARGSUSED */ 253 int 254 tc_mem_translate(void *v, bus_addr_t memaddr, bus_size_t memlen, int flags, struct alpha_bus_space_translation *abst) 255 { 256 257 return (EOPNOTSUPP); 258 } 259 260 /* ARGSUSED */ 261 int 262 tc_mem_get_window(void *v, int window, struct alpha_bus_space_translation *abst) 263 { 264 265 return (EOPNOTSUPP); 266 } 267 268 /* ARGSUSED */ 269 int 270 tc_mem_map(void *v, bus_addr_t memaddr, bus_size_t memsize, int flags, bus_space_handle_t *memhp, int acct) 271 { 272 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE; 273 int linear = flags & BUS_SPACE_MAP_LINEAR; 274 275 /* Requests for linear uncacheable space can't be satisfied. */ 276 if (linear && !cacheable) 277 return (EOPNOTSUPP); 278 279 if (memaddr & 0x7) 280 panic("tc_mem_map needs 8 byte alignment"); 281 if (cacheable) 282 *memhp = ALPHA_PHYS_TO_K0SEG(memaddr); 283 else 284 *memhp = ALPHA_PHYS_TO_K0SEG(TC_DENSE_TO_SPARSE(memaddr)); 285 return (0); 286 } 287 288 /* ARGSUSED */ 289 void 290 tc_mem_unmap(void *v, bus_space_handle_t memh, bus_size_t memsize, int acct) 291 { 292 293 /* XXX XX XXX nothing to do. */ 294 } 295 296 int 297 tc_mem_subregion(void *v, bus_space_handle_t memh, bus_size_t offset, bus_size_t size, bus_space_handle_t *nmemh) 298 { 299 300 /* Disallow subregioning that would make the handle unaligned. */ 301 if ((offset & 0x7) != 0) 302 return (1); 303 304 if ((memh & TC_SPACE_SPARSE) != 0) 305 *nmemh = memh + (offset << 1); 306 else 307 *nmemh = memh + offset; 308 309 return (0); 310 } 311 312 int 313 tc_mem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 314 { 315 316 /* XXX XXX XXX XXX XXX XXX */ 317 panic("tc_mem_alloc unimplemented"); 318 } 319 320 void 321 tc_mem_free(void *v, bus_space_handle_t bsh, bus_size_t size) 322 { 323 324 /* XXX XXX XXX XXX XXX XXX */ 325 panic("tc_mem_free unimplemented"); 326 } 327 328 void * 329 tc_mem_vaddr(void *v, bus_space_handle_t bsh) 330 { 331 #ifdef DIAGNOSTIC 332 if ((bsh & TC_SPACE_SPARSE) != 0) { 333 /* 334 * tc_mem_map() catches linear && !cacheable, 335 * so we shouldn't come here 336 */ 337 panic("tc_mem_vaddr"); 338 } 339 #endif 340 return ((void *)bsh); 341 } 342 343 paddr_t 344 tc_mem_mmap(void *v, bus_addr_t addr, off_t off, int prot, int flags) 345 { 346 int linear = flags & BUS_SPACE_MAP_LINEAR; 347 bus_addr_t rv; 348 349 if (linear) 350 rv = addr + off; 351 else 352 rv = TC_DENSE_TO_SPARSE(addr + off); 353 354 return (alpha_btop(rv)); 355 } 356 357 inline void 358 tc_mem_barrier(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int f) 359 { 360 361 if ((f & BUS_SPACE_BARRIER_READ) != 0) 362 alpha_mb(); 363 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 364 alpha_wmb(); 365 } 366 367 inline u_int8_t 368 tc_mem_read_1(void *v, bus_space_handle_t memh, bus_size_t off) 369 { 370 volatile u_int8_t *p; 371 372 alpha_mb(); /* XXX XXX XXX */ 373 374 if ((memh & TC_SPACE_SPARSE) != 0) 375 panic("tc_mem_read_1 not implemented for sparse space"); 376 377 p = (u_int8_t *)(memh + off); 378 return (*p); 379 } 380 381 inline u_int16_t 382 tc_mem_read_2(void *v, bus_space_handle_t memh, bus_size_t off) 383 { 384 volatile u_int16_t *p; 385 386 alpha_mb(); /* XXX XXX XXX */ 387 388 if ((memh & TC_SPACE_SPARSE) != 0) 389 panic("tc_mem_read_2 not implemented for sparse space"); 390 391 p = (u_int16_t *)(memh + off); 392 return (*p); 393 } 394 395 inline u_int32_t 396 tc_mem_read_4(void *v, bus_space_handle_t memh, bus_size_t off) 397 { 398 volatile u_int32_t *p; 399 400 alpha_mb(); /* XXX XXX XXX */ 401 402 if ((memh & TC_SPACE_SPARSE) != 0) 403 /* Nothing special to do for 4-byte sparse space accesses */ 404 p = (u_int32_t *)(memh + (off << 1)); 405 else 406 p = (u_int32_t *)(memh + off); 407 return (*p); 408 } 409 410 inline u_int64_t 411 tc_mem_read_8(void *v, bus_space_handle_t memh, bus_size_t off) 412 { 413 volatile u_int64_t *p; 414 415 alpha_mb(); /* XXX XXX XXX */ 416 417 if ((memh & TC_SPACE_SPARSE) != 0) 418 panic("tc_mem_read_8 not implemented for sparse space"); 419 420 p = (u_int64_t *)(memh + off); 421 return (*p); 422 } 423 424 #define tc_mem_read_multi_N(BYTES,TYPE) \ 425 void \ 426 __C(tc_mem_read_multi_,BYTES)(v, h, o, a, c) \ 427 void *v; \ 428 bus_space_handle_t h; \ 429 bus_size_t o, c; \ 430 TYPE *a; \ 431 { \ 432 \ 433 while (c-- > 0) { \ 434 tc_mem_barrier(v, h, o, sizeof *a, BUS_SPACE_BARRIER_READ); \ 435 *a++ = __C(tc_mem_read_,BYTES)(v, h, o); \ 436 } \ 437 } 438 tc_mem_read_multi_N(1,u_int8_t) 439 tc_mem_read_multi_N(2,u_int16_t) 440 tc_mem_read_multi_N(4,u_int32_t) 441 tc_mem_read_multi_N(8,u_int64_t) 442 443 #define tc_mem_read_region_N(BYTES,TYPE) \ 444 void \ 445 __C(tc_mem_read_region_,BYTES)(v, h, o, a, c) \ 446 void *v; \ 447 bus_space_handle_t h; \ 448 bus_size_t o, c; \ 449 TYPE *a; \ 450 { \ 451 \ 452 while (c-- > 0) { \ 453 *a++ = __C(tc_mem_read_,BYTES)(v, h, o); \ 454 o += sizeof *a; \ 455 } \ 456 } 457 tc_mem_read_region_N(1,u_int8_t) 458 tc_mem_read_region_N(2,u_int16_t) 459 tc_mem_read_region_N(4,u_int32_t) 460 tc_mem_read_region_N(8,u_int64_t) 461 462 inline void 463 tc_mem_write_1(void *v, bus_space_handle_t memh, bus_size_t off, u_int8_t val) 464 { 465 466 if ((memh & TC_SPACE_SPARSE) != 0) { 467 volatile u_int64_t *p, vl; 468 u_int64_t shift, msk; 469 470 shift = off & 0x3; 471 off &= 0x3; 472 473 p = (u_int64_t *)(memh + (off << 1)); 474 475 msk = ~(0x1 << shift) & 0xf; 476 vl = (msk << 32) | (((u_int64_t)val) << (shift * 8)); 477 478 *p = val; 479 } else { 480 volatile u_int8_t *p; 481 482 p = (u_int8_t *)(memh + off); 483 *p = val; 484 } 485 alpha_mb(); /* XXX XXX XXX */ 486 } 487 488 inline void 489 tc_mem_write_2(void *v, bus_space_handle_t memh, bus_size_t off, u_int16_t val) 490 { 491 492 if ((memh & TC_SPACE_SPARSE) != 0) { 493 volatile u_int64_t *p, vl; 494 u_int64_t shift, msk; 495 496 shift = off & 0x2; 497 off &= 0x3; 498 499 p = (u_int64_t *)(memh + (off << 1)); 500 501 msk = ~(0x3 << shift) & 0xf; 502 vl = (msk << 32) | (((u_int64_t)val) << (shift * 8)); 503 504 *p = val; 505 } else { 506 volatile u_int16_t *p; 507 508 p = (u_int16_t *)(memh + off); 509 *p = val; 510 } 511 alpha_mb(); /* XXX XXX XXX */ 512 } 513 514 inline void 515 tc_mem_write_4(void *v, bus_space_handle_t memh, bus_size_t off, u_int32_t val) 516 { 517 volatile u_int32_t *p; 518 519 if ((memh & TC_SPACE_SPARSE) != 0) 520 /* Nothing special to do for 4-byte sparse space accesses */ 521 p = (u_int32_t *)(memh + (off << 1)); 522 else 523 p = (u_int32_t *)(memh + off); 524 *p = val; 525 alpha_mb(); /* XXX XXX XXX */ 526 } 527 528 inline void 529 tc_mem_write_8(void *v, bus_space_handle_t memh, bus_size_t off, u_int64_t val) 530 { 531 volatile u_int64_t *p; 532 533 if ((memh & TC_SPACE_SPARSE) != 0) 534 panic("tc_mem_read_8 not implemented for sparse space"); 535 536 p = (u_int64_t *)(memh + off); 537 *p = val; 538 alpha_mb(); /* XXX XXX XXX */ 539 } 540 541 #define tc_mem_write_multi_N(BYTES,TYPE) \ 542 void \ 543 __C(tc_mem_write_multi_,BYTES)(v, h, o, a, c) \ 544 void *v; \ 545 bus_space_handle_t h; \ 546 bus_size_t o, c; \ 547 const TYPE *a; \ 548 { \ 549 \ 550 while (c-- > 0) { \ 551 __C(tc_mem_write_,BYTES)(v, h, o, *a++); \ 552 tc_mem_barrier(v, h, o, sizeof *a, BUS_SPACE_BARRIER_WRITE); \ 553 } \ 554 } 555 tc_mem_write_multi_N(1,u_int8_t) 556 tc_mem_write_multi_N(2,u_int16_t) 557 tc_mem_write_multi_N(4,u_int32_t) 558 tc_mem_write_multi_N(8,u_int64_t) 559 560 #define tc_mem_write_region_N(BYTES,TYPE) \ 561 void \ 562 __C(tc_mem_write_region_,BYTES)(v, h, o, a, c) \ 563 void *v; \ 564 bus_space_handle_t h; \ 565 bus_size_t o, c; \ 566 const TYPE *a; \ 567 { \ 568 \ 569 while (c-- > 0) { \ 570 __C(tc_mem_write_,BYTES)(v, h, o, *a++); \ 571 o += sizeof *a; \ 572 } \ 573 } 574 tc_mem_write_region_N(1,u_int8_t) 575 tc_mem_write_region_N(2,u_int16_t) 576 tc_mem_write_region_N(4,u_int32_t) 577 tc_mem_write_region_N(8,u_int64_t) 578 579 #define tc_mem_set_multi_N(BYTES,TYPE) \ 580 void \ 581 __C(tc_mem_set_multi_,BYTES)(v, h, o, val, c) \ 582 void *v; \ 583 bus_space_handle_t h; \ 584 bus_size_t o, c; \ 585 TYPE val; \ 586 { \ 587 \ 588 while (c-- > 0) { \ 589 __C(tc_mem_write_,BYTES)(v, h, o, val); \ 590 tc_mem_barrier(v, h, o, sizeof val, BUS_SPACE_BARRIER_WRITE); \ 591 } \ 592 } 593 tc_mem_set_multi_N(1,u_int8_t) 594 tc_mem_set_multi_N(2,u_int16_t) 595 tc_mem_set_multi_N(4,u_int32_t) 596 tc_mem_set_multi_N(8,u_int64_t) 597 598 #define tc_mem_set_region_N(BYTES,TYPE) \ 599 void \ 600 __C(tc_mem_set_region_,BYTES)(v, h, o, val, c) \ 601 void *v; \ 602 bus_space_handle_t h; \ 603 bus_size_t o, c; \ 604 TYPE val; \ 605 { \ 606 \ 607 while (c-- > 0) { \ 608 __C(tc_mem_write_,BYTES)(v, h, o, val); \ 609 o += sizeof val; \ 610 } \ 611 } 612 tc_mem_set_region_N(1,u_int8_t) 613 tc_mem_set_region_N(2,u_int16_t) 614 tc_mem_set_region_N(4,u_int32_t) 615 tc_mem_set_region_N(8,u_int64_t) 616 617 #define tc_mem_copy_region_N(BYTES) \ 618 void \ 619 __C(tc_mem_copy_region_,BYTES)(v, h1, o1, h2, o2, c) \ 620 void *v; \ 621 bus_space_handle_t h1, h2; \ 622 bus_size_t o1, o2, c; \ 623 { \ 624 bus_size_t o; \ 625 \ 626 if ((h1 & TC_SPACE_SPARSE) != 0 && \ 627 (h2 & TC_SPACE_SPARSE) != 0) { \ 628 memmove((void *)(h2 + o2), (void *)(h1 + o1), c * BYTES); \ 629 return; \ 630 } \ 631 \ 632 if (h1 + o1 >= h2 + o2) \ 633 /* src after dest: copy forward */ \ 634 for (o = 0; c > 0; c--, o += BYTES) \ 635 __C(tc_mem_write_,BYTES)(v, h2, o2 + o, \ 636 __C(tc_mem_read_,BYTES)(v, h1, o1 + o)); \ 637 else \ 638 /* dest after src: copy backwards */ \ 639 for (o = (c - 1) * BYTES; c > 0; c--, o -= BYTES) \ 640 __C(tc_mem_write_,BYTES)(v, h2, o2 + o, \ 641 __C(tc_mem_read_,BYTES)(v, h1, o1 + o)); \ 642 } 643 tc_mem_copy_region_N(1) 644 tc_mem_copy_region_N(2) 645 tc_mem_copy_region_N(4) 646 tc_mem_copy_region_N(8) 647