1 /* $NetBSD: tlsbreg.h,v 1.5 2000/01/27 22:27:50 mjacob Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 2000 by Matthew Jacob 5 * NASA AMES Research Center. 6 * All rights reserved. 7 * 8 * Based in part upon a prototype version by Jason Thorpe 9 * Copyright (c) 1996 by Jason Thorpe. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice immediately at the beginning of the file, without modification, 16 * this list of conditions, and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Definitions for the TurboLaser System Bus found on 36 * AlphaServer 8200/8400 systems. 37 */ 38 39 /* 40 * There are 9 TurboLaser nodes, 0 though 8. Their uses are defined as 41 * follows: 42 * 43 * Node Module 44 * ---- ------ 45 * 0 CPU, Memory 46 * 1 CPU, Memory 47 * 2 CPU, Memory 48 * 3 CPU, Memory 49 * 4 CPU, Memory, I/O 50 * 5 CPU, Memory, I/O 51 * 6 CPU, Memory, I/O 52 * 7 CPU, Memory, I/O 53 * 8 I/O 54 * 55 * A node occurs every 0x00400000 bytes. 56 * 57 * Note, the AlphaServer 8200 only has nodes 4 though 8. 58 */ 59 60 #define TLSB_NODE_BASE 0x000000ff88000000 /* Dense */ 61 #define TLSB_NODE_SIZE 0x00400000 62 #define TLSB_NODE_MAX 8 /* inclusive */ 63 64 /* Translate a node number to an address. */ 65 #define TLSB_NODE_ADDR(_node) \ 66 (long)(TLSB_NODE_BASE + ((_node) * TLSB_NODE_SIZE)) 67 68 #define TLSB_NODE_REG_ADDR(_node, _reg) \ 69 KV((long)TLSB_NODE_ADDR((_node)) + (_reg)) 70 71 /* Access the specified register on the specified node. */ 72 #define TLSB_GET_NODEREG(_node, _reg) \ 73 *(volatile u_int32_t *)(TLSB_NODE_REG_ADDR((_node), (_reg))) 74 #define TLSB_PUT_NODEREG(_node, _reg, _val) \ 75 *(volatile u_int32_t *)(TLSB_NODE_REG_ADDR((_node), (_reg))) = (_val) 76 77 /* 78 * Some registers are shared by all TurboLaser nodes, and appear in 79 * the TurboLaser Broadcast space. 80 */ 81 #define TLSB_BCAST_BASE 0x000000ff8e000000 /* Dense */ 82 83 #define TLSB_BCAST_REG_ADDR(_reg) KV((long)(TLSB_BCASE_BASE + (_reg))) 84 85 /* Access the specified register in the broadcast space. */ 86 #define TLSB_GET_BCASTREG(_reg) \ 87 *(volatile u_int32_t *)(TLSB_BCAST_REG_ADDR + (_reg)) 88 #define TLSB_PUT_BCASTREG(_reg, _val) \ 89 *(volatile u_int32_t *)(TLSB_BCAST_REG_ADDR + (_reg)) = (_val) 90 91 /* 92 * Location of the Gbus, the per-CPU bus containing the clock and 93 * console hardware. 94 */ 95 #define TLSB_GBUS_BASE 0x000000ff90000000 /* Dense */ 96 97 /* 98 * Note that not every module type supports each TurboLaser register. 99 * The following defines the keys used to denote module support for 100 * a given register: 101 * 102 * C Supported by CPU module 103 * M Supported by Memory module 104 * I Supported by I/O module 105 */ 106 107 /* 108 * Per-node TurboLaser System Bus registers, offsets from the 109 * base of the node. 110 */ 111 #define TLDEV 0x0000 /* CMI: Device Register */ 112 #define TLBER 0x0040 /* CMI: Bus Error Register */ 113 #define TLCNR 0x0080 /* CMI: Congfiguration Register */ 114 #define TLVID 0x00c0 /* CM: Virtual ID Register */ 115 #define TLMMR0 0x0200 /* CM: Memory Mapping Register 0 */ 116 #define TLMMR1 0x0240 /* CM: Memory Mapping Register 1 */ 117 #define TLMMR2 0x0280 /* CM: Memory Mapping Register 2 */ 118 #define TLMMR3 0x02c0 /* CM: Memory Mapping Register 3 */ 119 #define TLMMR4 0x0300 /* CM: Memory Mapping Register 4 */ 120 #define TLMMR5 0x0340 /* CM: Memory Mapping Register 5 */ 121 #define TLMMR6 0x0380 /* CM: Memory Mapping Register 6 */ 122 #define TLMMR7 0x03c0 /* CM: Memory Mapping Register 7 */ 123 #define TLFADR0 0x0600 /* MI: Failing Address Register 0 */ 124 #define TLFADR1 0x0640 /* MI: Failing Address Register 1 */ 125 #define TLESR0 0x0680 /* CMI: Error Syndrome Register 0 */ 126 #define TLESR1 0x06c0 /* CMI: Error Syndrome Register 1 */ 127 #define TLESR2 0x0700 /* CMI: Error Syndrome Register 2 */ 128 #define TLESR3 0x0740 /* CMI: Error Syndrome Register 3 */ 129 #define TLILID0 0x0a00 /* I: Int. Level 0 IDENT Register */ 130 #define TLILID1 0x0a40 /* I: Int. Level 1 IDENT Register */ 131 #define TLILID2 0x0a80 /* I: Int. Level 2 IDENT Register */ 132 #define TLILID3 0x0ac0 /* I: Int. Level 3 IDENT Register */ 133 #define TLCPUMASK 0x0b00 /* I: CPU Interrupt Mask Register */ 134 #define TLMBPTR 0x0c00 /* I: Mailbox Pointer Register */ 135 #define TLINTRMASK0 0x1100 /* C: Interrupt Mask Register CPU 0 */ 136 #define TLINTRMASK1 0x1140 /* C: Interrupt Mask Register CPU 1 */ 137 #define TLINTRSUM0 0x1180 /* C: Interrupt Sum Register CPU 0 */ 138 #define TLINTRSUM1 0x11C0 /* C: Interrupt Sum Register CPU 1 */ 139 #define TLEPAERR 0x1500 /* C: ADG error register */ 140 #define TLEPDERR 0x1540 /* C: DIGA error register */ 141 #define TLEPMERR 0x1580 /* C: MMG error register */ 142 #define TLDMCMD 0x1600 /* C: Data Mover Command */ 143 #define TLDMADRA 0x1680 /* C: Data Mover Source */ 144 #define TLDMADRB 0x16C0 /* C: Data Mover Destination */ 145 146 /* 147 * Registers shared between TurboLaser nodes, offsets from the 148 * TurboLaser Broadcast Base. 149 */ 150 #define TLPRIVATE 0x0000 /* CMI: private "global" space */ 151 #define TLIPINTR 0x0040 /* C: Interprocessor Int. Register */ 152 #define TLIOINTR4 0x0100 /* C: I/O Interrupt Register 4 */ 153 #define TLIOINTR5 0x0140 /* C: I/O Interrupt Register 5 */ 154 #define TLIOINTR6 0x0180 /* C: I/O Interrupt Register 6 */ 155 #define TLIOINTR7 0x01c0 /* C: I/O Interrupt Register 7 */ 156 #define TLIOINTR8 0x0200 /* C: I/O Interrupt Register 8 */ 157 #define TLWSDQR4 0x0400 /* C: Win Spc Dcr Que Ctr Reg 4 */ 158 #define TLWSDQR5 0x0440 /* C: Win Spc Dcr Que Ctr Reg 5 */ 159 #define TLWSDQR6 0x0480 /* C: Win Spc Dcr Que Ctr Reg 6 */ 160 #define TLWSDQR7 0x04c0 /* C: Win Spc Dcr Que Ctr Reg 7 */ 161 #define TLWSDQR8 0x0500 /* C: Win Spc Dcr Que Ctr Reg 8 */ 162 #define TLRMDQRX 0x0600 /* C: Mem Chan Dcr Que Ctr Reg X */ 163 #define TLRMDQR8 0x0640 /* C: Mem Chan Dcr Que Ctr Reg 8 */ 164 #define TLRDRD 0x0800 /* C: CSR Read Data Rtn Data Reg */ 165 #define TLRDRE 0x0840 /* C: CSR Read Data Rtn Error Reg */ 166 #define TLMCR 0x1880 /* M: Memory Control Register */ 167 168 /* 169 * TLDEV - Device Register 170 * 171 * Access: R/W 172 * 173 * Notes: 174 * Register is loaded during initialization with information 175 * that identifies a node. A zero value indicates a non-initialized 176 * (slot empty) node. 177 * 178 * Bits 0-15 contain the hardware device type, bits 16-23 179 * the board's software revision, and bits 24-31 the board's 180 * hardware revision. 181 * 182 * The device type portion is laid out as follows: 183 * 184 * Bit 15: identifies a CPU 185 * Bit 14: identifies a memory board 186 * Bit 13: identifies an I/O board 187 * Bits 0-7: specify the ID of a node type 188 */ 189 #define TLDEV_DTYPE_MASK 0x0000ffff 190 #define TLDEV_DTYPE_KFTHA 0x2000 /* KFTHA board, I/O */ 191 #define TLDEV_DTYPE_KFTIA 0x2020 /* KFTIA board, I/O */ 192 #define TLDEV_DTYPE_MS7CC 0x5000 /* Memory board */ 193 #define TLDEV_DTYPE_SCPU4 0x8011 /* 1 CPU, 4mb cache */ 194 #define TLDEV_DTYPE_SCPU16 0x8012 /* 1 CPU, 16mb cache */ 195 #define TLDEV_DTYPE_DCPU4 0x8014 /* 2 CPU, 4mb cache */ 196 #define TLDEV_DTYPE_DCPU16 0x8015 /* 2 CPU, 16mb cache */ 197 198 #define TLDEV_DTYPE(_val) ((_val) & TLDEV_DTYPE_MASK) 199 # define TLDEV_ISCPU(_val) (TLDEV_DTYPE(_val) & 0x8000) 200 # define TLDEV_ISMEM(_val) (TLDEV_DTYPE(_val) & 0x4000) 201 # define TLDEV_ISIOPORT(_val) (TLDEV_DTYPE(_val) & 0x2000) 202 #define TLDEV_SWREV(_val) (((_val) >> 16) & 0xff) 203 #define TLDEV_HWREV(_val) (((_val) >> 24) & 0xff) 204 205 /* 206 * TLBER - Bus Error Register 207 * 208 * Access: R/W 209 * 210 * Notes: 211 * This register contains information about TLSB errors detected by 212 * nodes on the TLSB. The register will become locked when: 213 * 214 * * Any error occurs and the "lock on first error" 215 * bit of the Configuration Register is set. 216 * 217 * * Any bit other than 20-23 (DS0-DS3) becomes set. 218 * 219 * and will remain locked until either: 220 * 221 * * All bits in the TLBER are cleared. 222 * 223 * * The "lock on first error" bit is cleared. 224 * 225 * TLBER locking is intended for diagnosic purposes only, and 226 * not for general use. 227 */ 228 #define TLBER_ATCE 0x00000001 /* Addr Transmit Ck Error */ 229 #define TLBER_APE 0x00000002 /* Addr Parity Error */ 230 #define TLBER_BAE 0x00000004 /* Bank Avail Violation Error */ 231 #define TLBER_LKTO 0x00000008 /* Bank Lock Timeout */ 232 #define TLBER_NAE 0x00000010 /* No Ack Error */ 233 #define TLBER_RTCE 0x00000020 /* Read Transmit Ck Error */ 234 #define TLBER_ACKTCE 0x00000040 /* Ack Transmit Ck Error */ 235 #define TLBER_MMRE 0x00000080 /* Mem Mapping Register Error */ 236 #define TLBER_FNAE 0x00000100 /* Fatal No Ack Error */ 237 #define TLBER_REQDE 0x00000200 /* Request Deassertion Error */ 238 #define TLBER_ATDE 0x00000400 /* Addredd Transmitter During Error */ 239 #define TLBER_UDE 0x00010000 /* Uncorrectable Data Error */ 240 #define TLBER_CWDE 0x00020000 /* Correctable Write Data Error */ 241 #define TLBER_CRDE 0x00040000 /* Correctable Read Data Error */ 242 #define TLBER_CRDE2 0x00080000 /* ...ditto... */ 243 #define TLBER_DS0 0x00100000 /* Data Synd 0 */ 244 #define TLBER_DS1 0x00200000 /* Data Synd 1 */ 245 #define TLBER_DS2 0x00400000 /* Data Synd 2 */ 246 #define TLBER_DS3 0x00800000 /* Data Synd 3 */ 247 #define TLBER_DTDE 0x01000000 /* Data Transmitter During Error */ 248 #define TLBER_FDTCE 0x02000000 /* Fatal Data Transmit Ck Error */ 249 #define TLBER_UACKE 0x04000000 /* Unexpected Ack Error */ 250 #define TLBER_ABTCE 0x08000000 /* Addr Bus Transmit Error */ 251 #define TLBER_DCTCE 0x10000000 /* Data Control Transmit Ck Error */ 252 #define TLBER_SEQE 0x20000000 /* Sequence Error */ 253 #define TLBER_DSE 0x40000000 /* Data Status Error */ 254 #define TLBER_DTO 0x80000000 /* Data Timeout Error */ 255 256 /* 257 * TLCNR - Configuration Register 258 * 259 * Access: R/W 260 */ 261 #define TLCNR_CWDD 0x00000001 /* Corr Write Data Err INTR Dis */ 262 #define TLCNR_CRDD 0x00000002 /* Corr Read Data Err INTR Dis */ 263 #define TLCNR_LKTOD 0x00000004 /* Bank Lock Timeout Disable */ 264 #define TLCNR_DTOD 0x00000008 /* Data Timeout Disable */ 265 #define TLCNR_STF_A 0x00001000 /* Self-Test Fail A */ 266 #define TLCNR_STF_B 0x00002000 /* Self-Test Fail B */ 267 #define TLCNR_HALT_A 0x00100000 /* Halt A */ 268 #define TLCNR_HALT_B 0x00200000 /* Halt B */ 269 #define TLCNR_RSTSTAT 0x10000000 /* Reset Status */ 270 #define TLCNR_NRST 0x40000000 /* Node Reset */ 271 #define TLCNR_LOFE 0x80000000 /* Lock On First Error */ 272 273 #define TLCNR_NODE_MASK 0x000000f0 /* Node ID mask */ 274 #define TLCNR_NODE_SHIFT 4 275 276 #define TLCNR_VCNT_MASK 0x00000f00 /* VCNT mask */ 277 #define TLCNR_VCNT_SHIFT 8 278 279 /* 280 * TLVID - Virtual ID Register 281 * 282 * Access: R/W 283 * 284 * Notes: 285 * Virtual units can be CPUs or Memory boards. The units are 286 * are addressed using virtual IDs. These virtual IDs are assigned 287 * by writing to the TLVID register. The upper 24 bits of this 288 * register are reserved and must be written as `0'. 289 */ 290 #define TLVID_VIDA_MASK 0x0000000f /* Virtual ID for unit 0 */ 291 #define TLVID_VIDA_SHIFT 0 292 293 #define TLVID_VIDB_MASK 0x000000f0 /* Virtual ID for unit 1 */ 294 #define TLVID_VIDB_SHIFT 4 295 296 /* 297 * TLMMRn - Memory Mapping Registers 298 * 299 * Access: W 300 * 301 * Notes: 302 * Contains mapping information for doing a bank-decode. 303 */ 304 #define TLMMR_INTMASK 0x00000003 /* Valid bits in Interleave */ 305 #define TLMMR_ADRMASK 0x000000f0 /* Valid bits in Address */ 306 #define TLMMR_SBANK 0x00000800 /* Single-bank indicator */ 307 #define TLMMR_VALID 0x80000000 /* Indicated mapping is valid */ 308 309 #define TLMMR_INTLV_MASK 0x00000700 /* Mask for interleave value */ 310 #define TLMMR_INTLV_SHIFT 8 311 312 #define TLMMR_ADDRESS_MASK 0x03fff000 /* Mask for address value */ 313 #define TLMMR_ADDRESS_SHIFT 12 314 315 /* 316 * TLFADRn - Failing Address Registers 317 * 318 * Access: R/W 319 * 320 * Notes: 321 * These registers contain status information for a failed address. 322 * Not all nodes preserve this information. The validation bits 323 * indicate the validity of a given field. 324 */ 325 326 327 /* 328 * CPU Interrupt Mask Register 329 * 330 * The PAL code reads this register for each CPU on a TLSB CPU board 331 * to see what is or isn't enabled. 332 */ 333 #define TLINTRMASK_CONHALT 0x100 /* Enable ^P Halt */ 334 #define TLINTRMASK_HALT 0x080 /* Enable Halt */ 335 #define TLINTRMASK_CLOCK 0x040 /* Enable Clock Interrupts */ 336 #define TLINTRMASK_XCALL 0x020 /* Enable Interprocessor Interrupts */ 337 #define TLINTRMASK_IPL17 0x010 /* Enable IPL 17 Interrupts */ 338 #define TLINTRMASK_IPL16 0x008 /* Enable IPL 16 Interrupts */ 339 #define TLINTRMASK_IPL15 0x004 /* Enable IPL 15 Interrupts */ 340 #define TLINTRMASK_IPL14 0x002 /* Enable IPL 14 Interrupts */ 341 #define TLINTRMASK_DUART 0x001 /* Enable GBUS Duart0 Interrupts */ 342 343 /* 344 * CPU Interrupt Summary Register 345 * 346 * The PAL code reads this register at interrupt time to figure out 347 * which interrupt line to assert to the CPU. Note that when the 348 * interrupt is actually vectored through the PAL code, it arrives 349 * here already presorted as to type (clock, halt, iointr). 350 */ 351 #define TLINTRSUM_HALT (1 << 28) /* Halted via TLCNR register */ 352 #define TLINTRSUM_CONHALT (1 << 27) /* Halted via ^P (W1C) */ 353 #define TLINTRSUM_CLOCK (1 << 6) /* Clock Interrupt (W1C) */ 354 #define TLINTRSUM_XCALL (1 << 5) /* Interprocessor Int (W1C) */ 355 #define TLINTRSUM_IPL17 (1 << 4) /* IPL 17 Interrupt Summary */ 356 #define TLINTRSUM_IPL16 (1 << 3) /* IPL 16 Interrupt Summary */ 357 #define TLINTRSUM_IPL15 (1 << 2) /* IPL 15 Interrupt Summary */ 358 #define TLINTRSUM_IPL14 (1 << 1) /* IPL 14 Interrupt Summary */ 359 #define TLINTRSUM_DUART (1 << 0) /* Duart Int (W1C) */ 360 /* after checking the summaries, you can get the source node for each level */ 361 #define TLINTRSUM_IPL17_SOURCE(x) ((x >> 22) & 0x1f) 362 #define TLINTRSUM_IPL16_SOURCE(x) ((x >> 17) & 0x1f) 363 #define TLINTRSUM_IPL15_SOURCE(x) ((x >> 12) & 0x1f) 364 #define TLINTRSUM_IPL14_SOURCE(x) ((x >> 7) & 0x1f) 365 366 /* 367 * (some of) TurboLaser CPU ADG error register defines. 368 */ 369 #define TLEPAERR_IBOX_TMO 0x1800 /* window space read failed */ 370 #define TLEPAERR_WSPC_RD 0x0600 /* window space read failed */ 371 372 /* 373 * (some of) TurboLaser CPU DIGA error register defines. 374 */ 375 #define TLEPDERR_GBTMO 0x4 /* GBus timeout */ 376 377 /* 378 * Platform specific uncorrectable machine check logout frame. 379 */ 380 struct tlsb_mchk_fatal { 381 u_int64_t rsvdheader; 382 u_int32_t tldev; 383 u_int32_t tlber; 384 u_int32_t tlcnr; 385 u_int32_t tlvid; 386 u_int32_t tlesr0; 387 u_int32_t tlesr1; 388 u_int32_t tlesr2; 389 u_int32_t tlesr3; 390 u_int32_t tlepaerr; 391 u_int32_t tlmodconfig; 392 u_int32_t tlepmerr; 393 u_int32_t tlepderr; 394 u_int32_t tlintrmask0; 395 u_int32_t tlintrmask1; 396 u_int32_t tlintrsum0; 397 u_int32_t tlintrsum1; 398 u_int32_t tlep_vmg; 399 u_int32_t spare[5]; 400 }; 401 /* 402 * Magic values from Digital Unix- if these bits are set in these 403 * registers in the fatal mcheck frame, then we *don't* take a look 404 * at system TLSB registers. 405 */ 406 #define AERR_NO_TLSBSNAP 0x7B /* errors on bits TLEPAERR <6:3,1,0> */ 407 #define DERR_NO_TLSBSNAP 0x07 /* errors on bits TLEPDERR <2:0> */ 408 #define MERR_NO_TLSBSNAP 0x3F /* errors on bits TLEPMERR <5:0> */ 409 410 /* 411 * Platform specific correctable machine check logout frame. 412 */ 413 struct tlsb_mchk_soft { 414 u_int64_t rsvdheader; 415 u_int32_t tldev; 416 u_int32_t tlber; 417 u_int32_t tlesr0; 418 u_int32_t tlesr1; 419 u_int32_t tlesr2; 420 u_int32_t tlesr3; 421 }; 422