1 /* $NetBSD: pte.h,v 1.8 2010/07/24 17:43:47 njoly Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Frank van der Linden for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _AMD64_PTE_H_ 39 #define _AMD64_PTE_H_ 40 41 #ifdef __x86_64__ 42 43 /* 44 * amd64 MMU hardware structure: 45 * 46 * the (first generation) amd64 MMU is a 4-level MMU which maps 2^48 bytes 47 * of virtual memory. The pagesize we use is 4K (4096 [0x1000] bytes), 48 * although 2M and 4M can be used as well. The indexes in the levels 49 * are 9 bits wide (512 64bit entries per level), dividing the bits 50 * 9-9-9-9-12. 51 * 52 * The top level table, called PML4, contains 512 64bit entries pointing 53 * to 3rd level table. The 3rd level table is called the 'page directory 54 * pointers directory' and has 512 entries pointing to page directories. 55 * The 2nd level is the page directory, containing 512 pointers to 56 * page table pages. Lastly, level 1 consists of pages containing 512 57 * PTEs. 58 * 59 * Simply put, levels 4-1 all consist of pages containing 512 60 * entries pointing to the next level. Level 0 is the actual PTEs 61 * themselves. 62 * 63 * For a description on the other bits, which are i386 compatible, 64 * see the i386 pte.h 65 */ 66 67 #if !defined(_LOCORE) 68 69 /* 70 * here we define the data types for PDEs and PTEs 71 */ 72 73 typedef uint64_t pd_entry_t; /* PDE */ 74 typedef uint64_t pt_entry_t; /* PTE */ 75 76 #endif 77 78 /* 79 * now we define various for playing with virtual addresses 80 */ 81 82 #define L1_SHIFT 12 83 #define L2_SHIFT 21 84 #define L3_SHIFT 30 85 #define L4_SHIFT 39 86 #define NBPD_L1 (1UL << L1_SHIFT) /* # bytes mapped by L1 ent (4K) */ 87 #define NBPD_L2 (1UL << L2_SHIFT) /* # bytes mapped by L2 ent (2MB) */ 88 #define NBPD_L3 (1UL << L3_SHIFT) /* # bytes mapped by L3 ent (1G) */ 89 #define NBPD_L4 (1UL << L4_SHIFT) /* # bytes mapped by L4 ent (512G) */ 90 91 #define L4_MASK 0x0000ff8000000000 92 #define L3_MASK 0x0000007fc0000000 93 #define L2_MASK 0x000000003fe00000 94 #define L1_MASK 0x00000000001ff000 95 96 #define L4_FRAME L4_MASK 97 #define L3_FRAME (L4_FRAME|L3_MASK) 98 #define L2_FRAME (L3_FRAME|L2_MASK) 99 #define L1_FRAME (L2_FRAME|L1_MASK) 100 101 /* 102 * PDE/PTE bits. These are no different from their i386 counterparts. 103 */ 104 105 #define PG_V 0x0000000000000001 /* valid */ 106 #define PG_RO 0x0000000000000000 /* read-only */ 107 #define PG_RW 0x0000000000000002 /* read-write */ 108 #define PG_u 0x0000000000000004 /* user accessible */ 109 #define PG_PROT 0x0000000000000006 110 #define PG_WT 0x0000000000000008 /* write-through */ 111 #define PG_N 0x0000000000000010 /* non-cacheable */ 112 #define PG_U 0x0000000000000020 /* used */ 113 #define PG_M 0x0000000000000040 /* modified */ 114 #define PG_PAT 0x0000000000000080 /* PAT (on pte) */ 115 #define PG_PS 0x0000000000000080 /* 2MB page size (on pde) */ 116 #define PG_G 0x0000000000000100 /* not flushed */ 117 #define PG_AVAIL1 0x0000000000000200 118 #define PG_AVAIL2 0x0000000000000400 119 #define PG_AVAIL3 0x0000000000000800 120 #define PG_LGPAT 0x0000000000001000 /* PAT on large pages */ 121 #define PG_FRAME 0x000ffffffffff000 122 #define PG_NX 0x8000000000000000 123 124 #define PG_2MFRAME 0x000fffffffe00000 /* large (2M) page frame mask */ 125 #define PG_1GFRAME 0x000fffffc0000000 /* large (1G) page frame mask */ 126 #define PG_LGFRAME PG_2MFRAME 127 128 /* 129 * short forms of protection codes 130 */ 131 132 #define PG_KR 0x0000000000000000 /* kernel read-only */ 133 #define PG_KW 0x0000000000000002 /* kernel read-write */ 134 135 #include <x86/pte.h> 136 137 #else /* !__x86_64__ */ 138 139 #include <i386/pte.h> 140 141 #endif /* !__x86_64__ */ 142 143 #endif /* _AMD64_PTE_H_ */ 144