xref: /netbsd/sys/arch/amiga/dev/ahscreg.h (revision bf9ec67e)
1 /*	$NetBSD: ahscreg.h,v 1.2 1994/10/26 02:02:46 cgd Exp $	*/
2 
3 /*
4  * Copyright (c) 1994 Christian E. Hopps
5  * Copyright (c) 1982, 1990 The Regents of the University of California.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product includes software developed by the University of
19  *	California, Berkeley and its contributors.
20  * 4. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  *	@(#)dmareg.h
37  */
38 #ifndef _AMIGA_DEV_AHSCREG_H_
39 #define _AMIGA_DEV_AHSCREG_H_
40 
41 /*
42  * Hardware layout of the A3000 SDMAC. This also contains the
43  * registers for the sbic chip, but in favor of separating DMA and
44  * scsi, the scsi-driver doesn't make use of this dependency
45  */
46 
47 #define v_char		volatile char
48 #define	v_int		volatile int
49 #define vu_char		volatile u_char
50 #define vu_short	volatile u_short
51 #define vu_int		volatile u_int
52 
53 struct sdmac {
54 	short		pad0;
55 	vu_short DAWR;		/* DACK Width Register WO */
56 	vu_int   WTC;		/* Word Transfer Count Register RW */
57 	short		pad1;
58 	vu_short CNTR;		/* Control Register RW */
59 	vu_int   ACR;		/* Address Count Register RW */
60 	short		pad2;
61 	vu_short ST_DMA;	/* Start DMA Transfers RW-Strobe */
62 	short		pad3;
63 	vu_short FLUSH;		/* Flush FIFO RW-Strobe */
64 	short		pad4;
65 	vu_short CINT;		/* Clear Interrupts RW-Strobe */
66 	short		pad5;
67 	vu_short ISTR;		/* Interrupt Status Register RO */
68 	int		pad6[7];
69 	short		pad7;
70 	vu_short SP_DMA;	/* Stop DMA Transfers RW-Strobe */
71 	char		pad8;
72 	vu_char  SASR;		/* sbic asr */
73 	char		pad9;
74 	vu_char  SCMD;		/* sbic data */
75 };
76 
77 /*
78  * value to go into DAWR
79  */
80 #define DAWR_AHSC	3	/* according to A3000T service-manual */
81 
82 /*
83  * bits defined for CNTR
84  */
85 #define CNTR_TCEN	(1<<5)	/* Terminal Count Enable */
86 #define CNTR_PREST	(1<<4)	/* Perp Reset (not implemented :-((( ) */
87 #define CNTR_PDMD	(1<<3)  /* Perp Device Mode Select (1=SCSI,0=XT/AT) */
88 #define CNTR_INTEN	(1<<2)	/* Interrupt Enable */
89 #define CNTR_DDIR	(1<<1)	/* Device Direction. 1==rd host, wr perp */
90 #define CNTR_IO_DX	(1<<0)	/* IORDY & CSX1 Polarity Select */
91 
92 /*
93  * bits defined for ISTR
94  */
95 #define ISTR_INTX	(1<<8)	/* XT/AT Interrupt pending */
96 #define ISTR_INT_F	(1<<7)	/* Interrupt Follow */
97 #define ISTR_INTS	(1<<6)	/* SCSI Peripheral Interrupt */
98 #define ISTR_E_INT	(1<<5)	/* End-Of-Process Interrupt */
99 #define ISTR_INT_P	(1<<4)	/* Interrupt Pending */
100 #define ISTR_UE_INT	(1<<3)	/* Under-Run FIFO Error Interrupt */
101 #define ISTR_OE_INT	(1<<2)	/* Over-Run FIFO Error Interrupt */
102 #define ISTR_FF_FLG	(1<<1)	/* FIFO-Full Flag */
103 #define ISTR_FE_FLG	(1<<0)	/* FIFO-Empty Flag */
104 
105 #endif /* _AMIGA_DEV_AHSCREG_H_ */
106