xref: /netbsd/sys/arch/amiga/dev/bzivsc.c (revision 6550d01e) 
1 /*	$NetBSD: bzivsc.c,v 1.31 2010/12/20 00:25:25 matt Exp $ */
2 
3 /*
4  * Copyright (c) 1997 Michael L. Hitch
5  * Copyright (c) 1982, 1990 The Regents of the University of California.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. Neither the name of the University nor the names of its contributors
17  *    may be used to endorse or promote products derived from this software
18  *    without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30  * SUCH DAMAGE.
31  *
32  */
33 
34 #ifdef __m68k__
35 #include "opt_m68k_arch.h"
36 #endif
37 
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: bzivsc.c,v 1.31 2010/12/20 00:25:25 matt Exp $");
40 
41 #include <sys/types.h>
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/errno.h>
46 #include <sys/ioctl.h>
47 #include <sys/device.h>
48 #include <sys/buf.h>
49 #include <sys/proc.h>
50 #include <sys/queue.h>
51 
52 #include <dev/scsipi/scsi_all.h>
53 #include <dev/scsipi/scsipi_all.h>
54 #include <dev/scsipi/scsiconf.h>
55 #include <dev/scsipi/scsi_message.h>
56 
57 #include <machine/cpu.h>
58 #include <machine/param.h>
59 
60 #include <dev/ic/ncr53c9xreg.h>
61 #include <dev/ic/ncr53c9xvar.h>
62 
63 #include <amiga/amiga/isr.h>
64 #include <amiga/dev/bzivscvar.h>
65 #include <amiga/dev/zbusvar.h>
66 
67 #ifdef __powerpc__
68 #define badaddr(a)      badaddr_read(a, 2, NULL)
69 #endif
70 
71 int	bzivscmatch(device_t, cfdata_t, void *);
72 void	bzivscattach(device_t, device_t, void *);
73 
74 /* Linkup to the rest of the kernel */
75 CFATTACH_DECL_NEW(bzivsc, sizeof(struct bzivsc_softc),
76     bzivscmatch, bzivscattach, NULL, NULL);
77 
78 /*
79  * Functions and the switch for the MI code.
80  */
81 uint8_t	bzivsc_read_reg(struct ncr53c9x_softc *, int);
82 void	bzivsc_write_reg(struct ncr53c9x_softc *, int, uint8_t);
83 int	bzivsc_dma_isintr(struct ncr53c9x_softc *);
84 void	bzivsc_dma_reset(struct ncr53c9x_softc *);
85 int	bzivsc_dma_intr(struct ncr53c9x_softc *);
86 int	bzivsc_dma_setup(struct ncr53c9x_softc *, uint8_t **,
87 	    size_t *, int, size_t *);
88 void	bzivsc_dma_go(struct ncr53c9x_softc *);
89 void	bzivsc_dma_stop(struct ncr53c9x_softc *);
90 int	bzivsc_dma_isactive(struct ncr53c9x_softc *);
91 
92 struct ncr53c9x_glue bzivsc_glue = {
93 	bzivsc_read_reg,
94 	bzivsc_write_reg,
95 	bzivsc_dma_isintr,
96 	bzivsc_dma_reset,
97 	bzivsc_dma_intr,
98 	bzivsc_dma_setup,
99 	bzivsc_dma_go,
100 	bzivsc_dma_stop,
101 	bzivsc_dma_isactive,
102 	NULL,
103 };
104 
105 /* Maximum DMA transfer length to reduce impact on high-speed serial input */
106 u_long bzivsc_max_dma = 1024;
107 extern int ser_open_speed;
108 
109 u_long bzivsc_cnt_pio = 0;	/* number of PIO transfers */
110 u_long bzivsc_cnt_dma = 0;	/* number of DMA transfers */
111 u_long bzivsc_cnt_dma2 = 0;	/* number of DMA transfers broken up */
112 u_long bzivsc_cnt_dma3 = 0;	/* number of pages combined */
113 
114 #ifdef DEBUG
115 struct {
116 	uint8_t hardbits;
117 	uint8_t status;
118 	uint8_t xx;
119 	uint8_t yy;
120 } bzivsc_trace[128];
121 int bzivsc_trace_ptr = 0;
122 int bzivsc_trace_enable = 1;
123 void bzivsc_dump(void);
124 #endif
125 
126 /*
127  * if we are a Phase5 Blizzard 12x0-IV
128  */
129 int
130 bzivscmatch(device_t parent, cfdata_t cf, void *aux)
131 {
132 	struct zbus_args *zap;
133 	volatile uint8_t *regs;
134 
135 	zap = aux;
136 	if (zap->manid != 0x2140)
137 		return 0;			/* It's not Phase 5 */
138 	if (zap->prodid != 11 && zap->prodid != 17)
139 		return 0;			/* Not Blizzard 12x0 */
140 	if (!is_a1200())
141 		return 0;			/* And not A1200 */
142 	regs = &((volatile u_char *)zap->va)[0x8000];
143 	if (badaddr((void *)__UNVOLATILE(regs)))
144 		return 0;
145 	regs[NCR_CFG1 * 4] = 0;
146 	regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
147 	delay(5);
148 	if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
149 		return 0;
150 	return 1;
151 }
152 
153 /*
154  * Attach this instance, and then all the sub-devices
155  */
156 void
157 bzivscattach(device_t parent, device_t self, void *aux)
158 {
159 	struct bzivsc_softc *bsc = device_private(self);
160 	struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x;
161 	struct zbus_args  *zap;
162 	extern u_long scsi_nosync;
163 	extern int shift_nosync;
164 	extern int ncr53c9x_debug;
165 
166 	/*
167 	 * Set up the glue for MI code early; we use some of it here.
168 	 */
169 	sc->sc_dev = self;
170 	sc->sc_glue = &bzivsc_glue;
171 
172 	/*
173 	 * Save the regs
174 	 */
175 	zap = aux;
176 	bsc->sc_reg = &((volatile uint8_t *)zap->va)[0x8000];
177 	bsc->sc_dmabase = &bsc->sc_reg[0x8000];
178 
179 	sc->sc_freq = 40;		/* Clocked at 40 MHz */
180 
181 	aprint_normal(": address %p", bsc->sc_reg);
182 
183 	sc->sc_id = 7;
184 
185 	/*
186 	 * It is necessary to try to load the 2nd config register here,
187 	 * to find out what rev the FAS chip is, else the ncr53c9x_reset
188 	 * will not set up the defaults correctly.
189 	 */
190 	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
191 	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
192 	sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
193 	sc->sc_rev = NCR_VARIANT_FAS216;
194 
195 	/*
196 	 * This is the value used to start sync negotiations
197 	 * Note that the NCR register "SYNCTP" is programmed
198 	 * in "clocks per byte", and has a minimum value of 4.
199 	 * The SCSI period used in negotiation is one-fourth
200 	 * of the time (in nanoseconds) needed to transfer one byte.
201 	 * Since the chip's clock is given in MHz, we have the following
202 	 * formula: 4 * period = (1000 / freq) * 4
203 	 */
204 	sc->sc_minsync = 1000 / sc->sc_freq;
205 
206 	/*
207 	 * get flags from -I argument and set cf_flags.
208 	 * NOTE: low 8 bits are to disable disconnect, and the next
209 	 *       8 bits are to disable sync.
210 	 */
211 	device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync)
212 	    & 0xffff;
213 	shift_nosync += 16;
214 
215 	/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
216 	ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
217 	shift_nosync += 16;
218 
219 #if 1
220 	if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
221 		sc->sc_minsync = 0;
222 #endif
223 
224 	/* Really no limit, but since we want to fit into the TCR... */
225 	sc->sc_maxxfer = 64 * 1024;
226 
227 	/*
228 	 * Configure interrupts.
229 	 */
230 	bsc->sc_isr.isr_intr = ncr53c9x_intr;
231 	bsc->sc_isr.isr_arg  = sc;
232 	bsc->sc_isr.isr_ipl  = 2;
233 	add_isr(&bsc->sc_isr);
234 
235 	/*
236 	 * Now try to attach all the sub-devices
237 	 */
238 	sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
239 	sc->sc_adapter.adapt_minphys = minphys;
240 	ncr53c9x_attach(sc);
241 }
242 
243 /*
244  * Glue functions.
245  */
246 
247 uint8_t
248 bzivsc_read_reg(struct ncr53c9x_softc *sc, int reg)
249 {
250 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
251 
252 	return bsc->sc_reg[reg * 4];
253 }
254 
255 void
256 bzivsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)
257 {
258 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
259 	uint8_t v = val;
260 
261 	bsc->sc_reg[reg * 4] = v;
262 #ifdef DEBUG
263 if (bzivsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL */ &&
264   reg == NCR_CMD/* && bsc->sc_active*/) {
265   bzivsc_trace[(bzivsc_trace_ptr - 1) & 127].yy = v;
266 /*  printf(" cmd %x", v);*/
267 }
268 #endif
269 }
270 
271 int
272 bzivsc_dma_isintr(struct ncr53c9x_softc *sc)
273 {
274 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
275 
276 	if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
277 		return 0;
278 
279 #ifdef DEBUG
280 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bzivsc_trace_enable) {
281   bzivsc_trace[bzivsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4];
282   bzivsc_trace[bzivsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4];
283   bzivsc_trace[bzivsc_trace_ptr].yy = bsc->sc_active;
284   bzivsc_trace_ptr = (bzivsc_trace_ptr + 1) & 127;
285 }
286 #endif
287 	return 1;
288 }
289 
290 void
291 bzivsc_dma_reset(struct ncr53c9x_softc *sc)
292 {
293 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
294 
295 	bsc->sc_active = 0;
296 }
297 
298 int
299 bzivsc_dma_intr(struct ncr53c9x_softc *sc)
300 {
301 	register struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
302 	register int	cnt;
303 
304 	NCR_DMA(("bzivsc_dma_intr: cnt %d int %x stat %x fifo %d ",
305 	    bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
306 	    bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
307 	if (bsc->sc_active == 0) {
308 		printf("bzivsc_intr--inactive DMA\n");
309 		return -1;
310 	}
311 
312 	/* update sc_dmaaddr and sc_pdmalen */
313 	cnt = bsc->sc_reg[NCR_TCL * 4];
314 	cnt += bsc->sc_reg[NCR_TCM * 4] << 8;
315 	cnt += bsc->sc_reg[NCR_TCH * 4] << 16;
316 	if (!bsc->sc_datain) {
317 		cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
318 		bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
319 	}
320 	cnt = bsc->sc_dmasize - cnt;	/* number of bytes transferred */
321 	NCR_DMA(("DMA xferred %d\n", cnt));
322 	if (bsc->sc_xfr_align) {
323 		memcpy(*bsc->sc_dmaaddr, bsc->sc_alignbuf, cnt);
324 		bsc->sc_xfr_align = 0;
325 	}
326 	*bsc->sc_dmaaddr += cnt;
327 	*bsc->sc_pdmalen -= cnt;
328 	bsc->sc_active = 0;
329 	return 0;
330 }
331 
332 int
333 bzivsc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
334                  int datain, size_t *dmasize)
335 {
336 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
337 	paddr_t pa;
338 	uint8_t *ptr;
339 	size_t xfer;
340 
341 	bsc->sc_dmaaddr = addr;
342 	bsc->sc_pdmalen = len;
343 	bsc->sc_datain = datain;
344 	bsc->sc_dmasize = *dmasize;
345 	/*
346 	 * DMA can be nasty for high-speed serial input, so limit the
347 	 * size of this DMA operation if the serial port is running at
348 	 * a high speed (higher than 19200 for now - should be adjusted
349 	 * based on CPU type and speed?).
350 	 * XXX - add serial speed check XXX
351 	 */
352 	if (ser_open_speed > 19200 && bzivsc_max_dma != 0 &&
353 	    bsc->sc_dmasize > bzivsc_max_dma)
354 		bsc->sc_dmasize = bzivsc_max_dma;
355 	ptr = *addr;			/* Kernel virtual address */
356 	pa = kvtop(ptr);		/* Physical address of DMA */
357 	xfer = min(bsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1)));
358 	bsc->sc_xfr_align = 0;
359 	/*
360 	 * If output and unaligned, stuff odd byte into FIFO
361 	 */
362 	if (datain == 0 && (int)ptr & 1) {
363 		NCR_DMA(("bzivsc_dma_setup: align byte written to fifo\n"));
364 		pa++;
365 		xfer--;			/* XXXX CHECK THIS !!!! XXXX */
366 		bsc->sc_reg[NCR_FIFO * 4] = *ptr++;
367 	}
368 	/*
369 	 * If unaligned address, read unaligned bytes into alignment buffer
370 	 */
371 	else if ((int)ptr & 1) {
372 		pa = kvtop((void *)&bsc->sc_alignbuf);
373 		xfer = bsc->sc_dmasize = min(xfer, sizeof(bsc->sc_alignbuf));
374 		NCR_DMA(("bzivsc_dma_setup: align read by %d bytes\n", xfer));
375 		bsc->sc_xfr_align = 1;
376 	}
377 ++bzivsc_cnt_dma;		/* number of DMA operations */
378 
379 	while (xfer < bsc->sc_dmasize) {
380 		if ((pa + xfer) != kvtop(*addr + xfer))
381 			break;
382 		if ((bsc->sc_dmasize - xfer) < PAGE_SIZE)
383 			xfer = bsc->sc_dmasize;
384 		else
385 			xfer += PAGE_SIZE;
386 ++bzivsc_cnt_dma3;
387 	}
388 if (xfer != *len)
389   ++bzivsc_cnt_dma2;
390 
391 	bsc->sc_dmasize = xfer;
392 	*dmasize = bsc->sc_dmasize;
393 	bsc->sc_pa = pa;
394 #if defined(M68040) || defined(M68060)
395 	if (mmutype == MMU_68040) {
396 		if (bsc->sc_xfr_align) {
397 			dma_cachectl(bsc->sc_alignbuf,
398 			    sizeof(bsc->sc_alignbuf));
399 		}
400 		else
401 			dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize);
402 	}
403 #endif
404 
405 	pa >>= 1;
406 	if (!bsc->sc_datain)
407 		pa |= 0x80000000;
408 	bsc->sc_dmabase[0x8000] = (uint8_t)(pa >> 24);
409 	bsc->sc_dmabase[0] = (uint8_t)(pa >> 24);
410 	bsc->sc_dmabase[0] = (uint8_t)(pa >> 16);
411 	bsc->sc_dmabase[0] = (uint8_t)(pa >> 8);
412 	bsc->sc_dmabase[0] = (uint8_t)(pa);
413 	bsc->sc_active = 1;
414 	return 0;
415 }
416 
417 void
418 bzivsc_dma_go(struct ncr53c9x_softc *sc)
419 {
420 }
421 
422 void
423 bzivsc_dma_stop(struct ncr53c9x_softc *sc)
424 {
425 }
426 
427 int
428 bzivsc_dma_isactive(struct ncr53c9x_softc *sc)
429 {
430 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
431 
432 	return bsc->sc_active;
433 }
434 
435 #ifdef DEBUG
436 void
437 bzivsc_dump(void)
438 {
439 	int i;
440 
441 	i = bzivsc_trace_ptr;
442 	printf("bzivsc_trace dump: ptr %x\n", bzivsc_trace_ptr);
443 	do {
444 		if (bzivsc_trace[i].hardbits == 0) {
445 			i = (i + 1) & 127;
446 			continue;
447 		}
448 		printf("%02x%02x%02x%02x(", bzivsc_trace[i].hardbits,
449 		    bzivsc_trace[i].status, bzivsc_trace[i].xx, bzivsc_trace[i].yy);
450 		if (bzivsc_trace[i].status & NCRSTAT_INT)
451 			printf("NCRINT/");
452 		if (bzivsc_trace[i].status & NCRSTAT_TC)
453 			printf("NCRTC/");
454 		switch(bzivsc_trace[i].status & NCRSTAT_PHASE) {
455 		case 0:
456 			printf("dataout"); break;
457 		case 1:
458 			printf("datain"); break;
459 		case 2:
460 			printf("cmdout"); break;
461 		case 3:
462 			printf("status"); break;
463 		case 6:
464 			printf("msgout"); break;
465 		case 7:
466 			printf("msgin"); break;
467 		default:
468 			printf("phase%d?", bzivsc_trace[i].status & NCRSTAT_PHASE);
469 		}
470 		printf(") ");
471 		i = (i + 1) & 127;
472 	} while (i != bzivsc_trace_ptr);
473 	printf("\n");
474 }
475 #endif
476