xref: /netbsd/sys/arch/amiga/dev/bzivsc.c (revision 9382c873) 
1 /*	$NetBSD: bzivsc.c,v 1.11 2002/01/26 13:40:53 aymeric Exp $ */
2 
3 /*
4  * Copyright (c) 1997 Michael L. Hitch
5  * Copyright (c) 1982, 1990 The Regents of the University of California.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product contains software written by Michael L. Hitch for
19  *	the NetBSD project.
20  * 4. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  */
37 
38 #include <sys/types.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/errno.h>
43 #include <sys/ioctl.h>
44 #include <sys/device.h>
45 #include <sys/buf.h>
46 #include <sys/proc.h>
47 #include <sys/user.h>
48 #include <sys/queue.h>
49 
50 #include <dev/scsipi/scsi_all.h>
51 #include <dev/scsipi/scsipi_all.h>
52 #include <dev/scsipi/scsiconf.h>
53 #include <dev/scsipi/scsi_message.h>
54 
55 #include <machine/cpu.h>
56 #include <machine/param.h>
57 
58 #include <dev/ic/ncr53c9xreg.h>
59 #include <dev/ic/ncr53c9xvar.h>
60 
61 #include <amiga/amiga/isr.h>
62 #include <amiga/dev/bzivscvar.h>
63 #include <amiga/dev/zbusvar.h>
64 
65 void	bzivscattach(struct device *, struct device *, void *);
66 int	bzivscmatch(struct device *, struct cfdata *, void *);
67 
68 /* Linkup to the rest of the kernel */
69 struct cfattach bzivsc_ca = {
70 	sizeof(struct bzivsc_softc), bzivscmatch, bzivscattach
71 };
72 
73 /*
74  * Functions and the switch for the MI code.
75  */
76 u_char	bzivsc_read_reg(struct ncr53c9x_softc *, int);
77 void	bzivsc_write_reg(struct ncr53c9x_softc *, int, u_char);
78 int	bzivsc_dma_isintr(struct ncr53c9x_softc *);
79 void	bzivsc_dma_reset(struct ncr53c9x_softc *);
80 int	bzivsc_dma_intr(struct ncr53c9x_softc *);
81 int	bzivsc_dma_setup(struct ncr53c9x_softc *, caddr_t *,
82 	    size_t *, int, size_t *);
83 void	bzivsc_dma_go(struct ncr53c9x_softc *);
84 void	bzivsc_dma_stop(struct ncr53c9x_softc *);
85 int	bzivsc_dma_isactive(struct ncr53c9x_softc *);
86 
87 struct ncr53c9x_glue bzivsc_glue = {
88 	bzivsc_read_reg,
89 	bzivsc_write_reg,
90 	bzivsc_dma_isintr,
91 	bzivsc_dma_reset,
92 	bzivsc_dma_intr,
93 	bzivsc_dma_setup,
94 	bzivsc_dma_go,
95 	bzivsc_dma_stop,
96 	bzivsc_dma_isactive,
97 	0,
98 };
99 
100 /* Maximum DMA transfer length to reduce impact on high-speed serial input */
101 u_long bzivsc_max_dma = 1024;
102 extern int ser_open_speed;
103 
104 u_long bzivsc_cnt_pio = 0;	/* number of PIO transfers */
105 u_long bzivsc_cnt_dma = 0;	/* number of DMA transfers */
106 u_long bzivsc_cnt_dma2 = 0;	/* number of DMA transfers broken up */
107 u_long bzivsc_cnt_dma3 = 0;	/* number of pages combined */
108 
109 #ifdef DEBUG
110 struct {
111 	u_char hardbits;
112 	u_char status;
113 	u_char xx;
114 	u_char yy;
115 } bzivsc_trace[128];
116 int bzivsc_trace_ptr = 0;
117 int bzivsc_trace_enable = 1;
118 void bzivsc_dump(void);
119 #endif
120 
121 /*
122  * if we are a Phase5 Blizzard 12x0-IV
123  */
124 int
125 bzivscmatch(struct device *parent, struct cfdata *cf, void *aux)
126 {
127 	struct zbus_args *zap;
128 	volatile u_char *regs;
129 
130 	zap = aux;
131 	if (zap->manid != 0x2140)
132 		return(0);			/* It's not Phase 5 */
133 	if (zap->prodid != 11 && zap->prodid != 17)
134 		return(0);			/* Not Blizzard 12x0 */
135 	if (!is_a1200())
136 		return(0);			/* And not A1200 */
137 	regs = &((volatile u_char *)zap->va)[0x8000];
138 	if (badaddr((caddr_t)regs))
139 		return(0);
140 	regs[NCR_CFG1 * 4] = 0;
141 	regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
142 	delay(5);
143 	if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
144 		return(0);
145 	return(1);
146 }
147 
148 /*
149  * Attach this instance, and then all the sub-devices
150  */
151 void
152 bzivscattach(struct device *parent, struct device *self, void *aux)
153 {
154 	struct bzivsc_softc *bsc = (void *)self;
155 	struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x;
156 	struct zbus_args  *zap;
157 	extern u_long scsi_nosync;
158 	extern int shift_nosync;
159 	extern int ncr53c9x_debug;
160 
161 	/*
162 	 * Set up the glue for MI code early; we use some of it here.
163 	 */
164 	sc->sc_glue = &bzivsc_glue;
165 
166 	/*
167 	 * Save the regs
168 	 */
169 	zap = aux;
170 	bsc->sc_reg = &((volatile u_char *)zap->va)[0x8000];
171 	bsc->sc_dmabase = &bsc->sc_reg[0x8000];
172 
173 	sc->sc_freq = 40;		/* Clocked at 40Mhz */
174 
175 	printf(": address %p", bsc->sc_reg);
176 
177 	sc->sc_id = 7;
178 
179 	/*
180 	 * It is necessary to try to load the 2nd config register here,
181 	 * to find out what rev the FAS chip is, else the ncr53c9x_reset
182 	 * will not set up the defaults correctly.
183 	 */
184 	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
185 	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
186 	sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
187 	sc->sc_rev = NCR_VARIANT_FAS216;
188 
189 	/*
190 	 * This is the value used to start sync negotiations
191 	 * Note that the NCR register "SYNCTP" is programmed
192 	 * in "clocks per byte", and has a minimum value of 4.
193 	 * The SCSI period used in negotiation is one-fourth
194 	 * of the time (in nanoseconds) needed to transfer one byte.
195 	 * Since the chip's clock is given in MHz, we have the following
196 	 * formula: 4 * period = (1000 / freq) * 4
197 	 */
198 	sc->sc_minsync = 1000 / sc->sc_freq;
199 
200 	/*
201 	 * get flags from -I argument and set cf_flags.
202 	 * NOTE: low 8 bits are to disable disconnect, and the next
203 	 *       8 bits are to disable sync.
204 	 */
205 	sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
206 	    & 0xffff;
207 	shift_nosync += 16;
208 
209 	/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
210 	ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
211 	shift_nosync += 16;
212 
213 #if 1
214 	if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
215 		sc->sc_minsync = 0;
216 #endif
217 
218 	/* Really no limit, but since we want to fit into the TCR... */
219 	sc->sc_maxxfer = 64 * 1024;
220 
221 	/*
222 	 * Configure interrupts.
223 	 */
224 	bsc->sc_isr.isr_intr = ncr53c9x_intr;
225 	bsc->sc_isr.isr_arg  = sc;
226 	bsc->sc_isr.isr_ipl  = 2;
227 	add_isr(&bsc->sc_isr);
228 
229 	/*
230 	 * Now try to attach all the sub-devices
231 	 */
232 	sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
233 	sc->sc_adapter.adapt_minphys = minphys;
234 	ncr53c9x_attach(sc);
235 }
236 
237 /*
238  * Glue functions.
239  */
240 
241 u_char
242 bzivsc_read_reg(struct ncr53c9x_softc *sc, int reg)
243 {
244 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
245 
246 	return bsc->sc_reg[reg * 4];
247 }
248 
249 void
250 bzivsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val)
251 {
252 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
253 	u_char v = val;
254 
255 	bsc->sc_reg[reg * 4] = v;
256 #ifdef DEBUG
257 if (bzivsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL */ &&
258   reg == NCR_CMD/* && bsc->sc_active*/) {
259   bzivsc_trace[(bzivsc_trace_ptr - 1) & 127].yy = v;
260 /*  printf(" cmd %x", v);*/
261 }
262 #endif
263 }
264 
265 int
266 bzivsc_dma_isintr(struct ncr53c9x_softc *sc)
267 {
268 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
269 
270 	if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
271 		return 0;
272 
273 #ifdef DEBUG
274 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bzivsc_trace_enable) {
275   bzivsc_trace[bzivsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4];
276   bzivsc_trace[bzivsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4];
277   bzivsc_trace[bzivsc_trace_ptr].yy = bsc->sc_active;
278   bzivsc_trace_ptr = (bzivsc_trace_ptr + 1) & 127;
279 }
280 #endif
281 	return 1;
282 }
283 
284 void
285 bzivsc_dma_reset(struct ncr53c9x_softc *sc)
286 {
287 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
288 
289 	bsc->sc_active = 0;
290 }
291 
292 int
293 bzivsc_dma_intr(struct ncr53c9x_softc *sc)
294 {
295 	register struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
296 	register int	cnt;
297 
298 	NCR_DMA(("bzivsc_dma_intr: cnt %d int %x stat %x fifo %d ",
299 	    bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
300 	    bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
301 	if (bsc->sc_active == 0) {
302 		printf("bzivsc_intr--inactive DMA\n");
303 		return -1;
304 	}
305 
306 	/* update sc_dmaaddr and sc_pdmalen */
307 	cnt = bsc->sc_reg[NCR_TCL * 4];
308 	cnt += bsc->sc_reg[NCR_TCM * 4] << 8;
309 	cnt += bsc->sc_reg[NCR_TCH * 4] << 16;
310 	if (!bsc->sc_datain) {
311 		cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
312 		bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
313 	}
314 	cnt = bsc->sc_dmasize - cnt;	/* number of bytes transferred */
315 	NCR_DMA(("DMA xferred %d\n", cnt));
316 	if (bsc->sc_xfr_align) {
317 		bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt);
318 		bsc->sc_xfr_align = 0;
319 	}
320 	*bsc->sc_dmaaddr += cnt;
321 	*bsc->sc_pdmalen -= cnt;
322 	bsc->sc_active = 0;
323 	return 0;
324 }
325 
326 int
327 bzivsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len,
328                  int datain, size_t *dmasize)
329 {
330 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
331 	paddr_t pa;
332 	u_char *ptr;
333 	size_t xfer;
334 
335 	bsc->sc_dmaaddr = addr;
336 	bsc->sc_pdmalen = len;
337 	bsc->sc_datain = datain;
338 	bsc->sc_dmasize = *dmasize;
339 	/*
340 	 * DMA can be nasty for high-speed serial input, so limit the
341 	 * size of this DMA operation if the serial port is running at
342 	 * a high speed (higher than 19200 for now - should be adjusted
343 	 * based on cpu type and speed?).
344 	 * XXX - add serial speed check XXX
345 	 */
346 	if (ser_open_speed > 19200 && bzivsc_max_dma != 0 &&
347 	    bsc->sc_dmasize > bzivsc_max_dma)
348 		bsc->sc_dmasize = bzivsc_max_dma;
349 	ptr = *addr;			/* Kernel virtual address */
350 	pa = kvtop(ptr);		/* Physical address of DMA */
351 	xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
352 	bsc->sc_xfr_align = 0;
353 	/*
354 	 * If output and unaligned, stuff odd byte into FIFO
355 	 */
356 	if (datain == 0 && (int)ptr & 1) {
357 		NCR_DMA(("bzivsc_dma_setup: align byte written to fifo\n"));
358 		pa++;
359 		xfer--;			/* XXXX CHECK THIS !!!! XXXX */
360 		bsc->sc_reg[NCR_FIFO * 4] = *ptr++;
361 	}
362 	/*
363 	 * If unaligned address, read unaligned bytes into alignment buffer
364 	 */
365 	else if ((int)ptr & 1) {
366 		pa = kvtop((caddr_t)&bsc->sc_alignbuf);
367 		xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf));
368 		NCR_DMA(("bzivsc_dma_setup: align read by %d bytes\n", xfer));
369 		bsc->sc_xfr_align = 1;
370 	}
371 ++bzivsc_cnt_dma;		/* number of DMA operations */
372 
373 	while (xfer < bsc->sc_dmasize) {
374 		if ((pa + xfer) != kvtop(*addr + xfer))
375 			break;
376 		if ((bsc->sc_dmasize - xfer) < NBPG)
377 			xfer = bsc->sc_dmasize;
378 		else
379 			xfer += NBPG;
380 ++bzivsc_cnt_dma3;
381 	}
382 if (xfer != *len)
383   ++bzivsc_cnt_dma2;
384 
385 	bsc->sc_dmasize = xfer;
386 	*dmasize = bsc->sc_dmasize;
387 	bsc->sc_pa = pa;
388 #if defined(M68040) || defined(M68060)
389 	if (mmutype == MMU_68040) {
390 		if (bsc->sc_xfr_align) {
391 			dma_cachectl(bsc->sc_alignbuf,
392 			    sizeof(bsc->sc_alignbuf));
393 		}
394 		else
395 			dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize);
396 	}
397 #endif
398 
399 	pa >>= 1;
400 	if (!bsc->sc_datain)
401 		pa |= 0x80000000;
402 	bsc->sc_dmabase[0x8000] = (u_int8_t)(pa >> 24);
403 	bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
404 	bsc->sc_dmabase[0] = (u_int8_t)(pa >> 16);
405 	bsc->sc_dmabase[0] = (u_int8_t)(pa >> 8);
406 	bsc->sc_dmabase[0] = (u_int8_t)(pa);
407 	bsc->sc_active = 1;
408 	return 0;
409 }
410 
411 void
412 bzivsc_dma_go(struct ncr53c9x_softc *sc)
413 {
414 }
415 
416 void
417 bzivsc_dma_stop(struct ncr53c9x_softc *sc)
418 {
419 }
420 
421 int
422 bzivsc_dma_isactive(struct ncr53c9x_softc *sc)
423 {
424 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
425 
426 	return bsc->sc_active;
427 }
428 
429 #ifdef DEBUG
430 void
431 bzivsc_dump(void)
432 {
433 	int i;
434 
435 	i = bzivsc_trace_ptr;
436 	printf("bzivsc_trace dump: ptr %x\n", bzivsc_trace_ptr);
437 	do {
438 		if (bzivsc_trace[i].hardbits == 0) {
439 			i = (i + 1) & 127;
440 			continue;
441 		}
442 		printf("%02x%02x%02x%02x(", bzivsc_trace[i].hardbits,
443 		    bzivsc_trace[i].status, bzivsc_trace[i].xx, bzivsc_trace[i].yy);
444 		if (bzivsc_trace[i].status & NCRSTAT_INT)
445 			printf("NCRINT/");
446 		if (bzivsc_trace[i].status & NCRSTAT_TC)
447 			printf("NCRTC/");
448 		switch(bzivsc_trace[i].status & NCRSTAT_PHASE) {
449 		case 0:
450 			printf("dataout"); break;
451 		case 1:
452 			printf("datain"); break;
453 		case 2:
454 			printf("cmdout"); break;
455 		case 3:
456 			printf("status"); break;
457 		case 6:
458 			printf("msgout"); break;
459 		case 7:
460 			printf("msgin"); break;
461 		default:
462 			printf("phase%d?", bzivsc_trace[i].status & NCRSTAT_PHASE);
463 		}
464 		printf(") ");
465 		i = (i + 1) & 127;
466 	} while (i != bzivsc_trace_ptr);
467 	printf("\n");
468 }
469 #endif
470