xref: /netbsd/sys/arch/amiga/dev/bzivsc.c (revision bf9ec67e) 
1 /*	$NetBSD: bzivsc.c,v 1.12 2002/01/28 09:56:52 aymeric Exp $ */
2 
3 /*
4  * Copyright (c) 1997 Michael L. Hitch
5  * Copyright (c) 1982, 1990 The Regents of the University of California.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product contains software written by Michael L. Hitch for
19  *	the NetBSD project.
20  * 4. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  */
37 
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: bzivsc.c,v 1.12 2002/01/28 09:56:52 aymeric Exp $");
40 
41 #include <sys/types.h>
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/errno.h>
46 #include <sys/ioctl.h>
47 #include <sys/device.h>
48 #include <sys/buf.h>
49 #include <sys/proc.h>
50 #include <sys/user.h>
51 #include <sys/queue.h>
52 
53 #include <dev/scsipi/scsi_all.h>
54 #include <dev/scsipi/scsipi_all.h>
55 #include <dev/scsipi/scsiconf.h>
56 #include <dev/scsipi/scsi_message.h>
57 
58 #include <machine/cpu.h>
59 #include <machine/param.h>
60 
61 #include <dev/ic/ncr53c9xreg.h>
62 #include <dev/ic/ncr53c9xvar.h>
63 
64 #include <amiga/amiga/isr.h>
65 #include <amiga/dev/bzivscvar.h>
66 #include <amiga/dev/zbusvar.h>
67 
68 void	bzivscattach(struct device *, struct device *, void *);
69 int	bzivscmatch(struct device *, struct cfdata *, void *);
70 
71 /* Linkup to the rest of the kernel */
72 struct cfattach bzivsc_ca = {
73 	sizeof(struct bzivsc_softc), bzivscmatch, bzivscattach
74 };
75 
76 /*
77  * Functions and the switch for the MI code.
78  */
79 u_char	bzivsc_read_reg(struct ncr53c9x_softc *, int);
80 void	bzivsc_write_reg(struct ncr53c9x_softc *, int, u_char);
81 int	bzivsc_dma_isintr(struct ncr53c9x_softc *);
82 void	bzivsc_dma_reset(struct ncr53c9x_softc *);
83 int	bzivsc_dma_intr(struct ncr53c9x_softc *);
84 int	bzivsc_dma_setup(struct ncr53c9x_softc *, caddr_t *,
85 	    size_t *, int, size_t *);
86 void	bzivsc_dma_go(struct ncr53c9x_softc *);
87 void	bzivsc_dma_stop(struct ncr53c9x_softc *);
88 int	bzivsc_dma_isactive(struct ncr53c9x_softc *);
89 
90 struct ncr53c9x_glue bzivsc_glue = {
91 	bzivsc_read_reg,
92 	bzivsc_write_reg,
93 	bzivsc_dma_isintr,
94 	bzivsc_dma_reset,
95 	bzivsc_dma_intr,
96 	bzivsc_dma_setup,
97 	bzivsc_dma_go,
98 	bzivsc_dma_stop,
99 	bzivsc_dma_isactive,
100 	0,
101 };
102 
103 /* Maximum DMA transfer length to reduce impact on high-speed serial input */
104 u_long bzivsc_max_dma = 1024;
105 extern int ser_open_speed;
106 
107 u_long bzivsc_cnt_pio = 0;	/* number of PIO transfers */
108 u_long bzivsc_cnt_dma = 0;	/* number of DMA transfers */
109 u_long bzivsc_cnt_dma2 = 0;	/* number of DMA transfers broken up */
110 u_long bzivsc_cnt_dma3 = 0;	/* number of pages combined */
111 
112 #ifdef DEBUG
113 struct {
114 	u_char hardbits;
115 	u_char status;
116 	u_char xx;
117 	u_char yy;
118 } bzivsc_trace[128];
119 int bzivsc_trace_ptr = 0;
120 int bzivsc_trace_enable = 1;
121 void bzivsc_dump(void);
122 #endif
123 
124 /*
125  * if we are a Phase5 Blizzard 12x0-IV
126  */
127 int
128 bzivscmatch(struct device *parent, struct cfdata *cf, void *aux)
129 {
130 	struct zbus_args *zap;
131 	volatile u_char *regs;
132 
133 	zap = aux;
134 	if (zap->manid != 0x2140)
135 		return(0);			/* It's not Phase 5 */
136 	if (zap->prodid != 11 && zap->prodid != 17)
137 		return(0);			/* Not Blizzard 12x0 */
138 	if (!is_a1200())
139 		return(0);			/* And not A1200 */
140 	regs = &((volatile u_char *)zap->va)[0x8000];
141 	if (badaddr((caddr_t)regs))
142 		return(0);
143 	regs[NCR_CFG1 * 4] = 0;
144 	regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
145 	delay(5);
146 	if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
147 		return(0);
148 	return(1);
149 }
150 
151 /*
152  * Attach this instance, and then all the sub-devices
153  */
154 void
155 bzivscattach(struct device *parent, struct device *self, void *aux)
156 {
157 	struct bzivsc_softc *bsc = (void *)self;
158 	struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x;
159 	struct zbus_args  *zap;
160 	extern u_long scsi_nosync;
161 	extern int shift_nosync;
162 	extern int ncr53c9x_debug;
163 
164 	/*
165 	 * Set up the glue for MI code early; we use some of it here.
166 	 */
167 	sc->sc_glue = &bzivsc_glue;
168 
169 	/*
170 	 * Save the regs
171 	 */
172 	zap = aux;
173 	bsc->sc_reg = &((volatile u_char *)zap->va)[0x8000];
174 	bsc->sc_dmabase = &bsc->sc_reg[0x8000];
175 
176 	sc->sc_freq = 40;		/* Clocked at 40Mhz */
177 
178 	printf(": address %p", bsc->sc_reg);
179 
180 	sc->sc_id = 7;
181 
182 	/*
183 	 * It is necessary to try to load the 2nd config register here,
184 	 * to find out what rev the FAS chip is, else the ncr53c9x_reset
185 	 * will not set up the defaults correctly.
186 	 */
187 	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
188 	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
189 	sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
190 	sc->sc_rev = NCR_VARIANT_FAS216;
191 
192 	/*
193 	 * This is the value used to start sync negotiations
194 	 * Note that the NCR register "SYNCTP" is programmed
195 	 * in "clocks per byte", and has a minimum value of 4.
196 	 * The SCSI period used in negotiation is one-fourth
197 	 * of the time (in nanoseconds) needed to transfer one byte.
198 	 * Since the chip's clock is given in MHz, we have the following
199 	 * formula: 4 * period = (1000 / freq) * 4
200 	 */
201 	sc->sc_minsync = 1000 / sc->sc_freq;
202 
203 	/*
204 	 * get flags from -I argument and set cf_flags.
205 	 * NOTE: low 8 bits are to disable disconnect, and the next
206 	 *       8 bits are to disable sync.
207 	 */
208 	sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
209 	    & 0xffff;
210 	shift_nosync += 16;
211 
212 	/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
213 	ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
214 	shift_nosync += 16;
215 
216 #if 1
217 	if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
218 		sc->sc_minsync = 0;
219 #endif
220 
221 	/* Really no limit, but since we want to fit into the TCR... */
222 	sc->sc_maxxfer = 64 * 1024;
223 
224 	/*
225 	 * Configure interrupts.
226 	 */
227 	bsc->sc_isr.isr_intr = ncr53c9x_intr;
228 	bsc->sc_isr.isr_arg  = sc;
229 	bsc->sc_isr.isr_ipl  = 2;
230 	add_isr(&bsc->sc_isr);
231 
232 	/*
233 	 * Now try to attach all the sub-devices
234 	 */
235 	sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
236 	sc->sc_adapter.adapt_minphys = minphys;
237 	ncr53c9x_attach(sc);
238 }
239 
240 /*
241  * Glue functions.
242  */
243 
244 u_char
245 bzivsc_read_reg(struct ncr53c9x_softc *sc, int reg)
246 {
247 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
248 
249 	return bsc->sc_reg[reg * 4];
250 }
251 
252 void
253 bzivsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val)
254 {
255 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
256 	u_char v = val;
257 
258 	bsc->sc_reg[reg * 4] = v;
259 #ifdef DEBUG
260 if (bzivsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL */ &&
261   reg == NCR_CMD/* && bsc->sc_active*/) {
262   bzivsc_trace[(bzivsc_trace_ptr - 1) & 127].yy = v;
263 /*  printf(" cmd %x", v);*/
264 }
265 #endif
266 }
267 
268 int
269 bzivsc_dma_isintr(struct ncr53c9x_softc *sc)
270 {
271 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
272 
273 	if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
274 		return 0;
275 
276 #ifdef DEBUG
277 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bzivsc_trace_enable) {
278   bzivsc_trace[bzivsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4];
279   bzivsc_trace[bzivsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4];
280   bzivsc_trace[bzivsc_trace_ptr].yy = bsc->sc_active;
281   bzivsc_trace_ptr = (bzivsc_trace_ptr + 1) & 127;
282 }
283 #endif
284 	return 1;
285 }
286 
287 void
288 bzivsc_dma_reset(struct ncr53c9x_softc *sc)
289 {
290 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
291 
292 	bsc->sc_active = 0;
293 }
294 
295 int
296 bzivsc_dma_intr(struct ncr53c9x_softc *sc)
297 {
298 	register struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
299 	register int	cnt;
300 
301 	NCR_DMA(("bzivsc_dma_intr: cnt %d int %x stat %x fifo %d ",
302 	    bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
303 	    bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
304 	if (bsc->sc_active == 0) {
305 		printf("bzivsc_intr--inactive DMA\n");
306 		return -1;
307 	}
308 
309 	/* update sc_dmaaddr and sc_pdmalen */
310 	cnt = bsc->sc_reg[NCR_TCL * 4];
311 	cnt += bsc->sc_reg[NCR_TCM * 4] << 8;
312 	cnt += bsc->sc_reg[NCR_TCH * 4] << 16;
313 	if (!bsc->sc_datain) {
314 		cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
315 		bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
316 	}
317 	cnt = bsc->sc_dmasize - cnt;	/* number of bytes transferred */
318 	NCR_DMA(("DMA xferred %d\n", cnt));
319 	if (bsc->sc_xfr_align) {
320 		bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt);
321 		bsc->sc_xfr_align = 0;
322 	}
323 	*bsc->sc_dmaaddr += cnt;
324 	*bsc->sc_pdmalen -= cnt;
325 	bsc->sc_active = 0;
326 	return 0;
327 }
328 
329 int
330 bzivsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len,
331                  int datain, size_t *dmasize)
332 {
333 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
334 	paddr_t pa;
335 	u_char *ptr;
336 	size_t xfer;
337 
338 	bsc->sc_dmaaddr = addr;
339 	bsc->sc_pdmalen = len;
340 	bsc->sc_datain = datain;
341 	bsc->sc_dmasize = *dmasize;
342 	/*
343 	 * DMA can be nasty for high-speed serial input, so limit the
344 	 * size of this DMA operation if the serial port is running at
345 	 * a high speed (higher than 19200 for now - should be adjusted
346 	 * based on cpu type and speed?).
347 	 * XXX - add serial speed check XXX
348 	 */
349 	if (ser_open_speed > 19200 && bzivsc_max_dma != 0 &&
350 	    bsc->sc_dmasize > bzivsc_max_dma)
351 		bsc->sc_dmasize = bzivsc_max_dma;
352 	ptr = *addr;			/* Kernel virtual address */
353 	pa = kvtop(ptr);		/* Physical address of DMA */
354 	xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
355 	bsc->sc_xfr_align = 0;
356 	/*
357 	 * If output and unaligned, stuff odd byte into FIFO
358 	 */
359 	if (datain == 0 && (int)ptr & 1) {
360 		NCR_DMA(("bzivsc_dma_setup: align byte written to fifo\n"));
361 		pa++;
362 		xfer--;			/* XXXX CHECK THIS !!!! XXXX */
363 		bsc->sc_reg[NCR_FIFO * 4] = *ptr++;
364 	}
365 	/*
366 	 * If unaligned address, read unaligned bytes into alignment buffer
367 	 */
368 	else if ((int)ptr & 1) {
369 		pa = kvtop((caddr_t)&bsc->sc_alignbuf);
370 		xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf));
371 		NCR_DMA(("bzivsc_dma_setup: align read by %d bytes\n", xfer));
372 		bsc->sc_xfr_align = 1;
373 	}
374 ++bzivsc_cnt_dma;		/* number of DMA operations */
375 
376 	while (xfer < bsc->sc_dmasize) {
377 		if ((pa + xfer) != kvtop(*addr + xfer))
378 			break;
379 		if ((bsc->sc_dmasize - xfer) < NBPG)
380 			xfer = bsc->sc_dmasize;
381 		else
382 			xfer += NBPG;
383 ++bzivsc_cnt_dma3;
384 	}
385 if (xfer != *len)
386   ++bzivsc_cnt_dma2;
387 
388 	bsc->sc_dmasize = xfer;
389 	*dmasize = bsc->sc_dmasize;
390 	bsc->sc_pa = pa;
391 #if defined(M68040) || defined(M68060)
392 	if (mmutype == MMU_68040) {
393 		if (bsc->sc_xfr_align) {
394 			dma_cachectl(bsc->sc_alignbuf,
395 			    sizeof(bsc->sc_alignbuf));
396 		}
397 		else
398 			dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize);
399 	}
400 #endif
401 
402 	pa >>= 1;
403 	if (!bsc->sc_datain)
404 		pa |= 0x80000000;
405 	bsc->sc_dmabase[0x8000] = (u_int8_t)(pa >> 24);
406 	bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
407 	bsc->sc_dmabase[0] = (u_int8_t)(pa >> 16);
408 	bsc->sc_dmabase[0] = (u_int8_t)(pa >> 8);
409 	bsc->sc_dmabase[0] = (u_int8_t)(pa);
410 	bsc->sc_active = 1;
411 	return 0;
412 }
413 
414 void
415 bzivsc_dma_go(struct ncr53c9x_softc *sc)
416 {
417 }
418 
419 void
420 bzivsc_dma_stop(struct ncr53c9x_softc *sc)
421 {
422 }
423 
424 int
425 bzivsc_dma_isactive(struct ncr53c9x_softc *sc)
426 {
427 	struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc;
428 
429 	return bsc->sc_active;
430 }
431 
432 #ifdef DEBUG
433 void
434 bzivsc_dump(void)
435 {
436 	int i;
437 
438 	i = bzivsc_trace_ptr;
439 	printf("bzivsc_trace dump: ptr %x\n", bzivsc_trace_ptr);
440 	do {
441 		if (bzivsc_trace[i].hardbits == 0) {
442 			i = (i + 1) & 127;
443 			continue;
444 		}
445 		printf("%02x%02x%02x%02x(", bzivsc_trace[i].hardbits,
446 		    bzivsc_trace[i].status, bzivsc_trace[i].xx, bzivsc_trace[i].yy);
447 		if (bzivsc_trace[i].status & NCRSTAT_INT)
448 			printf("NCRINT/");
449 		if (bzivsc_trace[i].status & NCRSTAT_TC)
450 			printf("NCRTC/");
451 		switch(bzivsc_trace[i].status & NCRSTAT_PHASE) {
452 		case 0:
453 			printf("dataout"); break;
454 		case 1:
455 			printf("datain"); break;
456 		case 2:
457 			printf("cmdout"); break;
458 		case 3:
459 			printf("status"); break;
460 		case 6:
461 			printf("msgout"); break;
462 		case 7:
463 			printf("msgin"); break;
464 		default:
465 			printf("phase%d?", bzivsc_trace[i].status & NCRSTAT_PHASE);
466 		}
467 		printf(") ");
468 		i = (i + 1) & 127;
469 	} while (i != bzivsc_trace_ptr);
470 	printf("\n");
471 }
472 #endif
473