1 /* $NetBSD: bzivsc.c,v 1.14 2002/10/02 04:55:48 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product contains software written by Michael L. Hitch for 19 * the NetBSD project. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: bzivsc.c,v 1.14 2002/10/02 04:55:48 thorpej Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/ioctl.h> 47 #include <sys/device.h> 48 #include <sys/buf.h> 49 #include <sys/proc.h> 50 #include <sys/user.h> 51 #include <sys/queue.h> 52 53 #include <dev/scsipi/scsi_all.h> 54 #include <dev/scsipi/scsipi_all.h> 55 #include <dev/scsipi/scsiconf.h> 56 #include <dev/scsipi/scsi_message.h> 57 58 #include <machine/cpu.h> 59 #include <machine/param.h> 60 61 #include <dev/ic/ncr53c9xreg.h> 62 #include <dev/ic/ncr53c9xvar.h> 63 64 #include <amiga/amiga/isr.h> 65 #include <amiga/dev/bzivscvar.h> 66 #include <amiga/dev/zbusvar.h> 67 68 void bzivscattach(struct device *, struct device *, void *); 69 int bzivscmatch(struct device *, struct cfdata *, void *); 70 71 /* Linkup to the rest of the kernel */ 72 CFATTACH_DECL(bzivsc, sizeof(struct bzivsc_softc), 73 bzivscmatch, bzivscattach, NULL, NULL); 74 75 /* 76 * Functions and the switch for the MI code. 77 */ 78 u_char bzivsc_read_reg(struct ncr53c9x_softc *, int); 79 void bzivsc_write_reg(struct ncr53c9x_softc *, int, u_char); 80 int bzivsc_dma_isintr(struct ncr53c9x_softc *); 81 void bzivsc_dma_reset(struct ncr53c9x_softc *); 82 int bzivsc_dma_intr(struct ncr53c9x_softc *); 83 int bzivsc_dma_setup(struct ncr53c9x_softc *, caddr_t *, 84 size_t *, int, size_t *); 85 void bzivsc_dma_go(struct ncr53c9x_softc *); 86 void bzivsc_dma_stop(struct ncr53c9x_softc *); 87 int bzivsc_dma_isactive(struct ncr53c9x_softc *); 88 89 struct ncr53c9x_glue bzivsc_glue = { 90 bzivsc_read_reg, 91 bzivsc_write_reg, 92 bzivsc_dma_isintr, 93 bzivsc_dma_reset, 94 bzivsc_dma_intr, 95 bzivsc_dma_setup, 96 bzivsc_dma_go, 97 bzivsc_dma_stop, 98 bzivsc_dma_isactive, 99 0, 100 }; 101 102 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 103 u_long bzivsc_max_dma = 1024; 104 extern int ser_open_speed; 105 106 u_long bzivsc_cnt_pio = 0; /* number of PIO transfers */ 107 u_long bzivsc_cnt_dma = 0; /* number of DMA transfers */ 108 u_long bzivsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 109 u_long bzivsc_cnt_dma3 = 0; /* number of pages combined */ 110 111 #ifdef DEBUG 112 struct { 113 u_char hardbits; 114 u_char status; 115 u_char xx; 116 u_char yy; 117 } bzivsc_trace[128]; 118 int bzivsc_trace_ptr = 0; 119 int bzivsc_trace_enable = 1; 120 void bzivsc_dump(void); 121 #endif 122 123 /* 124 * if we are a Phase5 Blizzard 12x0-IV 125 */ 126 int 127 bzivscmatch(struct device *parent, struct cfdata *cf, void *aux) 128 { 129 struct zbus_args *zap; 130 volatile u_char *regs; 131 132 zap = aux; 133 if (zap->manid != 0x2140) 134 return(0); /* It's not Phase 5 */ 135 if (zap->prodid != 11 && zap->prodid != 17) 136 return(0); /* Not Blizzard 12x0 */ 137 if (!is_a1200()) 138 return(0); /* And not A1200 */ 139 regs = &((volatile u_char *)zap->va)[0x8000]; 140 if (badaddr((caddr_t)regs)) 141 return(0); 142 regs[NCR_CFG1 * 4] = 0; 143 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 144 delay(5); 145 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 146 return(0); 147 return(1); 148 } 149 150 /* 151 * Attach this instance, and then all the sub-devices 152 */ 153 void 154 bzivscattach(struct device *parent, struct device *self, void *aux) 155 { 156 struct bzivsc_softc *bsc = (void *)self; 157 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 158 struct zbus_args *zap; 159 extern u_long scsi_nosync; 160 extern int shift_nosync; 161 extern int ncr53c9x_debug; 162 163 /* 164 * Set up the glue for MI code early; we use some of it here. 165 */ 166 sc->sc_glue = &bzivsc_glue; 167 168 /* 169 * Save the regs 170 */ 171 zap = aux; 172 bsc->sc_reg = &((volatile u_char *)zap->va)[0x8000]; 173 bsc->sc_dmabase = &bsc->sc_reg[0x8000]; 174 175 sc->sc_freq = 40; /* Clocked at 40Mhz */ 176 177 printf(": address %p", bsc->sc_reg); 178 179 sc->sc_id = 7; 180 181 /* 182 * It is necessary to try to load the 2nd config register here, 183 * to find out what rev the FAS chip is, else the ncr53c9x_reset 184 * will not set up the defaults correctly. 185 */ 186 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 187 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 188 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 189 sc->sc_rev = NCR_VARIANT_FAS216; 190 191 /* 192 * This is the value used to start sync negotiations 193 * Note that the NCR register "SYNCTP" is programmed 194 * in "clocks per byte", and has a minimum value of 4. 195 * The SCSI period used in negotiation is one-fourth 196 * of the time (in nanoseconds) needed to transfer one byte. 197 * Since the chip's clock is given in MHz, we have the following 198 * formula: 4 * period = (1000 / freq) * 4 199 */ 200 sc->sc_minsync = 1000 / sc->sc_freq; 201 202 /* 203 * get flags from -I argument and set cf_flags. 204 * NOTE: low 8 bits are to disable disconnect, and the next 205 * 8 bits are to disable sync. 206 */ 207 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 208 & 0xffff; 209 shift_nosync += 16; 210 211 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 212 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 213 shift_nosync += 16; 214 215 #if 1 216 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 217 sc->sc_minsync = 0; 218 #endif 219 220 /* Really no limit, but since we want to fit into the TCR... */ 221 sc->sc_maxxfer = 64 * 1024; 222 223 /* 224 * Configure interrupts. 225 */ 226 bsc->sc_isr.isr_intr = ncr53c9x_intr; 227 bsc->sc_isr.isr_arg = sc; 228 bsc->sc_isr.isr_ipl = 2; 229 add_isr(&bsc->sc_isr); 230 231 /* 232 * Now try to attach all the sub-devices 233 */ 234 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 235 sc->sc_adapter.adapt_minphys = minphys; 236 ncr53c9x_attach(sc); 237 } 238 239 /* 240 * Glue functions. 241 */ 242 243 u_char 244 bzivsc_read_reg(struct ncr53c9x_softc *sc, int reg) 245 { 246 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 247 248 return bsc->sc_reg[reg * 4]; 249 } 250 251 void 252 bzivsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 253 { 254 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 255 u_char v = val; 256 257 bsc->sc_reg[reg * 4] = v; 258 #ifdef DEBUG 259 if (bzivsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL */ && 260 reg == NCR_CMD/* && bsc->sc_active*/) { 261 bzivsc_trace[(bzivsc_trace_ptr - 1) & 127].yy = v; 262 /* printf(" cmd %x", v);*/ 263 } 264 #endif 265 } 266 267 int 268 bzivsc_dma_isintr(struct ncr53c9x_softc *sc) 269 { 270 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 271 272 if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 273 return 0; 274 275 #ifdef DEBUG 276 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bzivsc_trace_enable) { 277 bzivsc_trace[bzivsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4]; 278 bzivsc_trace[bzivsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4]; 279 bzivsc_trace[bzivsc_trace_ptr].yy = bsc->sc_active; 280 bzivsc_trace_ptr = (bzivsc_trace_ptr + 1) & 127; 281 } 282 #endif 283 return 1; 284 } 285 286 void 287 bzivsc_dma_reset(struct ncr53c9x_softc *sc) 288 { 289 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 290 291 bsc->sc_active = 0; 292 } 293 294 int 295 bzivsc_dma_intr(struct ncr53c9x_softc *sc) 296 { 297 register struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 298 register int cnt; 299 300 NCR_DMA(("bzivsc_dma_intr: cnt %d int %x stat %x fifo %d ", 301 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 302 bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 303 if (bsc->sc_active == 0) { 304 printf("bzivsc_intr--inactive DMA\n"); 305 return -1; 306 } 307 308 /* update sc_dmaaddr and sc_pdmalen */ 309 cnt = bsc->sc_reg[NCR_TCL * 4]; 310 cnt += bsc->sc_reg[NCR_TCM * 4] << 8; 311 cnt += bsc->sc_reg[NCR_TCH * 4] << 16; 312 if (!bsc->sc_datain) { 313 cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 314 bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 315 } 316 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 317 NCR_DMA(("DMA xferred %d\n", cnt)); 318 if (bsc->sc_xfr_align) { 319 bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt); 320 bsc->sc_xfr_align = 0; 321 } 322 *bsc->sc_dmaaddr += cnt; 323 *bsc->sc_pdmalen -= cnt; 324 bsc->sc_active = 0; 325 return 0; 326 } 327 328 int 329 bzivsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 330 int datain, size_t *dmasize) 331 { 332 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 333 paddr_t pa; 334 u_char *ptr; 335 size_t xfer; 336 337 bsc->sc_dmaaddr = addr; 338 bsc->sc_pdmalen = len; 339 bsc->sc_datain = datain; 340 bsc->sc_dmasize = *dmasize; 341 /* 342 * DMA can be nasty for high-speed serial input, so limit the 343 * size of this DMA operation if the serial port is running at 344 * a high speed (higher than 19200 for now - should be adjusted 345 * based on cpu type and speed?). 346 * XXX - add serial speed check XXX 347 */ 348 if (ser_open_speed > 19200 && bzivsc_max_dma != 0 && 349 bsc->sc_dmasize > bzivsc_max_dma) 350 bsc->sc_dmasize = bzivsc_max_dma; 351 ptr = *addr; /* Kernel virtual address */ 352 pa = kvtop(ptr); /* Physical address of DMA */ 353 xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 354 bsc->sc_xfr_align = 0; 355 /* 356 * If output and unaligned, stuff odd byte into FIFO 357 */ 358 if (datain == 0 && (int)ptr & 1) { 359 NCR_DMA(("bzivsc_dma_setup: align byte written to fifo\n")); 360 pa++; 361 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 362 bsc->sc_reg[NCR_FIFO * 4] = *ptr++; 363 } 364 /* 365 * If unaligned address, read unaligned bytes into alignment buffer 366 */ 367 else if ((int)ptr & 1) { 368 pa = kvtop((caddr_t)&bsc->sc_alignbuf); 369 xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf)); 370 NCR_DMA(("bzivsc_dma_setup: align read by %d bytes\n", xfer)); 371 bsc->sc_xfr_align = 1; 372 } 373 ++bzivsc_cnt_dma; /* number of DMA operations */ 374 375 while (xfer < bsc->sc_dmasize) { 376 if ((pa + xfer) != kvtop(*addr + xfer)) 377 break; 378 if ((bsc->sc_dmasize - xfer) < NBPG) 379 xfer = bsc->sc_dmasize; 380 else 381 xfer += NBPG; 382 ++bzivsc_cnt_dma3; 383 } 384 if (xfer != *len) 385 ++bzivsc_cnt_dma2; 386 387 bsc->sc_dmasize = xfer; 388 *dmasize = bsc->sc_dmasize; 389 bsc->sc_pa = pa; 390 #if defined(M68040) || defined(M68060) 391 if (mmutype == MMU_68040) { 392 if (bsc->sc_xfr_align) { 393 dma_cachectl(bsc->sc_alignbuf, 394 sizeof(bsc->sc_alignbuf)); 395 } 396 else 397 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 398 } 399 #endif 400 401 pa >>= 1; 402 if (!bsc->sc_datain) 403 pa |= 0x80000000; 404 bsc->sc_dmabase[0x8000] = (u_int8_t)(pa >> 24); 405 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 406 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 16); 407 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 8); 408 bsc->sc_dmabase[0] = (u_int8_t)(pa); 409 bsc->sc_active = 1; 410 return 0; 411 } 412 413 void 414 bzivsc_dma_go(struct ncr53c9x_softc *sc) 415 { 416 } 417 418 void 419 bzivsc_dma_stop(struct ncr53c9x_softc *sc) 420 { 421 } 422 423 int 424 bzivsc_dma_isactive(struct ncr53c9x_softc *sc) 425 { 426 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 427 428 return bsc->sc_active; 429 } 430 431 #ifdef DEBUG 432 void 433 bzivsc_dump(void) 434 { 435 int i; 436 437 i = bzivsc_trace_ptr; 438 printf("bzivsc_trace dump: ptr %x\n", bzivsc_trace_ptr); 439 do { 440 if (bzivsc_trace[i].hardbits == 0) { 441 i = (i + 1) & 127; 442 continue; 443 } 444 printf("%02x%02x%02x%02x(", bzivsc_trace[i].hardbits, 445 bzivsc_trace[i].status, bzivsc_trace[i].xx, bzivsc_trace[i].yy); 446 if (bzivsc_trace[i].status & NCRSTAT_INT) 447 printf("NCRINT/"); 448 if (bzivsc_trace[i].status & NCRSTAT_TC) 449 printf("NCRTC/"); 450 switch(bzivsc_trace[i].status & NCRSTAT_PHASE) { 451 case 0: 452 printf("dataout"); break; 453 case 1: 454 printf("datain"); break; 455 case 2: 456 printf("cmdout"); break; 457 case 3: 458 printf("status"); break; 459 case 6: 460 printf("msgout"); break; 461 case 7: 462 printf("msgin"); break; 463 default: 464 printf("phase%d?", bzivsc_trace[i].status & NCRSTAT_PHASE); 465 } 466 printf(") "); 467 i = (i + 1) & 127; 468 } while (i != bzivsc_trace_ptr); 469 printf("\n"); 470 } 471 #endif 472