1 /* $NetBSD: bzsc.c,v 1.48 2010/12/20 00:25:25 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #ifdef __m68k__ 40 #include "opt_m68k_arch.h" 41 #endif 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: bzsc.c,v 1.48 2010/12/20 00:25:25 matt Exp $"); 45 46 /* 47 * Initial amiga Blizzard 1230-II driver by Daniel Widenfalk. Conversion to 48 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 49 */ 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/errno.h> 56 #include <sys/ioctl.h> 57 #include <sys/device.h> 58 #include <sys/buf.h> 59 #include <sys/proc.h> 60 #include <sys/queue.h> 61 62 #include <dev/scsipi/scsi_all.h> 63 #include <dev/scsipi/scsipi_all.h> 64 #include <dev/scsipi/scsiconf.h> 65 #include <dev/scsipi/scsi_message.h> 66 67 #include <machine/cpu.h> 68 #include <machine/param.h> 69 70 #include <dev/ic/ncr53c9xreg.h> 71 #include <dev/ic/ncr53c9xvar.h> 72 73 #include <amiga/amiga/isr.h> 74 #include <amiga/dev/bzscvar.h> 75 #include <amiga/dev/zbusvar.h> 76 77 #ifdef __powerpc__ 78 #define badaddr(a) badaddr_read(a, 2, NULL) 79 #endif 80 81 int bzscmatch(device_t, cfdata_t, void *); 82 void bzscattach(device_t, device_t, void *); 83 84 /* Linkup to the rest of the kernel */ 85 CFATTACH_DECL_NEW(bzsc, sizeof(struct bzsc_softc), 86 bzscmatch, bzscattach, NULL, NULL); 87 88 /* 89 * Functions and the switch for the MI code. 90 */ 91 uint8_t bzsc_read_reg(struct ncr53c9x_softc *, int); 92 void bzsc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 93 int bzsc_dma_isintr(struct ncr53c9x_softc *); 94 void bzsc_dma_reset(struct ncr53c9x_softc *); 95 int bzsc_dma_intr(struct ncr53c9x_softc *); 96 int bzsc_dma_setup(struct ncr53c9x_softc *, uint8_t **, 97 size_t *, int, size_t *); 98 void bzsc_dma_go(struct ncr53c9x_softc *); 99 void bzsc_dma_stop(struct ncr53c9x_softc *); 100 int bzsc_dma_isactive(struct ncr53c9x_softc *); 101 102 struct ncr53c9x_glue bzsc_glue = { 103 bzsc_read_reg, 104 bzsc_write_reg, 105 bzsc_dma_isintr, 106 bzsc_dma_reset, 107 bzsc_dma_intr, 108 bzsc_dma_setup, 109 bzsc_dma_go, 110 bzsc_dma_stop, 111 bzsc_dma_isactive, 112 NULL, 113 }; 114 115 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 116 u_long bzsc_max_dma = 1024; 117 extern int ser_open_speed; 118 119 u_long bzsc_cnt_pio = 0; /* number of PIO transfers */ 120 u_long bzsc_cnt_dma = 0; /* number of DMA transfers */ 121 u_long bzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 122 u_long bzsc_cnt_dma3 = 0; /* number of pages combined */ 123 124 #ifdef DEBUG 125 struct { 126 uint8_t hardbits; 127 uint8_t status; 128 uint8_t xx; 129 uint8_t yy; 130 } bzsc_trace[128]; 131 int bzsc_trace_ptr = 0; 132 int bzsc_trace_enable = 1; 133 void bzsc_dump(void); 134 #endif 135 136 /* 137 * if we are a Phase5 Blizzard 1230 II 138 */ 139 int 140 bzscmatch(device_t parent, cfdata_t cf, void *aux) 141 { 142 struct zbus_args *zap; 143 volatile uint8_t *regs; 144 145 zap = aux; 146 if (zap->manid != 0x2140 || zap->prodid != 11) 147 return 0; /* It's not Blizzard 1230 */ 148 if (!is_a1200()) 149 return 0; /* And not A1200 */ 150 regs = &((volatile uint8_t *)zap->va)[0x10000]; 151 if (badaddr((void *)__UNVOLATILE(regs))) 152 return 0; 153 regs[NCR_CFG1 * 2] = 0; 154 regs[NCR_CFG1 * 2] = NCRCFG1_PARENB | 7; 155 delay(5); 156 if (regs[NCR_CFG1 * 2] != (NCRCFG1_PARENB | 7)) 157 return 0; 158 return 1; 159 } 160 161 /* 162 * Attach this instance, and then all the sub-devices 163 */ 164 void 165 bzscattach(device_t parent, device_t self, void *aux) 166 { 167 struct bzsc_softc *bsc = device_private(self); 168 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 169 struct zbus_args *zap; 170 extern u_long scsi_nosync; 171 extern int shift_nosync; 172 extern int ncr53c9x_debug; 173 174 /* 175 * Set up the glue for MI code early; we use some of it here. 176 */ 177 sc->sc_dev = self; 178 sc->sc_glue = &bzsc_glue; 179 180 /* 181 * Save the regs 182 */ 183 zap = aux; 184 bsc->sc_reg = &((volatile uint8_t *)zap->va)[0x10000]; 185 bsc->sc_dmabase = &bsc->sc_reg[0x21]; 186 187 sc->sc_freq = 40; /* Clocked at 40 MHz */ 188 189 aprint_normal(": address %p", bsc->sc_reg); 190 191 sc->sc_id = 7; 192 193 /* 194 * It is necessary to try to load the 2nd config register here, 195 * to find out what rev the FAS chip is, else the ncr53c9x_reset 196 * will not set up the defaults correctly. 197 */ 198 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 199 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 200 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 201 sc->sc_rev = NCR_VARIANT_FAS216; 202 203 /* 204 * This is the value used to start sync negotiations 205 * Note that the NCR register "SYNCTP" is programmed 206 * in "clocks per byte", and has a minimum value of 4. 207 * The SCSI period used in negotiation is one-fourth 208 * of the time (in nanoseconds) needed to transfer one byte. 209 * Since the chip's clock is given in MHz, we have the following 210 * formula: 4 * period = (1000 / freq) * 4 211 */ 212 sc->sc_minsync = 1000 / sc->sc_freq; 213 214 /* 215 * get flags from -I argument and set cf_flags. 216 * NOTE: low 8 bits are to disable disconnect, and the next 217 * 8 bits are to disable sync. 218 */ 219 device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync) 220 & 0xffff; 221 shift_nosync += 16; 222 223 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 224 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 225 shift_nosync += 16; 226 227 #if 1 228 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 229 sc->sc_minsync = 0; 230 #endif 231 232 /* Really no limit, but since we want to fit into the TCR... */ 233 sc->sc_maxxfer = 64 * 1024; 234 235 /* 236 * Configure interrupts. 237 */ 238 bsc->sc_isr.isr_intr = ncr53c9x_intr; 239 bsc->sc_isr.isr_arg = sc; 240 bsc->sc_isr.isr_ipl = 2; 241 add_isr(&bsc->sc_isr); 242 243 /* 244 * Now try to attach all the sub-devices 245 */ 246 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 247 sc->sc_adapter.adapt_minphys = minphys; 248 ncr53c9x_attach(sc); 249 } 250 251 /* 252 * Glue functions. 253 */ 254 255 uint8_t 256 bzsc_read_reg(struct ncr53c9x_softc *sc, int reg) 257 { 258 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 259 260 return bsc->sc_reg[reg * 2]; 261 } 262 263 void 264 bzsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 265 { 266 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 267 uint8_t v = val; 268 269 bsc->sc_reg[reg * 2] = v; 270 #ifdef DEBUG 271 if (bzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 272 reg == NCR_CMD/* && bsc->sc_active*/) { 273 bzsc_trace[(bzsc_trace_ptr - 1) & 127].yy = v; 274 /* printf(" cmd %x", v);*/ 275 } 276 #endif 277 } 278 279 int 280 bzsc_dma_isintr(struct ncr53c9x_softc *sc) 281 { 282 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 283 284 if ((bsc->sc_reg[NCR_STAT * 2] & NCRSTAT_INT) == 0) 285 return 0; 286 287 #ifdef DEBUG 288 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bzsc_trace_enable) { 289 bzsc_trace[bzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 2]; 290 bzsc_trace[bzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 2]; 291 bzsc_trace[bzsc_trace_ptr].yy = bsc->sc_active; 292 bzsc_trace_ptr = (bzsc_trace_ptr + 1) & 127; 293 } 294 #endif 295 return 1; 296 } 297 298 void 299 bzsc_dma_reset(struct ncr53c9x_softc *sc) 300 { 301 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 302 303 bsc->sc_active = 0; 304 } 305 306 int 307 bzsc_dma_intr(struct ncr53c9x_softc *sc) 308 { 309 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 310 int cnt; 311 312 NCR_DMA(("bzsc_dma_intr: cnt %d int %x stat %x fifo %d ", 313 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 314 bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF)); 315 if (bsc->sc_active == 0) { 316 printf("bzsc_intr--inactive DMA\n"); 317 return -1; 318 } 319 320 /* update sc_dmaaddr and sc_pdmalen */ 321 cnt = bsc->sc_reg[NCR_TCL * 2]; 322 cnt += bsc->sc_reg[NCR_TCM * 2] << 8; 323 cnt += bsc->sc_reg[NCR_TCH * 2] << 16; 324 if (!bsc->sc_datain) { 325 cnt += bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF; 326 bsc->sc_reg[NCR_CMD * 2] = NCRCMD_FLUSH; 327 } 328 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 329 NCR_DMA(("DMA xferred %d\n", cnt)); 330 if (bsc->sc_xfr_align) { 331 memcpy(*bsc->sc_dmaaddr, bsc->sc_alignbuf, cnt); 332 bsc->sc_xfr_align = 0; 333 } 334 *bsc->sc_dmaaddr += cnt; 335 *bsc->sc_pdmalen -= cnt; 336 bsc->sc_active = 0; 337 return 0; 338 } 339 340 int 341 bzsc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 342 int datain, size_t *dmasize) 343 { 344 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 345 paddr_t pa; 346 uint8_t *ptr; 347 size_t xfer; 348 349 bsc->sc_dmaaddr = addr; 350 bsc->sc_pdmalen = len; 351 bsc->sc_datain = datain; 352 bsc->sc_dmasize = *dmasize; 353 /* 354 * DMA can be nasty for high-speed serial input, so limit the 355 * size of this DMA operation if the serial port is running at 356 * a high speed (higher than 19200 for now - should be adjusted 357 * based on CPU type and speed?). 358 * XXX - add serial speed check XXX 359 */ 360 if (ser_open_speed > 19200 && bzsc_max_dma != 0 && 361 bsc->sc_dmasize > bzsc_max_dma) 362 bsc->sc_dmasize = bzsc_max_dma; 363 ptr = *addr; /* Kernel virtual address */ 364 pa = kvtop(ptr); /* Physical address of DMA */ 365 xfer = min(bsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 366 bsc->sc_xfr_align = 0; 367 /* 368 * If output and unaligned, stuff odd byte into FIFO 369 */ 370 if (datain == 0 && (int)ptr & 1) { 371 NCR_DMA(("bzsc_dma_setup: align byte written to fifo\n")); 372 pa++; 373 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 374 bsc->sc_reg[NCR_FIFO * 2] = *ptr++; 375 } 376 /* 377 * If unaligned address, read unaligned bytes into alignment buffer 378 */ 379 else if ((int)ptr & 1) { 380 pa = kvtop((void *)&bsc->sc_alignbuf); 381 xfer = bsc->sc_dmasize = min(xfer, sizeof(bsc->sc_alignbuf)); 382 NCR_DMA(("bzsc_dma_setup: align read by %d bytes\n", xfer)); 383 bsc->sc_xfr_align = 1; 384 } 385 ++bzsc_cnt_dma; /* number of DMA operations */ 386 387 while (xfer < bsc->sc_dmasize) { 388 if ((pa + xfer) != kvtop(*addr + xfer)) 389 break; 390 if ((bsc->sc_dmasize - xfer) < PAGE_SIZE) 391 xfer = bsc->sc_dmasize; 392 else 393 xfer += PAGE_SIZE; 394 ++bzsc_cnt_dma3; 395 } 396 if (xfer != *len) 397 ++bzsc_cnt_dma2; 398 399 bsc->sc_dmasize = xfer; 400 *dmasize = bsc->sc_dmasize; 401 bsc->sc_pa = pa; 402 #if defined(M68040) || defined(M68060) 403 if (mmutype == MMU_68040) { 404 if (bsc->sc_xfr_align) { 405 dma_cachectl(bsc->sc_alignbuf, 406 sizeof(bsc->sc_alignbuf)); 407 } 408 else 409 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 410 } 411 #endif 412 413 pa >>= 1; 414 if (!bsc->sc_datain) 415 pa |= 0x80000000; 416 bsc->sc_dmabase[0x10] = (uint8_t)(pa >> 24); 417 bsc->sc_dmabase[0] = (uint8_t)(pa >> 16); 418 bsc->sc_dmabase[0] = (uint8_t)(pa >> 8); 419 bsc->sc_dmabase[0] = (uint8_t)(pa); 420 bsc->sc_active = 1; 421 return 0; 422 } 423 424 void 425 bzsc_dma_go(struct ncr53c9x_softc *sc) 426 { 427 } 428 429 void 430 bzsc_dma_stop(struct ncr53c9x_softc *sc) 431 { 432 } 433 434 int 435 bzsc_dma_isactive(struct ncr53c9x_softc *sc) 436 { 437 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 438 439 return bsc->sc_active; 440 } 441 442 #ifdef DEBUG 443 void 444 bzsc_dump(void) 445 { 446 int i; 447 448 i = bzsc_trace_ptr; 449 printf("bzsc_trace dump: ptr %x\n", bzsc_trace_ptr); 450 do { 451 if (bzsc_trace[i].hardbits == 0) { 452 i = (i + 1) & 127; 453 continue; 454 } 455 printf("%02x%02x%02x%02x(", bzsc_trace[i].hardbits, 456 bzsc_trace[i].status, bzsc_trace[i].xx, bzsc_trace[i].yy); 457 if (bzsc_trace[i].status & NCRSTAT_INT) 458 printf("NCRINT/"); 459 if (bzsc_trace[i].status & NCRSTAT_TC) 460 printf("NCRTC/"); 461 switch(bzsc_trace[i].status & NCRSTAT_PHASE) { 462 case 0: 463 printf("dataout"); break; 464 case 1: 465 printf("datain"); break; 466 case 2: 467 printf("cmdout"); break; 468 case 3: 469 printf("status"); break; 470 case 6: 471 printf("msgout"); break; 472 case 7: 473 printf("msgin"); break; 474 default: 475 printf("phase%d?", bzsc_trace[i].status & NCRSTAT_PHASE); 476 } 477 printf(") "); 478 i = (i + 1) & 127; 479 } while (i != bzsc_trace_ptr); 480 printf("\n"); 481 } 482 #endif 483