1 /* $NetBSD: bzsc.c,v 1.32 2002/10/02 04:55:48 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: bzsc.c,v 1.32 2002/10/02 04:55:48 thorpej Exp $"); 41 42 /* 43 * Initial amiga Blizzard 1230-II driver by Daniel Widenfalk. Conversion to 44 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 45 */ 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 #include <sys/proc.h> 56 #include <sys/user.h> 57 #include <sys/queue.h> 58 59 #include <dev/scsipi/scsi_all.h> 60 #include <dev/scsipi/scsipi_all.h> 61 #include <dev/scsipi/scsiconf.h> 62 #include <dev/scsipi/scsi_message.h> 63 64 #include <machine/cpu.h> 65 #include <machine/param.h> 66 67 #include <dev/ic/ncr53c9xreg.h> 68 #include <dev/ic/ncr53c9xvar.h> 69 70 #include <amiga/amiga/isr.h> 71 #include <amiga/dev/bzscvar.h> 72 #include <amiga/dev/zbusvar.h> 73 74 void bzscattach(struct device *, struct device *, void *); 75 int bzscmatch(struct device *, struct cfdata *, void *); 76 77 /* Linkup to the rest of the kernel */ 78 CFATTACH_DECL(bzsc, sizeof(struct bzsc_softc), 79 bzscmatch, bzscattach, NULL, NULL); 80 81 /* 82 * Functions and the switch for the MI code. 83 */ 84 u_char bzsc_read_reg(struct ncr53c9x_softc *, int); 85 void bzsc_write_reg(struct ncr53c9x_softc *, int, u_char); 86 int bzsc_dma_isintr(struct ncr53c9x_softc *); 87 void bzsc_dma_reset(struct ncr53c9x_softc *); 88 int bzsc_dma_intr(struct ncr53c9x_softc *); 89 int bzsc_dma_setup(struct ncr53c9x_softc *, caddr_t *, 90 size_t *, int, size_t *); 91 void bzsc_dma_go(struct ncr53c9x_softc *); 92 void bzsc_dma_stop(struct ncr53c9x_softc *); 93 int bzsc_dma_isactive(struct ncr53c9x_softc *); 94 95 struct ncr53c9x_glue bzsc_glue = { 96 bzsc_read_reg, 97 bzsc_write_reg, 98 bzsc_dma_isintr, 99 bzsc_dma_reset, 100 bzsc_dma_intr, 101 bzsc_dma_setup, 102 bzsc_dma_go, 103 bzsc_dma_stop, 104 bzsc_dma_isactive, 105 0, 106 }; 107 108 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 109 u_long bzsc_max_dma = 1024; 110 extern int ser_open_speed; 111 112 u_long bzsc_cnt_pio = 0; /* number of PIO transfers */ 113 u_long bzsc_cnt_dma = 0; /* number of DMA transfers */ 114 u_long bzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 115 u_long bzsc_cnt_dma3 = 0; /* number of pages combined */ 116 117 #ifdef DEBUG 118 struct { 119 u_char hardbits; 120 u_char status; 121 u_char xx; 122 u_char yy; 123 } bzsc_trace[128]; 124 int bzsc_trace_ptr = 0; 125 int bzsc_trace_enable = 1; 126 void bzsc_dump(void); 127 #endif 128 129 /* 130 * if we are a Phase5 Blizzard 1230 II 131 */ 132 int 133 bzscmatch(struct device *parent, struct cfdata *cf, void *aux) 134 { 135 struct zbus_args *zap; 136 volatile u_char *regs; 137 138 zap = aux; 139 if (zap->manid != 0x2140 || zap->prodid != 11) 140 return(0); /* It's not Blizzard 1230 */ 141 if (!is_a1200()) 142 return(0); /* And not A1200 */ 143 regs = &((volatile u_char *)zap->va)[0x10000]; 144 if (badaddr((caddr_t)regs)) 145 return(0); 146 regs[NCR_CFG1 * 2] = 0; 147 regs[NCR_CFG1 * 2] = NCRCFG1_PARENB | 7; 148 delay(5); 149 if (regs[NCR_CFG1 * 2] != (NCRCFG1_PARENB | 7)) 150 return(0); 151 return(1); 152 } 153 154 /* 155 * Attach this instance, and then all the sub-devices 156 */ 157 void 158 bzscattach(struct device *parent, struct device *self, void *aux) 159 { 160 struct bzsc_softc *bsc = (void *)self; 161 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 162 struct zbus_args *zap; 163 extern u_long scsi_nosync; 164 extern int shift_nosync; 165 extern int ncr53c9x_debug; 166 167 /* 168 * Set up the glue for MI code early; we use some of it here. 169 */ 170 sc->sc_glue = &bzsc_glue; 171 172 /* 173 * Save the regs 174 */ 175 zap = aux; 176 bsc->sc_reg = &((volatile u_char *)zap->va)[0x10000]; 177 bsc->sc_dmabase = &bsc->sc_reg[0x21]; 178 179 sc->sc_freq = 40; /* Clocked at 40Mhz */ 180 181 printf(": address %p", bsc->sc_reg); 182 183 sc->sc_id = 7; 184 185 /* 186 * It is necessary to try to load the 2nd config register here, 187 * to find out what rev the FAS chip is, else the ncr53c9x_reset 188 * will not set up the defaults correctly. 189 */ 190 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 191 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 192 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 193 sc->sc_rev = NCR_VARIANT_FAS216; 194 195 /* 196 * This is the value used to start sync negotiations 197 * Note that the NCR register "SYNCTP" is programmed 198 * in "clocks per byte", and has a minimum value of 4. 199 * The SCSI period used in negotiation is one-fourth 200 * of the time (in nanoseconds) needed to transfer one byte. 201 * Since the chip's clock is given in MHz, we have the following 202 * formula: 4 * period = (1000 / freq) * 4 203 */ 204 sc->sc_minsync = 1000 / sc->sc_freq; 205 206 /* 207 * get flags from -I argument and set cf_flags. 208 * NOTE: low 8 bits are to disable disconnect, and the next 209 * 8 bits are to disable sync. 210 */ 211 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 212 & 0xffff; 213 shift_nosync += 16; 214 215 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 216 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 217 shift_nosync += 16; 218 219 #if 1 220 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 221 sc->sc_minsync = 0; 222 #endif 223 224 /* Really no limit, but since we want to fit into the TCR... */ 225 sc->sc_maxxfer = 64 * 1024; 226 227 /* 228 * Configure interrupts. 229 */ 230 bsc->sc_isr.isr_intr = ncr53c9x_intr; 231 bsc->sc_isr.isr_arg = sc; 232 bsc->sc_isr.isr_ipl = 2; 233 add_isr(&bsc->sc_isr); 234 235 /* 236 * Now try to attach all the sub-devices 237 */ 238 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 239 sc->sc_adapter.adapt_minphys = minphys; 240 ncr53c9x_attach(sc); 241 } 242 243 /* 244 * Glue functions. 245 */ 246 247 u_char 248 bzsc_read_reg(struct ncr53c9x_softc *sc, int reg) 249 { 250 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 251 252 return bsc->sc_reg[reg * 2]; 253 } 254 255 void 256 bzsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 257 { 258 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 259 u_char v = val; 260 261 bsc->sc_reg[reg * 2] = v; 262 #ifdef DEBUG 263 if (bzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 264 reg == NCR_CMD/* && bsc->sc_active*/) { 265 bzsc_trace[(bzsc_trace_ptr - 1) & 127].yy = v; 266 /* printf(" cmd %x", v);*/ 267 } 268 #endif 269 } 270 271 int 272 bzsc_dma_isintr(struct ncr53c9x_softc *sc) 273 { 274 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 275 276 if ((bsc->sc_reg[NCR_STAT * 2] & NCRSTAT_INT) == 0) 277 return 0; 278 279 #ifdef DEBUG 280 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bzsc_trace_enable) { 281 bzsc_trace[bzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 2]; 282 bzsc_trace[bzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 2]; 283 bzsc_trace[bzsc_trace_ptr].yy = bsc->sc_active; 284 bzsc_trace_ptr = (bzsc_trace_ptr + 1) & 127; 285 } 286 #endif 287 return 1; 288 } 289 290 void 291 bzsc_dma_reset(struct ncr53c9x_softc *sc) 292 { 293 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 294 295 bsc->sc_active = 0; 296 } 297 298 int 299 bzsc_dma_intr(struct ncr53c9x_softc *sc) 300 { 301 register struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 302 register int cnt; 303 304 NCR_DMA(("bzsc_dma_intr: cnt %d int %x stat %x fifo %d ", 305 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 306 bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF)); 307 if (bsc->sc_active == 0) { 308 printf("bzsc_intr--inactive DMA\n"); 309 return -1; 310 } 311 312 /* update sc_dmaaddr and sc_pdmalen */ 313 cnt = bsc->sc_reg[NCR_TCL * 2]; 314 cnt += bsc->sc_reg[NCR_TCM * 2] << 8; 315 cnt += bsc->sc_reg[NCR_TCH * 2] << 16; 316 if (!bsc->sc_datain) { 317 cnt += bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF; 318 bsc->sc_reg[NCR_CMD * 2] = NCRCMD_FLUSH; 319 } 320 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 321 NCR_DMA(("DMA xferred %d\n", cnt)); 322 if (bsc->sc_xfr_align) { 323 bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt); 324 bsc->sc_xfr_align = 0; 325 } 326 *bsc->sc_dmaaddr += cnt; 327 *bsc->sc_pdmalen -= cnt; 328 bsc->sc_active = 0; 329 return 0; 330 } 331 332 int 333 bzsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 334 int datain, size_t *dmasize) 335 { 336 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 337 paddr_t pa; 338 u_char *ptr; 339 size_t xfer; 340 341 bsc->sc_dmaaddr = addr; 342 bsc->sc_pdmalen = len; 343 bsc->sc_datain = datain; 344 bsc->sc_dmasize = *dmasize; 345 /* 346 * DMA can be nasty for high-speed serial input, so limit the 347 * size of this DMA operation if the serial port is running at 348 * a high speed (higher than 19200 for now - should be adjusted 349 * based on cpu type and speed?). 350 * XXX - add serial speed check XXX 351 */ 352 if (ser_open_speed > 19200 && bzsc_max_dma != 0 && 353 bsc->sc_dmasize > bzsc_max_dma) 354 bsc->sc_dmasize = bzsc_max_dma; 355 ptr = *addr; /* Kernel virtual address */ 356 pa = kvtop(ptr); /* Physical address of DMA */ 357 xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 358 bsc->sc_xfr_align = 0; 359 /* 360 * If output and unaligned, stuff odd byte into FIFO 361 */ 362 if (datain == 0 && (int)ptr & 1) { 363 NCR_DMA(("bzsc_dma_setup: align byte written to fifo\n")); 364 pa++; 365 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 366 bsc->sc_reg[NCR_FIFO * 2] = *ptr++; 367 } 368 /* 369 * If unaligned address, read unaligned bytes into alignment buffer 370 */ 371 else if ((int)ptr & 1) { 372 pa = kvtop((caddr_t)&bsc->sc_alignbuf); 373 xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf)); 374 NCR_DMA(("bzsc_dma_setup: align read by %d bytes\n", xfer)); 375 bsc->sc_xfr_align = 1; 376 } 377 ++bzsc_cnt_dma; /* number of DMA operations */ 378 379 while (xfer < bsc->sc_dmasize) { 380 if ((pa + xfer) != kvtop(*addr + xfer)) 381 break; 382 if ((bsc->sc_dmasize - xfer) < NBPG) 383 xfer = bsc->sc_dmasize; 384 else 385 xfer += NBPG; 386 ++bzsc_cnt_dma3; 387 } 388 if (xfer != *len) 389 ++bzsc_cnt_dma2; 390 391 bsc->sc_dmasize = xfer; 392 *dmasize = bsc->sc_dmasize; 393 bsc->sc_pa = pa; 394 #if defined(M68040) || defined(M68060) 395 if (mmutype == MMU_68040) { 396 if (bsc->sc_xfr_align) { 397 dma_cachectl(bsc->sc_alignbuf, 398 sizeof(bsc->sc_alignbuf)); 399 } 400 else 401 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 402 } 403 #endif 404 405 pa >>= 1; 406 if (!bsc->sc_datain) 407 pa |= 0x80000000; 408 bsc->sc_dmabase[0x10] = (u_int8_t)(pa >> 24); 409 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 16); 410 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 8); 411 bsc->sc_dmabase[0] = (u_int8_t)(pa); 412 bsc->sc_active = 1; 413 return 0; 414 } 415 416 void 417 bzsc_dma_go(struct ncr53c9x_softc *sc) 418 { 419 } 420 421 void 422 bzsc_dma_stop(struct ncr53c9x_softc *sc) 423 { 424 } 425 426 int 427 bzsc_dma_isactive(struct ncr53c9x_softc *sc) 428 { 429 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 430 431 return bsc->sc_active; 432 } 433 434 #ifdef DEBUG 435 void 436 bzsc_dump(void) 437 { 438 int i; 439 440 i = bzsc_trace_ptr; 441 printf("bzsc_trace dump: ptr %x\n", bzsc_trace_ptr); 442 do { 443 if (bzsc_trace[i].hardbits == 0) { 444 i = (i + 1) & 127; 445 continue; 446 } 447 printf("%02x%02x%02x%02x(", bzsc_trace[i].hardbits, 448 bzsc_trace[i].status, bzsc_trace[i].xx, bzsc_trace[i].yy); 449 if (bzsc_trace[i].status & NCRSTAT_INT) 450 printf("NCRINT/"); 451 if (bzsc_trace[i].status & NCRSTAT_TC) 452 printf("NCRTC/"); 453 switch(bzsc_trace[i].status & NCRSTAT_PHASE) { 454 case 0: 455 printf("dataout"); break; 456 case 1: 457 printf("datain"); break; 458 case 2: 459 printf("cmdout"); break; 460 case 3: 461 printf("status"); break; 462 case 6: 463 printf("msgout"); break; 464 case 7: 465 printf("msgin"); break; 466 default: 467 printf("phase%d?", bzsc_trace[i].status & NCRSTAT_PHASE); 468 } 469 printf(") "); 470 i = (i + 1) & 127; 471 } while (i != bzsc_trace_ptr); 472 printf("\n"); 473 } 474 #endif 475