xref: /netbsd/sys/arch/amiga/dev/bztzsc.c (revision bf9ec67e) 
1 /*	$NetBSD: bztzsc.c,v 1.17 2002/01/28 09:56:52 aymeric Exp $ */
2 
3 /*
4  * Copyright (c) 1997 Michael L. Hitch
5  * Copyright (c) 1996 Ignatios Souvatzis
6  * Copyright (c) 1982, 1990 The Regents of the University of California.
7  * All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product contains software written by Ignatios Souvatzis and
20  *	Michael L. Hitch for the NetBSD project.
21  * 4. Neither the name of the University nor the names of its contributors
22  *    may be used to endorse or promote products derived from this software
23  *    without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35  * SUCH DAMAGE.
36  *
37  */
38 
39 /*
40  * Initial amiga Blizzard 2060 driver by Ingatios Souvatzis.  Conversion to
41  * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu).
42  */
43 
44 #include <sys/cdefs.h>
45 __KERNEL_RCSID(0, "$NetBSD: bztzsc.c,v 1.17 2002/01/28 09:56:52 aymeric Exp $");
46 
47 #include <sys/types.h>
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
51 #include <sys/errno.h>
52 #include <sys/ioctl.h>
53 #include <sys/device.h>
54 #include <sys/buf.h>
55 #include <sys/proc.h>
56 #include <sys/user.h>
57 #include <sys/queue.h>
58 
59 #include <dev/scsipi/scsi_all.h>
60 #include <dev/scsipi/scsipi_all.h>
61 #include <dev/scsipi/scsiconf.h>
62 #include <dev/scsipi/scsi_message.h>
63 
64 #include <machine/cpu.h>
65 #include <machine/param.h>
66 
67 #include <dev/ic/ncr53c9xreg.h>
68 #include <dev/ic/ncr53c9xvar.h>
69 
70 #include <amiga/amiga/isr.h>
71 #include <amiga/dev/bztzscvar.h>
72 #include <amiga/dev/zbusvar.h>
73 
74 void	bztzscattach(struct device *, struct device *, void *);
75 int	bztzscmatch(struct device *, struct cfdata *, void *);
76 
77 /* Linkup to the rest of the kernel */
78 struct cfattach bztzsc_ca = {
79 	sizeof(struct bztzsc_softc), bztzscmatch, bztzscattach
80 };
81 
82 /*
83  * Functions and the switch for the MI code.
84  */
85 u_char	bztzsc_read_reg(struct ncr53c9x_softc *, int);
86 void	bztzsc_write_reg(struct ncr53c9x_softc *, int, u_char);
87 int	bztzsc_dma_isintr(struct ncr53c9x_softc *);
88 void	bztzsc_dma_reset(struct ncr53c9x_softc *);
89 int	bztzsc_dma_intr(struct ncr53c9x_softc *);
90 int	bztzsc_dma_setup(struct ncr53c9x_softc *, caddr_t *,
91 	    size_t *, int, size_t *);
92 void	bztzsc_dma_go(struct ncr53c9x_softc *);
93 void	bztzsc_dma_stop(struct ncr53c9x_softc *);
94 int	bztzsc_dma_isactive(struct ncr53c9x_softc *);
95 
96 struct ncr53c9x_glue bztzsc_glue = {
97 	bztzsc_read_reg,
98 	bztzsc_write_reg,
99 	bztzsc_dma_isintr,
100 	bztzsc_dma_reset,
101 	bztzsc_dma_intr,
102 	bztzsc_dma_setup,
103 	bztzsc_dma_go,
104 	bztzsc_dma_stop,
105 	bztzsc_dma_isactive,
106 	0,
107 };
108 
109 /* Maximum DMA transfer length to reduce impact on high-speed serial input */
110 u_long bztzsc_max_dma = 1024;
111 extern int ser_open_speed;
112 
113 u_long bztzsc_cnt_pio = 0;	/* number of PIO transfers */
114 u_long bztzsc_cnt_dma = 0;	/* number of DMA transfers */
115 u_long bztzsc_cnt_dma2 = 0;	/* number of DMA transfers broken up */
116 u_long bztzsc_cnt_dma3 = 0;	/* number of pages combined */
117 
118 #ifdef DEBUG
119 struct {
120 	u_char hardbits;
121 	u_char status;
122 	u_char xx;
123 	u_char yy;
124 } bztzsc_trace[128];
125 int bztzsc_trace_ptr = 0;
126 int bztzsc_trace_enable = 1;
127 void bztzsc_dump(void);
128 #endif
129 
130 /*
131  * if we are a Phase5 Blizzard 2060 SCSI
132  */
133 int
134 bztzscmatch(struct device *parent, struct cfdata *cf, void *aux)
135 {
136 	struct zbus_args *zap;
137 	volatile u_char *regs;
138 
139 	zap = aux;
140 	if (zap->manid != 0x2140 || zap->prodid != 24)
141 		return(0);
142 	regs = &((volatile u_char *)zap->va)[0x1ff00];
143 	if (badaddr((caddr_t)regs))
144 		return(0);
145 	regs[NCR_CFG1 * 4] = 0;
146 	regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
147 	delay(5);
148 	if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
149 		return(0);
150 	return(1);
151 }
152 
153 /*
154  * Attach this instance, and then all the sub-devices
155  */
156 void
157 bztzscattach(struct device *parent, struct device *self, void *aux)
158 {
159 	struct bztzsc_softc *bsc = (void *)self;
160 	struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x;
161 	struct zbus_args  *zap;
162 	extern u_long scsi_nosync;
163 	extern int shift_nosync;
164 	extern int ncr53c9x_debug;
165 
166 	/*
167 	 * Set up the glue for MI code early; we use some of it here.
168 	 */
169 	sc->sc_glue = &bztzsc_glue;
170 
171 	/*
172 	 * Save the regs
173 	 */
174 	zap = aux;
175 	bsc->sc_reg = &((volatile u_char *)zap->va)[0x1ff00];
176 	bsc->sc_dmabase = &bsc->sc_reg[0xf0];
177 
178 	sc->sc_freq = 40;		/* Clocked at 40Mhz */
179 
180 	printf(": address %p", bsc->sc_reg);
181 
182 	sc->sc_id = 7;
183 
184 	/*
185 	 * It is necessary to try to load the 2nd config register here,
186 	 * to find out what rev the FAS chip is, else the ncr53c9x_reset
187 	 * will not set up the defaults correctly.
188 	 */
189 	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
190 	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
191 	sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
192 	sc->sc_rev = NCR_VARIANT_FAS216;
193 
194 	/*
195 	 * This is the value used to start sync negotiations
196 	 * Note that the NCR register "SYNCTP" is programmed
197 	 * in "clocks per byte", and has a minimum value of 4.
198 	 * The SCSI period used in negotiation is one-fourth
199 	 * of the time (in nanoseconds) needed to transfer one byte.
200 	 * Since the chip's clock is given in MHz, we have the following
201 	 * formula: 4 * period = (1000 / freq) * 4
202 	 */
203 	sc->sc_minsync = 1000 / sc->sc_freq;
204 
205 	/*
206 	 * get flags from -I argument and set cf_flags.
207 	 * NOTE: low 8 bits are to disable disconnect, and the next
208 	 *       8 bits are to disable sync.
209 	 */
210 	sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
211 	    & 0xffff;
212 	shift_nosync += 16;
213 
214 	/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
215 	ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
216 	shift_nosync += 16;
217 
218 #if 1
219 	if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
220 		sc->sc_minsync = 0;
221 #endif
222 
223 	/* Really no limit, but since we want to fit into the TCR... */
224 	sc->sc_maxxfer = 64 * 1024;
225 
226 	bsc->sc_reg[0xe0] = BZTZSC_PB_LED;	/* Turn LED off */
227 
228 	/*
229 	 * Configure interrupts.
230 	 */
231 	bsc->sc_isr.isr_intr = ncr53c9x_intr;
232 	bsc->sc_isr.isr_arg  = sc;
233 	bsc->sc_isr.isr_ipl  = 2;
234 	add_isr(&bsc->sc_isr);
235 
236 	/*
237 	 * Now try to attach all the sub-devices
238 	 */
239 	sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
240 	sc->sc_adapter.adapt_minphys = minphys;
241 	ncr53c9x_attach(sc);
242 }
243 
244 /*
245  * Glue functions.
246  */
247 
248 u_char
249 bztzsc_read_reg(struct ncr53c9x_softc *sc, int reg)
250 {
251 	struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
252 
253 	return bsc->sc_reg[reg * 4];
254 }
255 
256 void
257 bztzsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val)
258 {
259 	struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
260 	u_char v = val;
261 
262 	bsc->sc_reg[reg * 4] = v;
263 #ifdef DEBUG
264 if (bztzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ &&
265   reg == NCR_CMD/* && bsc->sc_active*/) {
266   bztzsc_trace[(bztzsc_trace_ptr - 1) & 127].yy = v;
267 /*  printf(" cmd %x", v);*/
268 }
269 #endif
270 }
271 
272 int
273 bztzsc_dma_isintr(struct ncr53c9x_softc *sc)
274 {
275 	struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
276 
277 	if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
278 		return 0;
279 
280 	if (sc->sc_state == NCR_CONNECTED)
281 		bsc->sc_reg[0xe0] = 0;			/* Turn LED on */
282 	else
283 		bsc->sc_reg[0xe0] = BZTZSC_PB_LED;	/* Turn LED off */
284 
285 #ifdef DEBUG
286 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bztzsc_trace_enable) {
287   bztzsc_trace[bztzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4];
288   bztzsc_trace[bztzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4];
289   bztzsc_trace[bztzsc_trace_ptr].yy = bsc->sc_active;
290   bztzsc_trace_ptr = (bztzsc_trace_ptr + 1) & 127;
291 }
292 #endif
293 	return 1;
294 }
295 
296 void
297 bztzsc_dma_reset(struct ncr53c9x_softc *sc)
298 {
299 	struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
300 
301 	bsc->sc_active = 0;
302 }
303 
304 int
305 bztzsc_dma_intr(struct ncr53c9x_softc *sc)
306 {
307 	register struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
308 	register int	cnt;
309 
310 	NCR_DMA(("bztzsc_dma_intr: cnt %d int %x stat %x fifo %d ",
311 	    bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
312 	    bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
313 	if (bsc->sc_active == 0) {
314 		printf("bztzsc_intr--inactive DMA\n");
315 		return -1;
316 	}
317 
318 	/* update sc_dmaaddr and sc_pdmalen */
319 	cnt = bsc->sc_reg[NCR_TCL * 4];
320 	cnt += bsc->sc_reg[NCR_TCM * 4] << 8;
321 	cnt += bsc->sc_reg[NCR_TCH * 4] << 16;
322 	if (!bsc->sc_datain) {
323 		cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
324 		bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
325 	}
326 	cnt = bsc->sc_dmasize - cnt;	/* number of bytes transferred */
327 	NCR_DMA(("DMA xferred %d\n", cnt));
328 	if (bsc->sc_xfr_align) {
329 		bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt);
330 		bsc->sc_xfr_align = 0;
331 	}
332 	*bsc->sc_dmaaddr += cnt;
333 	*bsc->sc_pdmalen -= cnt;
334 	bsc->sc_active = 0;
335 	return 0;
336 }
337 
338 int
339 bztzsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len,
340                  int datain, size_t *dmasize)
341 {
342 	struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
343 	paddr_t pa;
344 	u_char *ptr;
345 	size_t xfer;
346 
347 	bsc->sc_dmaaddr = addr;
348 	bsc->sc_pdmalen = len;
349 	bsc->sc_datain = datain;
350 	bsc->sc_dmasize = *dmasize;
351 	/*
352 	 * DMA can be nasty for high-speed serial input, so limit the
353 	 * size of this DMA operation if the serial port is running at
354 	 * a high speed (higher than 19200 for now - should be adjusted
355 	 * based on cpu type and speed?).
356 	 * XXX - add serial speed check XXX
357 	 */
358 	if (ser_open_speed > 19200 && bztzsc_max_dma != 0 &&
359 	    bsc->sc_dmasize > bztzsc_max_dma)
360 		bsc->sc_dmasize = bztzsc_max_dma;
361 	ptr = *addr;			/* Kernel virtual address */
362 	pa = kvtop(ptr);		/* Physical address of DMA */
363 	xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
364 	bsc->sc_xfr_align = 0;
365 	/*
366 	 * If output and unaligned, stuff odd byte into FIFO
367 	 */
368 	if (datain == 0 && (int)ptr & 1) {
369 		NCR_DMA(("bztzsc_dma_setup: align byte written to fifo\n"));
370 		pa++;
371 		xfer--;			/* XXXX CHECK THIS !!!! XXXX */
372 		bsc->sc_reg[NCR_FIFO * 4] = *ptr++;
373 	}
374 	/*
375 	 * If unaligned address, read unaligned bytes into alignment buffer
376 	 */
377 	else if ((int)ptr & 1) {
378 		pa = kvtop((caddr_t)&bsc->sc_alignbuf);
379 		xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf));
380 		NCR_DMA(("bztzsc_dma_setup: align read by %d bytes\n", xfer));
381 		bsc->sc_xfr_align = 1;
382 	}
383 ++bztzsc_cnt_dma;		/* number of DMA operations */
384 
385 	while (xfer < bsc->sc_dmasize) {
386 		if ((pa + xfer) != kvtop(*addr + xfer))
387 			break;
388 		if ((bsc->sc_dmasize - xfer) < NBPG)
389 			xfer = bsc->sc_dmasize;
390 		else
391 			xfer += NBPG;
392 ++bztzsc_cnt_dma3;
393 	}
394 if (xfer != *len)
395   ++bztzsc_cnt_dma2;
396 
397 	bsc->sc_dmasize = xfer;
398 	*dmasize = bsc->sc_dmasize;
399 	bsc->sc_pa = pa;
400 #if defined(M68040) || defined(M68060)
401 	if (mmutype == MMU_68040) {
402 		if (bsc->sc_xfr_align) {
403 			dma_cachectl(bsc->sc_alignbuf,
404 			    sizeof(bsc->sc_alignbuf));
405 		}
406 		else
407 			dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize);
408 	}
409 #endif
410 
411 	pa >>= 1;
412 	if (!bsc->sc_datain)
413 		pa |= 0x80000000;
414 	bsc->sc_dmabase[12] = (u_int8_t)(pa);
415 	bsc->sc_dmabase[8] = (u_int8_t)(pa >> 8);
416 	bsc->sc_dmabase[4] = (u_int8_t)(pa >> 16);
417 	bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
418 	bsc->sc_active = 1;
419 	return 0;
420 }
421 
422 void
423 bztzsc_dma_go(struct ncr53c9x_softc *sc)
424 {
425 }
426 
427 void
428 bztzsc_dma_stop(struct ncr53c9x_softc *sc)
429 {
430 }
431 
432 int
433 bztzsc_dma_isactive(struct ncr53c9x_softc *sc)
434 {
435 	struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
436 
437 	return bsc->sc_active;
438 }
439 
440 #ifdef DEBUG
441 void
442 bztzsc_dump(void)
443 {
444 	int i;
445 
446 	i = bztzsc_trace_ptr;
447 	printf("bztzsc_trace dump: ptr %x\n", bztzsc_trace_ptr);
448 	do {
449 		if (bztzsc_trace[i].hardbits == 0) {
450 			i = (i + 1) & 127;
451 			continue;
452 		}
453 		printf("%02x%02x%02x%02x(", bztzsc_trace[i].hardbits,
454 		    bztzsc_trace[i].status, bztzsc_trace[i].xx, bztzsc_trace[i].yy);
455 		if (bztzsc_trace[i].status & NCRSTAT_INT)
456 			printf("NCRINT/");
457 		if (bztzsc_trace[i].status & NCRSTAT_TC)
458 			printf("NCRTC/");
459 		switch(bztzsc_trace[i].status & NCRSTAT_PHASE) {
460 		case 0:
461 			printf("dataout"); break;
462 		case 1:
463 			printf("datain"); break;
464 		case 2:
465 			printf("cmdout"); break;
466 		case 3:
467 			printf("status"); break;
468 		case 6:
469 			printf("msgout"); break;
470 		case 7:
471 			printf("msgin"); break;
472 		default:
473 			printf("phase%d?", bztzsc_trace[i].status & NCRSTAT_PHASE);
474 		}
475 		printf(") ");
476 		i = (i + 1) & 127;
477 	} while (i != bztzsc_trace_ptr);
478 	printf("\n");
479 }
480 #endif
481