1 /* $NetBSD: bztzsc.c,v 1.19 2002/10/02 04:55:48 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1996 Ignatios Souvatzis 6 * Copyright (c) 1982, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product contains software written by Ignatios Souvatzis and 20 * Michael L. Hitch for the NetBSD project. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 /* 40 * Initial amiga Blizzard 2060 driver by Ingatios Souvatzis. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: bztzsc.c,v 1.19 2002/10/02 04:55:48 thorpej Exp $"); 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 #include <sys/proc.h> 56 #include <sys/user.h> 57 #include <sys/queue.h> 58 59 #include <dev/scsipi/scsi_all.h> 60 #include <dev/scsipi/scsipi_all.h> 61 #include <dev/scsipi/scsiconf.h> 62 #include <dev/scsipi/scsi_message.h> 63 64 #include <machine/cpu.h> 65 #include <machine/param.h> 66 67 #include <dev/ic/ncr53c9xreg.h> 68 #include <dev/ic/ncr53c9xvar.h> 69 70 #include <amiga/amiga/isr.h> 71 #include <amiga/dev/bztzscvar.h> 72 #include <amiga/dev/zbusvar.h> 73 74 void bztzscattach(struct device *, struct device *, void *); 75 int bztzscmatch(struct device *, struct cfdata *, void *); 76 77 /* Linkup to the rest of the kernel */ 78 CFATTACH_DECL(bztzsc, sizeof(struct bztzsc_softc), 79 bztzscmatch, bztzscattach, NULL, NULL); 80 81 /* 82 * Functions and the switch for the MI code. 83 */ 84 u_char bztzsc_read_reg(struct ncr53c9x_softc *, int); 85 void bztzsc_write_reg(struct ncr53c9x_softc *, int, u_char); 86 int bztzsc_dma_isintr(struct ncr53c9x_softc *); 87 void bztzsc_dma_reset(struct ncr53c9x_softc *); 88 int bztzsc_dma_intr(struct ncr53c9x_softc *); 89 int bztzsc_dma_setup(struct ncr53c9x_softc *, caddr_t *, 90 size_t *, int, size_t *); 91 void bztzsc_dma_go(struct ncr53c9x_softc *); 92 void bztzsc_dma_stop(struct ncr53c9x_softc *); 93 int bztzsc_dma_isactive(struct ncr53c9x_softc *); 94 95 struct ncr53c9x_glue bztzsc_glue = { 96 bztzsc_read_reg, 97 bztzsc_write_reg, 98 bztzsc_dma_isintr, 99 bztzsc_dma_reset, 100 bztzsc_dma_intr, 101 bztzsc_dma_setup, 102 bztzsc_dma_go, 103 bztzsc_dma_stop, 104 bztzsc_dma_isactive, 105 0, 106 }; 107 108 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 109 u_long bztzsc_max_dma = 1024; 110 extern int ser_open_speed; 111 112 u_long bztzsc_cnt_pio = 0; /* number of PIO transfers */ 113 u_long bztzsc_cnt_dma = 0; /* number of DMA transfers */ 114 u_long bztzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 115 u_long bztzsc_cnt_dma3 = 0; /* number of pages combined */ 116 117 #ifdef DEBUG 118 struct { 119 u_char hardbits; 120 u_char status; 121 u_char xx; 122 u_char yy; 123 } bztzsc_trace[128]; 124 int bztzsc_trace_ptr = 0; 125 int bztzsc_trace_enable = 1; 126 void bztzsc_dump(void); 127 #endif 128 129 /* 130 * if we are a Phase5 Blizzard 2060 SCSI 131 */ 132 int 133 bztzscmatch(struct device *parent, struct cfdata *cf, void *aux) 134 { 135 struct zbus_args *zap; 136 volatile u_char *regs; 137 138 zap = aux; 139 if (zap->manid != 0x2140 || zap->prodid != 24) 140 return(0); 141 regs = &((volatile u_char *)zap->va)[0x1ff00]; 142 if (badaddr((caddr_t)regs)) 143 return(0); 144 regs[NCR_CFG1 * 4] = 0; 145 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 146 delay(5); 147 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 148 return(0); 149 return(1); 150 } 151 152 /* 153 * Attach this instance, and then all the sub-devices 154 */ 155 void 156 bztzscattach(struct device *parent, struct device *self, void *aux) 157 { 158 struct bztzsc_softc *bsc = (void *)self; 159 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 160 struct zbus_args *zap; 161 extern u_long scsi_nosync; 162 extern int shift_nosync; 163 extern int ncr53c9x_debug; 164 165 /* 166 * Set up the glue for MI code early; we use some of it here. 167 */ 168 sc->sc_glue = &bztzsc_glue; 169 170 /* 171 * Save the regs 172 */ 173 zap = aux; 174 bsc->sc_reg = &((volatile u_char *)zap->va)[0x1ff00]; 175 bsc->sc_dmabase = &bsc->sc_reg[0xf0]; 176 177 sc->sc_freq = 40; /* Clocked at 40Mhz */ 178 179 printf(": address %p", bsc->sc_reg); 180 181 sc->sc_id = 7; 182 183 /* 184 * It is necessary to try to load the 2nd config register here, 185 * to find out what rev the FAS chip is, else the ncr53c9x_reset 186 * will not set up the defaults correctly. 187 */ 188 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 189 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 190 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 191 sc->sc_rev = NCR_VARIANT_FAS216; 192 193 /* 194 * This is the value used to start sync negotiations 195 * Note that the NCR register "SYNCTP" is programmed 196 * in "clocks per byte", and has a minimum value of 4. 197 * The SCSI period used in negotiation is one-fourth 198 * of the time (in nanoseconds) needed to transfer one byte. 199 * Since the chip's clock is given in MHz, we have the following 200 * formula: 4 * period = (1000 / freq) * 4 201 */ 202 sc->sc_minsync = 1000 / sc->sc_freq; 203 204 /* 205 * get flags from -I argument and set cf_flags. 206 * NOTE: low 8 bits are to disable disconnect, and the next 207 * 8 bits are to disable sync. 208 */ 209 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 210 & 0xffff; 211 shift_nosync += 16; 212 213 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 214 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 215 shift_nosync += 16; 216 217 #if 1 218 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 219 sc->sc_minsync = 0; 220 #endif 221 222 /* Really no limit, but since we want to fit into the TCR... */ 223 sc->sc_maxxfer = 64 * 1024; 224 225 bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */ 226 227 /* 228 * Configure interrupts. 229 */ 230 bsc->sc_isr.isr_intr = ncr53c9x_intr; 231 bsc->sc_isr.isr_arg = sc; 232 bsc->sc_isr.isr_ipl = 2; 233 add_isr(&bsc->sc_isr); 234 235 /* 236 * Now try to attach all the sub-devices 237 */ 238 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 239 sc->sc_adapter.adapt_minphys = minphys; 240 ncr53c9x_attach(sc); 241 } 242 243 /* 244 * Glue functions. 245 */ 246 247 u_char 248 bztzsc_read_reg(struct ncr53c9x_softc *sc, int reg) 249 { 250 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 251 252 return bsc->sc_reg[reg * 4]; 253 } 254 255 void 256 bztzsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 257 { 258 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 259 u_char v = val; 260 261 bsc->sc_reg[reg * 4] = v; 262 #ifdef DEBUG 263 if (bztzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 264 reg == NCR_CMD/* && bsc->sc_active*/) { 265 bztzsc_trace[(bztzsc_trace_ptr - 1) & 127].yy = v; 266 /* printf(" cmd %x", v);*/ 267 } 268 #endif 269 } 270 271 int 272 bztzsc_dma_isintr(struct ncr53c9x_softc *sc) 273 { 274 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 275 276 if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 277 return 0; 278 279 if (sc->sc_state == NCR_CONNECTED) 280 bsc->sc_reg[0xe0] = 0; /* Turn LED on */ 281 else 282 bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */ 283 284 #ifdef DEBUG 285 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bztzsc_trace_enable) { 286 bztzsc_trace[bztzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4]; 287 bztzsc_trace[bztzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4]; 288 bztzsc_trace[bztzsc_trace_ptr].yy = bsc->sc_active; 289 bztzsc_trace_ptr = (bztzsc_trace_ptr + 1) & 127; 290 } 291 #endif 292 return 1; 293 } 294 295 void 296 bztzsc_dma_reset(struct ncr53c9x_softc *sc) 297 { 298 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 299 300 bsc->sc_active = 0; 301 } 302 303 int 304 bztzsc_dma_intr(struct ncr53c9x_softc *sc) 305 { 306 register struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 307 register int cnt; 308 309 NCR_DMA(("bztzsc_dma_intr: cnt %d int %x stat %x fifo %d ", 310 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 311 bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 312 if (bsc->sc_active == 0) { 313 printf("bztzsc_intr--inactive DMA\n"); 314 return -1; 315 } 316 317 /* update sc_dmaaddr and sc_pdmalen */ 318 cnt = bsc->sc_reg[NCR_TCL * 4]; 319 cnt += bsc->sc_reg[NCR_TCM * 4] << 8; 320 cnt += bsc->sc_reg[NCR_TCH * 4] << 16; 321 if (!bsc->sc_datain) { 322 cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 323 bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 324 } 325 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 326 NCR_DMA(("DMA xferred %d\n", cnt)); 327 if (bsc->sc_xfr_align) { 328 bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt); 329 bsc->sc_xfr_align = 0; 330 } 331 *bsc->sc_dmaaddr += cnt; 332 *bsc->sc_pdmalen -= cnt; 333 bsc->sc_active = 0; 334 return 0; 335 } 336 337 int 338 bztzsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 339 int datain, size_t *dmasize) 340 { 341 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 342 paddr_t pa; 343 u_char *ptr; 344 size_t xfer; 345 346 bsc->sc_dmaaddr = addr; 347 bsc->sc_pdmalen = len; 348 bsc->sc_datain = datain; 349 bsc->sc_dmasize = *dmasize; 350 /* 351 * DMA can be nasty for high-speed serial input, so limit the 352 * size of this DMA operation if the serial port is running at 353 * a high speed (higher than 19200 for now - should be adjusted 354 * based on cpu type and speed?). 355 * XXX - add serial speed check XXX 356 */ 357 if (ser_open_speed > 19200 && bztzsc_max_dma != 0 && 358 bsc->sc_dmasize > bztzsc_max_dma) 359 bsc->sc_dmasize = bztzsc_max_dma; 360 ptr = *addr; /* Kernel virtual address */ 361 pa = kvtop(ptr); /* Physical address of DMA */ 362 xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 363 bsc->sc_xfr_align = 0; 364 /* 365 * If output and unaligned, stuff odd byte into FIFO 366 */ 367 if (datain == 0 && (int)ptr & 1) { 368 NCR_DMA(("bztzsc_dma_setup: align byte written to fifo\n")); 369 pa++; 370 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 371 bsc->sc_reg[NCR_FIFO * 4] = *ptr++; 372 } 373 /* 374 * If unaligned address, read unaligned bytes into alignment buffer 375 */ 376 else if ((int)ptr & 1) { 377 pa = kvtop((caddr_t)&bsc->sc_alignbuf); 378 xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf)); 379 NCR_DMA(("bztzsc_dma_setup: align read by %d bytes\n", xfer)); 380 bsc->sc_xfr_align = 1; 381 } 382 ++bztzsc_cnt_dma; /* number of DMA operations */ 383 384 while (xfer < bsc->sc_dmasize) { 385 if ((pa + xfer) != kvtop(*addr + xfer)) 386 break; 387 if ((bsc->sc_dmasize - xfer) < NBPG) 388 xfer = bsc->sc_dmasize; 389 else 390 xfer += NBPG; 391 ++bztzsc_cnt_dma3; 392 } 393 if (xfer != *len) 394 ++bztzsc_cnt_dma2; 395 396 bsc->sc_dmasize = xfer; 397 *dmasize = bsc->sc_dmasize; 398 bsc->sc_pa = pa; 399 #if defined(M68040) || defined(M68060) 400 if (mmutype == MMU_68040) { 401 if (bsc->sc_xfr_align) { 402 dma_cachectl(bsc->sc_alignbuf, 403 sizeof(bsc->sc_alignbuf)); 404 } 405 else 406 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 407 } 408 #endif 409 410 pa >>= 1; 411 if (!bsc->sc_datain) 412 pa |= 0x80000000; 413 bsc->sc_dmabase[12] = (u_int8_t)(pa); 414 bsc->sc_dmabase[8] = (u_int8_t)(pa >> 8); 415 bsc->sc_dmabase[4] = (u_int8_t)(pa >> 16); 416 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 417 bsc->sc_active = 1; 418 return 0; 419 } 420 421 void 422 bztzsc_dma_go(struct ncr53c9x_softc *sc) 423 { 424 } 425 426 void 427 bztzsc_dma_stop(struct ncr53c9x_softc *sc) 428 { 429 } 430 431 int 432 bztzsc_dma_isactive(struct ncr53c9x_softc *sc) 433 { 434 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 435 436 return bsc->sc_active; 437 } 438 439 #ifdef DEBUG 440 void 441 bztzsc_dump(void) 442 { 443 int i; 444 445 i = bztzsc_trace_ptr; 446 printf("bztzsc_trace dump: ptr %x\n", bztzsc_trace_ptr); 447 do { 448 if (bztzsc_trace[i].hardbits == 0) { 449 i = (i + 1) & 127; 450 continue; 451 } 452 printf("%02x%02x%02x%02x(", bztzsc_trace[i].hardbits, 453 bztzsc_trace[i].status, bztzsc_trace[i].xx, bztzsc_trace[i].yy); 454 if (bztzsc_trace[i].status & NCRSTAT_INT) 455 printf("NCRINT/"); 456 if (bztzsc_trace[i].status & NCRSTAT_TC) 457 printf("NCRTC/"); 458 switch(bztzsc_trace[i].status & NCRSTAT_PHASE) { 459 case 0: 460 printf("dataout"); break; 461 case 1: 462 printf("datain"); break; 463 case 2: 464 printf("cmdout"); break; 465 case 3: 466 printf("status"); break; 467 case 6: 468 printf("msgout"); break; 469 case 7: 470 printf("msgin"); break; 471 default: 472 printf("phase%d?", bztzsc_trace[i].status & NCRSTAT_PHASE); 473 } 474 printf(") "); 475 i = (i + 1) & 127; 476 } while (i != bztzsc_trace_ptr); 477 printf("\n"); 478 } 479 #endif 480