1 /* $NetBSD: cbiisc.c,v 1.32 2010/12/20 00:25:25 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #ifdef __m68k__ 35 #include "opt_m68k_arch.h" 36 #endif 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: cbiisc.c,v 1.32 2010/12/20 00:25:25 matt Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/ioctl.h> 47 #include <sys/device.h> 48 #include <sys/buf.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 52 #include <dev/scsipi/scsi_all.h> 53 #include <dev/scsipi/scsipi_all.h> 54 #include <dev/scsipi/scsiconf.h> 55 #include <dev/scsipi/scsi_message.h> 56 57 #include <machine/cpu.h> 58 #include <machine/param.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <amiga/amiga/isr.h> 64 #include <amiga/dev/cbiiscvar.h> 65 #include <amiga/dev/zbusvar.h> 66 67 #ifdef __powerpc__ 68 #define badaddr(a) badaddr_read(a, 2, NULL) 69 #endif 70 71 int cbiiscmatch(device_t, cfdata_t, void *); 72 void cbiiscattach(device_t, device_t, void *); 73 74 /* Linkup to the rest of the kernel */ 75 CFATTACH_DECL_NEW(cbiisc, sizeof(struct cbiisc_softc), 76 cbiiscmatch, cbiiscattach, NULL, NULL); 77 78 /* 79 * Functions and the switch for the MI code. 80 */ 81 uint8_t cbiisc_read_reg(struct ncr53c9x_softc *, int); 82 void cbiisc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 83 int cbiisc_dma_isintr(struct ncr53c9x_softc *); 84 void cbiisc_dma_reset(struct ncr53c9x_softc *); 85 int cbiisc_dma_intr(struct ncr53c9x_softc *); 86 int cbiisc_dma_setup(struct ncr53c9x_softc *, uint8_t **, 87 size_t *, int, size_t *); 88 void cbiisc_dma_go(struct ncr53c9x_softc *); 89 void cbiisc_dma_stop(struct ncr53c9x_softc *); 90 int cbiisc_dma_isactive(struct ncr53c9x_softc *); 91 92 struct ncr53c9x_glue cbiisc_glue = { 93 cbiisc_read_reg, 94 cbiisc_write_reg, 95 cbiisc_dma_isintr, 96 cbiisc_dma_reset, 97 cbiisc_dma_intr, 98 cbiisc_dma_setup, 99 cbiisc_dma_go, 100 cbiisc_dma_stop, 101 cbiisc_dma_isactive, 102 NULL, 103 }; 104 105 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 106 u_long cbiisc_max_dma = 1024; 107 extern int ser_open_speed; 108 109 u_long cbiisc_cnt_pio = 0; /* number of PIO transfers */ 110 u_long cbiisc_cnt_dma = 0; /* number of DMA transfers */ 111 u_long cbiisc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 112 u_long cbiisc_cnt_dma3 = 0; /* number of pages combined */ 113 114 #ifdef DEBUG 115 struct { 116 uint8_t hardbits; 117 uint8_t status; 118 uint8_t xx; 119 uint8_t yy; 120 } cbiisc_trace[128]; 121 int cbiisc_trace_ptr = 0; 122 int cbiisc_trace_enable = 1; 123 void cbiisc_dump(void); 124 #endif 125 126 /* 127 * if we are a Phase5 CyberSCSI II 128 */ 129 int 130 cbiiscmatch(device_t parent, cfdata_t cf, void *aux) 131 { 132 struct zbus_args *zap; 133 volatile uint8_t *regs; 134 135 zap = aux; 136 if (zap->manid != 0x2140 || zap->prodid != 25) 137 return 0; 138 regs = &((volatile uint8_t *)zap->va)[0x1ff03]; 139 if (badaddr((void *)__UNVOLATILE(regs))) 140 return 0; 141 regs[NCR_CFG1 * 4] = 0; 142 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 143 delay(5); 144 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 145 return 0; 146 return 1; 147 } 148 149 /* 150 * Attach this instance, and then all the sub-devices 151 */ 152 void 153 cbiiscattach(device_t parent, device_t self, void *aux) 154 { 155 struct cbiisc_softc *csc = device_private(self); 156 struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x; 157 struct zbus_args *zap; 158 extern u_long scsi_nosync; 159 extern int shift_nosync; 160 extern int ncr53c9x_debug; 161 162 /* 163 * Set up the glue for MI code early; we use some of it here. 164 */ 165 sc->sc_dev = self; 166 sc->sc_glue = &cbiisc_glue; 167 168 /* 169 * Save the regs 170 */ 171 zap = aux; 172 csc->sc_reg = &((volatile uint8_t *)zap->va)[0x1ff03]; 173 csc->sc_dmabase = &csc->sc_reg[0x80]; 174 175 sc->sc_freq = 40; /* Clocked at 40 MHz */ 176 177 aprint_normal(": address %p", csc->sc_reg); 178 179 sc->sc_id = 7; 180 181 /* 182 * It is necessary to try to load the 2nd config register here, 183 * to find out what rev the FAS chip is, else the ncr53c9x_reset 184 * will not set up the defaults correctly. 185 */ 186 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 187 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 188 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 189 sc->sc_rev = NCR_VARIANT_FAS216; 190 191 /* 192 * This is the value used to start sync negotiations 193 * Note that the NCR register "SYNCTP" is programmed 194 * in "clocks per byte", and has a minimum value of 4. 195 * The SCSI period used in negotiation is one-fourth 196 * of the time (in nanoseconds) needed to transfer one byte. 197 * Since the chip's clock is given in MHz, we have the following 198 * formula: 4 * period = (1000 / freq) * 4 199 */ 200 sc->sc_minsync = 1000 / sc->sc_freq; 201 202 /* 203 * get flags from -I argument and set cf_flags. 204 * NOTE: low 8 bits are to disable disconnect, and the next 205 * 8 bits are to disable sync. 206 */ 207 device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync) 208 & 0xffff; 209 shift_nosync += 16; 210 211 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 212 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 213 shift_nosync += 16; 214 215 #if 1 216 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 217 sc->sc_minsync = 0; 218 #endif 219 220 /* Really no limit, but since we want to fit into the TCR... */ 221 sc->sc_maxxfer = 64 * 1024; 222 223 /* 224 * Configure interrupts. 225 */ 226 csc->sc_isr.isr_intr = ncr53c9x_intr; 227 csc->sc_isr.isr_arg = sc; 228 csc->sc_isr.isr_ipl = 2; 229 add_isr(&csc->sc_isr); 230 231 /* 232 * Now try to attach all the sub-devices 233 */ 234 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 235 sc->sc_adapter.adapt_minphys = minphys; 236 ncr53c9x_attach(sc); 237 } 238 239 /* 240 * Glue functions. 241 */ 242 243 uint8_t 244 cbiisc_read_reg(struct ncr53c9x_softc *sc, int reg) 245 { 246 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 247 248 return csc->sc_reg[reg * 4]; 249 } 250 251 void 252 cbiisc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 253 { 254 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 255 uint8_t v = val; 256 257 csc->sc_reg[reg * 4] = v; 258 #ifdef DEBUG 259 if (cbiisc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 260 reg == NCR_CMD/* && csc->sc_active*/) { 261 cbiisc_trace[(cbiisc_trace_ptr - 1) & 127].yy = v; 262 /* printf(" cmd %x", v);*/ 263 } 264 #endif 265 } 266 267 int 268 cbiisc_dma_isintr(struct ncr53c9x_softc *sc) 269 { 270 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 271 272 if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 273 return 0; 274 275 if (sc->sc_state == NCR_CONNECTED) 276 csc->sc_reg[0x40] = CBIISC_PB_LED; 277 else 278 csc->sc_reg[0x40] = 0; 279 280 #ifdef DEBUG 281 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbiisc_trace_enable) { 282 cbiisc_trace[cbiisc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4]; 283 cbiisc_trace[cbiisc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4]; 284 cbiisc_trace[cbiisc_trace_ptr].yy = csc->sc_active; 285 cbiisc_trace_ptr = (cbiisc_trace_ptr + 1) & 127; 286 } 287 #endif 288 return 1; 289 } 290 291 void 292 cbiisc_dma_reset(struct ncr53c9x_softc *sc) 293 { 294 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 295 296 csc->sc_active = 0; 297 } 298 299 int 300 cbiisc_dma_intr(struct ncr53c9x_softc *sc) 301 { 302 register struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 303 register int cnt; 304 305 NCR_DMA(("cbiisc_dma_intr: cnt %d int %x stat %x fifo %d ", 306 csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 307 csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 308 if (csc->sc_active == 0) { 309 printf("cbiisc_intr--inactive DMA\n"); 310 return -1; 311 } 312 313 /* update sc_dmaaddr and sc_pdmalen */ 314 cnt = csc->sc_reg[NCR_TCL * 4]; 315 cnt += csc->sc_reg[NCR_TCM * 4] << 8; 316 cnt += csc->sc_reg[NCR_TCH * 4] << 16; 317 if (!csc->sc_datain) { 318 cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 319 csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 320 } 321 cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */ 322 NCR_DMA(("DMA xferred %d\n", cnt)); 323 if (csc->sc_xfr_align) { 324 memcpy(*csc->sc_dmaaddr, csc->sc_alignbuf, cnt); 325 csc->sc_xfr_align = 0; 326 } 327 *csc->sc_dmaaddr += cnt; 328 *csc->sc_pdmalen -= cnt; 329 csc->sc_active = 0; 330 return 0; 331 } 332 333 int 334 cbiisc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 335 int datain, size_t *dmasize) 336 { 337 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 338 paddr_t pa; 339 uint8_t *ptr; 340 size_t xfer; 341 342 csc->sc_dmaaddr = addr; 343 csc->sc_pdmalen = len; 344 csc->sc_datain = datain; 345 csc->sc_dmasize = *dmasize; 346 /* 347 * DMA can be nasty for high-speed serial input, so limit the 348 * size of this DMA operation if the serial port is running at 349 * a high speed (higher than 19200 for now - should be adjusted 350 * based on CPU type and speed?). 351 * XXX - add serial speed check XXX 352 */ 353 if (ser_open_speed > 19200 && cbiisc_max_dma != 0 && 354 csc->sc_dmasize > cbiisc_max_dma) 355 csc->sc_dmasize = cbiisc_max_dma; 356 ptr = *addr; /* Kernel virtual address */ 357 pa = kvtop(ptr); /* Physical address of DMA */ 358 xfer = min(csc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 359 csc->sc_xfr_align = 0; 360 /* 361 * If output and unaligned, stuff odd byte into FIFO 362 */ 363 if (datain == 0 && (int)ptr & 1) { 364 NCR_DMA(("cbiisc_dma_setup: align byte written to fifo\n")); 365 pa++; 366 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 367 csc->sc_reg[NCR_FIFO * 4] = *ptr++; 368 } 369 /* 370 * If unaligned address, read unaligned bytes into alignment buffer 371 */ 372 else if ((int)ptr & 1) { 373 pa = kvtop((void *)&csc->sc_alignbuf); 374 xfer = csc->sc_dmasize = min(xfer, sizeof(csc->sc_alignbuf)); 375 NCR_DMA(("cbiisc_dma_setup: align read by %d bytes\n", xfer)); 376 csc->sc_xfr_align = 1; 377 } 378 ++cbiisc_cnt_dma; /* number of DMA operations */ 379 380 while (xfer < csc->sc_dmasize) { 381 if ((pa + xfer) != kvtop(*addr + xfer)) 382 break; 383 if ((csc->sc_dmasize - xfer) < PAGE_SIZE) 384 xfer = csc->sc_dmasize; 385 else 386 xfer += PAGE_SIZE; 387 ++cbiisc_cnt_dma3; 388 } 389 if (xfer != *len) 390 ++cbiisc_cnt_dma2; 391 392 csc->sc_dmasize = xfer; 393 *dmasize = csc->sc_dmasize; 394 csc->sc_pa = pa; 395 #if defined(M68040) || defined(M68060) 396 if (mmutype == MMU_68040) { 397 if (csc->sc_xfr_align) { 398 dma_cachectl(csc->sc_alignbuf, 399 sizeof(csc->sc_alignbuf)); 400 } 401 else 402 dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize); 403 } 404 #endif 405 406 if (csc->sc_datain) 407 pa &= ~1; 408 else 409 pa |= 1; 410 csc->sc_dmabase[0] = (uint8_t)(pa >> 24); 411 csc->sc_dmabase[4] = (uint8_t)(pa >> 16); 412 csc->sc_dmabase[8] = (uint8_t)(pa >> 8); 413 csc->sc_dmabase[12] = (uint8_t)(pa); 414 csc->sc_active = 1; 415 return 0; 416 } 417 418 void 419 cbiisc_dma_go(struct ncr53c9x_softc *sc) 420 { 421 } 422 423 void 424 cbiisc_dma_stop(struct ncr53c9x_softc *sc) 425 { 426 } 427 428 int 429 cbiisc_dma_isactive(struct ncr53c9x_softc *sc) 430 { 431 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 432 433 return csc->sc_active; 434 } 435 436 #ifdef DEBUG 437 void 438 cbiisc_dump(void) 439 { 440 int i; 441 442 i = cbiisc_trace_ptr; 443 printf("cbiisc_trace dump: ptr %x\n", cbiisc_trace_ptr); 444 do { 445 if (cbiisc_trace[i].hardbits == 0) { 446 i = (i + 1) & 127; 447 continue; 448 } 449 printf("%02x%02x%02x%02x(", cbiisc_trace[i].hardbits, 450 cbiisc_trace[i].status, cbiisc_trace[i].xx, cbiisc_trace[i].yy); 451 if (cbiisc_trace[i].status & NCRSTAT_INT) 452 printf("NCRINT/"); 453 if (cbiisc_trace[i].status & NCRSTAT_TC) 454 printf("NCRTC/"); 455 switch(cbiisc_trace[i].status & NCRSTAT_PHASE) { 456 case 0: 457 printf("dataout"); break; 458 case 1: 459 printf("datain"); break; 460 case 2: 461 printf("cmdout"); break; 462 case 3: 463 printf("status"); break; 464 case 6: 465 printf("msgout"); break; 466 case 7: 467 printf("msgin"); break; 468 default: 469 printf("phase%d?", cbiisc_trace[i].status & NCRSTAT_PHASE); 470 } 471 printf(") "); 472 i = (i + 1) & 127; 473 } while (i != cbiisc_trace_ptr); 474 printf("\n"); 475 } 476 #endif 477