xref: /netbsd/sys/arch/amiga/dev/cbiisc.c (revision bf9ec67e) 
1 /*	$NetBSD: cbiisc.c,v 1.13 2002/01/28 09:56:53 aymeric Exp $ */
2 
3 /*
4  * Copyright (c) 1997 Michael L. Hitch
5  * Copyright (c) 1982, 1990 The Regents of the University of California.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product contains software written by Michael L. Hitch for
19  *	the NetBSD project.
20  * 4. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  */
37 
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: cbiisc.c,v 1.13 2002/01/28 09:56:53 aymeric Exp $");
40 
41 #include <sys/types.h>
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/errno.h>
46 #include <sys/ioctl.h>
47 #include <sys/device.h>
48 #include <sys/buf.h>
49 #include <sys/proc.h>
50 #include <sys/user.h>
51 #include <sys/queue.h>
52 
53 #include <dev/scsipi/scsi_all.h>
54 #include <dev/scsipi/scsipi_all.h>
55 #include <dev/scsipi/scsiconf.h>
56 #include <dev/scsipi/scsi_message.h>
57 
58 #include <machine/cpu.h>
59 #include <machine/param.h>
60 
61 #include <dev/ic/ncr53c9xreg.h>
62 #include <dev/ic/ncr53c9xvar.h>
63 
64 #include <amiga/amiga/isr.h>
65 #include <amiga/dev/cbiiscvar.h>
66 #include <amiga/dev/zbusvar.h>
67 
68 void	cbiiscattach(struct device *, struct device *, void *);
69 int	cbiiscmatch(struct device *, struct cfdata *, void *);
70 
71 /* Linkup to the rest of the kernel */
72 struct cfattach cbiisc_ca = {
73 	sizeof(struct cbiisc_softc), cbiiscmatch, cbiiscattach
74 };
75 
76 /*
77  * Functions and the switch for the MI code.
78  */
79 u_char	cbiisc_read_reg(struct ncr53c9x_softc *, int);
80 void	cbiisc_write_reg(struct ncr53c9x_softc *, int, u_char);
81 int	cbiisc_dma_isintr(struct ncr53c9x_softc *);
82 void	cbiisc_dma_reset(struct ncr53c9x_softc *);
83 int	cbiisc_dma_intr(struct ncr53c9x_softc *);
84 int	cbiisc_dma_setup(struct ncr53c9x_softc *, caddr_t *,
85 	    size_t *, int, size_t *);
86 void	cbiisc_dma_go(struct ncr53c9x_softc *);
87 void	cbiisc_dma_stop(struct ncr53c9x_softc *);
88 int	cbiisc_dma_isactive(struct ncr53c9x_softc *);
89 
90 struct ncr53c9x_glue cbiisc_glue = {
91 	cbiisc_read_reg,
92 	cbiisc_write_reg,
93 	cbiisc_dma_isintr,
94 	cbiisc_dma_reset,
95 	cbiisc_dma_intr,
96 	cbiisc_dma_setup,
97 	cbiisc_dma_go,
98 	cbiisc_dma_stop,
99 	cbiisc_dma_isactive,
100 	0,
101 };
102 
103 /* Maximum DMA transfer length to reduce impact on high-speed serial input */
104 u_long cbiisc_max_dma = 1024;
105 extern int ser_open_speed;
106 
107 u_long cbiisc_cnt_pio = 0;	/* number of PIO transfers */
108 u_long cbiisc_cnt_dma = 0;	/* number of DMA transfers */
109 u_long cbiisc_cnt_dma2 = 0;	/* number of DMA transfers broken up */
110 u_long cbiisc_cnt_dma3 = 0;	/* number of pages combined */
111 
112 #ifdef DEBUG
113 struct {
114 	u_char hardbits;
115 	u_char status;
116 	u_char xx;
117 	u_char yy;
118 } cbiisc_trace[128];
119 int cbiisc_trace_ptr = 0;
120 int cbiisc_trace_enable = 1;
121 void cbiisc_dump(void);
122 #endif
123 
124 /*
125  * if we are a Phase5 CyberSCSI II
126  */
127 int
128 cbiiscmatch(struct device *parent, struct cfdata *cf, void *aux)
129 {
130 	struct zbus_args *zap;
131 	volatile u_char *regs;
132 
133 	zap = aux;
134 	if (zap->manid != 0x2140 || zap->prodid != 25)
135 		return(0);
136 	regs = &((volatile u_char *)zap->va)[0x1ff03];
137 	if (badaddr((caddr_t)regs))
138 		return(0);
139 	regs[NCR_CFG1 * 4] = 0;
140 	regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
141 	delay(5);
142 	if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
143 		return(0);
144 	return(1);
145 }
146 
147 /*
148  * Attach this instance, and then all the sub-devices
149  */
150 void
151 cbiiscattach(struct device *parent, struct device *self, void *aux)
152 {
153 	struct cbiisc_softc *csc = (void *)self;
154 	struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x;
155 	struct zbus_args  *zap;
156 	extern u_long scsi_nosync;
157 	extern int shift_nosync;
158 	extern int ncr53c9x_debug;
159 
160 	/*
161 	 * Set up the glue for MI code early; we use some of it here.
162 	 */
163 	sc->sc_glue = &cbiisc_glue;
164 
165 	/*
166 	 * Save the regs
167 	 */
168 	zap = aux;
169 	csc->sc_reg = &((volatile u_char *)zap->va)[0x1ff03];
170 	csc->sc_dmabase = &csc->sc_reg[0x80];
171 
172 	sc->sc_freq = 40;		/* Clocked at 40Mhz */
173 
174 	printf(": address %p", csc->sc_reg);
175 
176 	sc->sc_id = 7;
177 
178 	/*
179 	 * It is necessary to try to load the 2nd config register here,
180 	 * to find out what rev the FAS chip is, else the ncr53c9x_reset
181 	 * will not set up the defaults correctly.
182 	 */
183 	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
184 	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
185 	sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
186 	sc->sc_rev = NCR_VARIANT_FAS216;
187 
188 	/*
189 	 * This is the value used to start sync negotiations
190 	 * Note that the NCR register "SYNCTP" is programmed
191 	 * in "clocks per byte", and has a minimum value of 4.
192 	 * The SCSI period used in negotiation is one-fourth
193 	 * of the time (in nanoseconds) needed to transfer one byte.
194 	 * Since the chip's clock is given in MHz, we have the following
195 	 * formula: 4 * period = (1000 / freq) * 4
196 	 */
197 	sc->sc_minsync = 1000 / sc->sc_freq;
198 
199 	/*
200 	 * get flags from -I argument and set cf_flags.
201 	 * NOTE: low 8 bits are to disable disconnect, and the next
202 	 *       8 bits are to disable sync.
203 	 */
204 	sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
205 	    & 0xffff;
206 	shift_nosync += 16;
207 
208 	/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
209 	ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
210 	shift_nosync += 16;
211 
212 #if 1
213 	if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
214 		sc->sc_minsync = 0;
215 #endif
216 
217 	/* Really no limit, but since we want to fit into the TCR... */
218 	sc->sc_maxxfer = 64 * 1024;
219 
220 	/*
221 	 * Configure interrupts.
222 	 */
223 	csc->sc_isr.isr_intr = ncr53c9x_intr;
224 	csc->sc_isr.isr_arg  = sc;
225 	csc->sc_isr.isr_ipl  = 2;
226 	add_isr(&csc->sc_isr);
227 
228 	/*
229 	 * Now try to attach all the sub-devices
230 	 */
231 	sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
232 	sc->sc_adapter.adapt_minphys = minphys;
233 	ncr53c9x_attach(sc);
234 }
235 
236 /*
237  * Glue functions.
238  */
239 
240 u_char
241 cbiisc_read_reg(struct ncr53c9x_softc *sc, int reg)
242 {
243 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
244 
245 	return csc->sc_reg[reg * 4];
246 }
247 
248 void
249 cbiisc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val)
250 {
251 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
252 	u_char v = val;
253 
254 	csc->sc_reg[reg * 4] = v;
255 #ifdef DEBUG
256 if (cbiisc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ &&
257   reg == NCR_CMD/* && csc->sc_active*/) {
258   cbiisc_trace[(cbiisc_trace_ptr - 1) & 127].yy = v;
259 /*  printf(" cmd %x", v);*/
260 }
261 #endif
262 }
263 
264 int
265 cbiisc_dma_isintr(struct ncr53c9x_softc *sc)
266 {
267 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
268 
269 	if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
270 		return 0;
271 
272 	if (sc->sc_state == NCR_CONNECTED)
273 		csc->sc_reg[0x40] = CBIISC_PB_LED;
274 	else
275 		csc->sc_reg[0x40] = 0;
276 
277 #ifdef DEBUG
278 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbiisc_trace_enable) {
279   cbiisc_trace[cbiisc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4];
280   cbiisc_trace[cbiisc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4];
281   cbiisc_trace[cbiisc_trace_ptr].yy = csc->sc_active;
282   cbiisc_trace_ptr = (cbiisc_trace_ptr + 1) & 127;
283 }
284 #endif
285 	return 1;
286 }
287 
288 void
289 cbiisc_dma_reset(struct ncr53c9x_softc *sc)
290 {
291 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
292 
293 	csc->sc_active = 0;
294 }
295 
296 int
297 cbiisc_dma_intr(struct ncr53c9x_softc *sc)
298 {
299 	register struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
300 	register int	cnt;
301 
302 	NCR_DMA(("cbiisc_dma_intr: cnt %d int %x stat %x fifo %d ",
303 	    csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
304 	    csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
305 	if (csc->sc_active == 0) {
306 		printf("cbiisc_intr--inactive DMA\n");
307 		return -1;
308 	}
309 
310 	/* update sc_dmaaddr and sc_pdmalen */
311 	cnt = csc->sc_reg[NCR_TCL * 4];
312 	cnt += csc->sc_reg[NCR_TCM * 4] << 8;
313 	cnt += csc->sc_reg[NCR_TCH * 4] << 16;
314 	if (!csc->sc_datain) {
315 		cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
316 		csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
317 	}
318 	cnt = csc->sc_dmasize - cnt;	/* number of bytes transferred */
319 	NCR_DMA(("DMA xferred %d\n", cnt));
320 	if (csc->sc_xfr_align) {
321 		bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt);
322 		csc->sc_xfr_align = 0;
323 	}
324 	*csc->sc_dmaaddr += cnt;
325 	*csc->sc_pdmalen -= cnt;
326 	csc->sc_active = 0;
327 	return 0;
328 }
329 
330 int
331 cbiisc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len,
332                  int datain, size_t *dmasize)
333 {
334 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
335 	paddr_t pa;
336 	u_char *ptr;
337 	size_t xfer;
338 
339 	csc->sc_dmaaddr = addr;
340 	csc->sc_pdmalen = len;
341 	csc->sc_datain = datain;
342 	csc->sc_dmasize = *dmasize;
343 	/*
344 	 * DMA can be nasty for high-speed serial input, so limit the
345 	 * size of this DMA operation if the serial port is running at
346 	 * a high speed (higher than 19200 for now - should be adjusted
347 	 * based on cpu type and speed?).
348 	 * XXX - add serial speed check XXX
349 	 */
350 	if (ser_open_speed > 19200 && cbiisc_max_dma != 0 &&
351 	    csc->sc_dmasize > cbiisc_max_dma)
352 		csc->sc_dmasize = cbiisc_max_dma;
353 	ptr = *addr;			/* Kernel virtual address */
354 	pa = kvtop(ptr);		/* Physical address of DMA */
355 	xfer = min(csc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
356 	csc->sc_xfr_align = 0;
357 	/*
358 	 * If output and unaligned, stuff odd byte into FIFO
359 	 */
360 	if (datain == 0 && (int)ptr & 1) {
361 		NCR_DMA(("cbiisc_dma_setup: align byte written to fifo\n"));
362 		pa++;
363 		xfer--;			/* XXXX CHECK THIS !!!! XXXX */
364 		csc->sc_reg[NCR_FIFO * 4] = *ptr++;
365 	}
366 	/*
367 	 * If unaligned address, read unaligned bytes into alignment buffer
368 	 */
369 	else if ((int)ptr & 1) {
370 		pa = kvtop((caddr_t)&csc->sc_alignbuf);
371 		xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf));
372 		NCR_DMA(("cbiisc_dma_setup: align read by %d bytes\n", xfer));
373 		csc->sc_xfr_align = 1;
374 	}
375 ++cbiisc_cnt_dma;		/* number of DMA operations */
376 
377 	while (xfer < csc->sc_dmasize) {
378 		if ((pa + xfer) != kvtop(*addr + xfer))
379 			break;
380 		if ((csc->sc_dmasize - xfer) < NBPG)
381 			xfer = csc->sc_dmasize;
382 		else
383 			xfer += NBPG;
384 ++cbiisc_cnt_dma3;
385 	}
386 if (xfer != *len)
387   ++cbiisc_cnt_dma2;
388 
389 	csc->sc_dmasize = xfer;
390 	*dmasize = csc->sc_dmasize;
391 	csc->sc_pa = pa;
392 #if defined(M68040) || defined(M68060)
393 	if (mmutype == MMU_68040) {
394 		if (csc->sc_xfr_align) {
395 			dma_cachectl(csc->sc_alignbuf,
396 			    sizeof(csc->sc_alignbuf));
397 		}
398 		else
399 			dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize);
400 	}
401 #endif
402 
403 	if (csc->sc_datain)
404 		pa &= ~1;
405 	else
406 		pa |= 1;
407 	csc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
408 	csc->sc_dmabase[4] = (u_int8_t)(pa >> 16);
409 	csc->sc_dmabase[8] = (u_int8_t)(pa >> 8);
410 	csc->sc_dmabase[12] = (u_int8_t)(pa);
411 	csc->sc_active = 1;
412 	return 0;
413 }
414 
415 void
416 cbiisc_dma_go(struct ncr53c9x_softc *sc)
417 {
418 }
419 
420 void
421 cbiisc_dma_stop(struct ncr53c9x_softc *sc)
422 {
423 }
424 
425 int
426 cbiisc_dma_isactive(struct ncr53c9x_softc *sc)
427 {
428 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
429 
430 	return csc->sc_active;
431 }
432 
433 #ifdef DEBUG
434 void
435 cbiisc_dump(void)
436 {
437 	int i;
438 
439 	i = cbiisc_trace_ptr;
440 	printf("cbiisc_trace dump: ptr %x\n", cbiisc_trace_ptr);
441 	do {
442 		if (cbiisc_trace[i].hardbits == 0) {
443 			i = (i + 1) & 127;
444 			continue;
445 		}
446 		printf("%02x%02x%02x%02x(", cbiisc_trace[i].hardbits,
447 		    cbiisc_trace[i].status, cbiisc_trace[i].xx, cbiisc_trace[i].yy);
448 		if (cbiisc_trace[i].status & NCRSTAT_INT)
449 			printf("NCRINT/");
450 		if (cbiisc_trace[i].status & NCRSTAT_TC)
451 			printf("NCRTC/");
452 		switch(cbiisc_trace[i].status & NCRSTAT_PHASE) {
453 		case 0:
454 			printf("dataout"); break;
455 		case 1:
456 			printf("datain"); break;
457 		case 2:
458 			printf("cmdout"); break;
459 		case 3:
460 			printf("status"); break;
461 		case 6:
462 			printf("msgout"); break;
463 		case 7:
464 			printf("msgin"); break;
465 		default:
466 			printf("phase%d?", cbiisc_trace[i].status & NCRSTAT_PHASE);
467 		}
468 		printf(") ");
469 		i = (i + 1) & 127;
470 	} while (i != cbiisc_trace_ptr);
471 	printf("\n");
472 }
473 #endif
474