1 /* $NetBSD: cbsc.c,v 1.14 2002/01/28 09:56:53 aymeric Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product contains software written by Michael L. Hitch for 19 * the NetBSD project. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: cbsc.c,v 1.14 2002/01/28 09:56:53 aymeric Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/ioctl.h> 47 #include <sys/device.h> 48 #include <sys/buf.h> 49 #include <sys/proc.h> 50 #include <sys/user.h> 51 #include <sys/queue.h> 52 53 #include <dev/scsipi/scsi_all.h> 54 #include <dev/scsipi/scsipi_all.h> 55 #include <dev/scsipi/scsiconf.h> 56 #include <dev/scsipi/scsi_message.h> 57 58 #include <machine/cpu.h> 59 #include <machine/param.h> 60 61 #include <dev/ic/ncr53c9xreg.h> 62 #include <dev/ic/ncr53c9xvar.h> 63 64 #include <amiga/amiga/isr.h> 65 #include <amiga/dev/cbscvar.h> 66 #include <amiga/dev/zbusvar.h> 67 68 void cbscattach(struct device *, struct device *, void *); 69 int cbscmatch(struct device *, struct cfdata *, void *); 70 71 /* Linkup to the rest of the kernel */ 72 struct cfattach cbsc_ca = { 73 sizeof(struct cbsc_softc), cbscmatch, cbscattach 74 }; 75 76 /* 77 * Functions and the switch for the MI code. 78 */ 79 u_char cbsc_read_reg(struct ncr53c9x_softc *, int); 80 void cbsc_write_reg(struct ncr53c9x_softc *, int, u_char); 81 int cbsc_dma_isintr(struct ncr53c9x_softc *); 82 void cbsc_dma_reset(struct ncr53c9x_softc *); 83 int cbsc_dma_intr(struct ncr53c9x_softc *); 84 int cbsc_dma_setup(struct ncr53c9x_softc *, caddr_t *, 85 size_t *, int, size_t *); 86 void cbsc_dma_go(struct ncr53c9x_softc *); 87 void cbsc_dma_stop(struct ncr53c9x_softc *); 88 int cbsc_dma_isactive(struct ncr53c9x_softc *); 89 90 struct ncr53c9x_glue cbsc_glue = { 91 cbsc_read_reg, 92 cbsc_write_reg, 93 cbsc_dma_isintr, 94 cbsc_dma_reset, 95 cbsc_dma_intr, 96 cbsc_dma_setup, 97 cbsc_dma_go, 98 cbsc_dma_stop, 99 cbsc_dma_isactive, 100 0, 101 }; 102 103 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 104 u_long cbsc_max_dma = 1024; 105 extern int ser_open_speed; 106 107 u_long cbsc_cnt_pio = 0; /* number of PIO transfers */ 108 u_long cbsc_cnt_dma = 0; /* number of DMA transfers */ 109 u_long cbsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 110 u_long cbsc_cnt_dma3 = 0; /* number of pages combined */ 111 112 #ifdef DEBUG 113 struct { 114 u_char hardbits; 115 u_char status; 116 u_char xx; 117 u_char yy; 118 } cbsc_trace[128]; 119 int cbsc_trace_ptr = 0; 120 int cbsc_trace_enable = 1; 121 void cbsc_dump(void); 122 #endif 123 124 /* 125 * if we are a Phase5 CyberSCSI [mark I?] 126 */ 127 int 128 cbscmatch(struct device *parent, struct cfdata *cf, void *aux) 129 { 130 struct zbus_args *zap; 131 volatile u_char *regs; 132 133 zap = aux; 134 if (zap->manid != 0x2140) 135 return(0); /* It's not Phase5 */ 136 if (zap->prodid != 12 && zap->prodid != 11) 137 return(0); /* Not CyberStorm MKI SCSI */ 138 if (zap->prodid == 11 && iszthreepa(zap->pa)) 139 return(0); /* Fastlane Z3! */ 140 regs = &((volatile u_char *)zap->va)[0xf400]; 141 if (badaddr((caddr_t)regs)) 142 return(0); 143 regs[NCR_CFG1 * 4] = 0; 144 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 145 delay(5); 146 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 147 return(0); 148 return(1); 149 } 150 151 /* 152 * Attach this instance, and then all the sub-devices 153 */ 154 void 155 cbscattach(struct device *parent, struct device *self, void *aux) 156 { 157 struct cbsc_softc *csc = (void *)self; 158 struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x; 159 struct zbus_args *zap; 160 extern u_long scsi_nosync; 161 extern int shift_nosync; 162 extern int ncr53c9x_debug; 163 164 /* 165 * Set up the glue for MI code early; we use some of it here. 166 */ 167 sc->sc_glue = &cbsc_glue; 168 169 /* 170 * Save the regs 171 */ 172 zap = aux; 173 csc->sc_reg = &((volatile u_char *)zap->va)[0xf400]; 174 csc->sc_dmabase = &csc->sc_reg[0x400]; 175 176 sc->sc_freq = 40; /* Clocked at 40Mhz */ 177 178 printf(": address %p", csc->sc_reg); 179 180 sc->sc_id = 7; 181 182 /* 183 * It is necessary to try to load the 2nd config register here, 184 * to find out what rev the FAS chip is, else the ncr53c9x_reset 185 * will not set up the defaults correctly. 186 */ 187 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 188 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 189 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 190 sc->sc_rev = NCR_VARIANT_FAS216; 191 192 /* 193 * This is the value used to start sync negotiations 194 * Note that the NCR register "SYNCTP" is programmed 195 * in "clocks per byte", and has a minimum value of 4. 196 * The SCSI period used in negotiation is one-fourth 197 * of the time (in nanoseconds) needed to transfer one byte. 198 * Since the chip's clock is given in MHz, we have the following 199 * formula: 4 * period = (1000 / freq) * 4 200 */ 201 sc->sc_minsync = 1000 / sc->sc_freq; 202 203 /* 204 * get flags from -I argument and set cf_flags. 205 * NOTE: low 8 bits are to disable disconnect, and the next 206 * 8 bits are to disable sync. 207 */ 208 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 209 & 0xffff; 210 shift_nosync += 16; 211 212 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 213 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 214 shift_nosync += 16; 215 216 #if 1 217 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 218 sc->sc_minsync = 0; 219 #endif 220 221 /* Really no limit, but since we want to fit into the TCR... */ 222 sc->sc_maxxfer = 64 * 1024; 223 224 /* 225 * Configure interrupts. 226 */ 227 csc->sc_isr.isr_intr = ncr53c9x_intr; 228 csc->sc_isr.isr_arg = sc; 229 csc->sc_isr.isr_ipl = 2; 230 add_isr(&csc->sc_isr); 231 232 /* 233 * Now try to attach all the sub-devices 234 */ 235 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 236 sc->sc_adapter.adapt_minphys = minphys; 237 ncr53c9x_attach(sc); 238 } 239 240 /* 241 * Glue functions. 242 */ 243 244 u_char 245 cbsc_read_reg(struct ncr53c9x_softc *sc, int reg) 246 { 247 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 248 249 return csc->sc_reg[reg * 4]; 250 } 251 252 void 253 cbsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 254 { 255 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 256 u_char v = val; 257 258 csc->sc_reg[reg * 4] = v; 259 #ifdef DEBUG 260 if (cbsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 261 reg == NCR_CMD/* && csc->sc_active*/) { 262 cbsc_trace[(cbsc_trace_ptr - 1) & 127].yy = v; 263 /* printf(" cmd %x", v);*/ 264 } 265 #endif 266 } 267 268 int 269 cbsc_dma_isintr(struct ncr53c9x_softc *sc) 270 { 271 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 272 273 if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 274 return 0; 275 276 if (sc->sc_state == NCR_CONNECTED) 277 csc->sc_portbits |= CBSC_PB_LED; 278 else 279 csc->sc_portbits &= ~CBSC_PB_LED; 280 csc->sc_reg[0x802] = csc->sc_portbits; 281 282 if ((csc->sc_reg[0x802] & CBSC_HB_CREQ) == 0) 283 return 0; 284 #ifdef DEBUG 285 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbsc_trace_enable) { 286 cbsc_trace[cbsc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4]; 287 cbsc_trace[cbsc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4]; 288 cbsc_trace[cbsc_trace_ptr].yy = csc->sc_active; 289 cbsc_trace_ptr = (cbsc_trace_ptr + 1) & 127; 290 } 291 #endif 292 return 1; 293 } 294 295 void 296 cbsc_dma_reset(struct ncr53c9x_softc *sc) 297 { 298 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 299 300 csc->sc_active = 0; 301 } 302 303 int 304 cbsc_dma_intr(struct ncr53c9x_softc *sc) 305 { 306 register struct cbsc_softc *csc = (struct cbsc_softc *)sc; 307 register int cnt; 308 309 NCR_DMA(("cbsc_dma_intr: cnt %d int %x stat %x fifo %d ", 310 csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 311 csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 312 if (csc->sc_active == 0) { 313 printf("cbsc_intr--inactive DMA\n"); 314 return -1; 315 } 316 317 /* update sc_dmaaddr and sc_pdmalen */ 318 cnt = csc->sc_reg[NCR_TCL * 4]; 319 cnt += csc->sc_reg[NCR_TCM * 4] << 8; 320 cnt += csc->sc_reg[NCR_TCH * 4] << 16; 321 if (!csc->sc_datain) { 322 cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 323 csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 324 } 325 cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */ 326 NCR_DMA(("DMA xferred %d\n", cnt)); 327 if (csc->sc_xfr_align) { 328 bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt); 329 csc->sc_xfr_align = 0; 330 } 331 *csc->sc_dmaaddr += cnt; 332 *csc->sc_pdmalen -= cnt; 333 csc->sc_active = 0; 334 return 0; 335 } 336 337 int 338 cbsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 339 int datain, size_t *dmasize) 340 { 341 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 342 paddr_t pa; 343 u_char *ptr; 344 size_t xfer; 345 346 csc->sc_dmaaddr = addr; 347 csc->sc_pdmalen = len; 348 csc->sc_datain = datain; 349 csc->sc_dmasize = *dmasize; 350 /* 351 * DMA can be nasty for high-speed serial input, so limit the 352 * size of this DMA operation if the serial port is running at 353 * a high speed (higher than 19200 for now - should be adjusted 354 * based on cpu type and speed?). 355 * XXX - add serial speed check XXX 356 */ 357 if (ser_open_speed > 19200 && cbsc_max_dma != 0 && 358 csc->sc_dmasize > cbsc_max_dma) 359 csc->sc_dmasize = cbsc_max_dma; 360 ptr = *addr; /* Kernel virtual address */ 361 pa = kvtop(ptr); /* Physical address of DMA */ 362 xfer = min(csc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 363 csc->sc_xfr_align = 0; 364 /* 365 * If output and unaligned, stuff odd byte into FIFO 366 */ 367 if (datain == 0 && (int)ptr & 1) { 368 NCR_DMA(("cbsc_dma_setup: align byte written to fifo\n")); 369 pa++; 370 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 371 csc->sc_reg[NCR_FIFO * 4] = *ptr++; 372 } 373 /* 374 * If unaligned address, read unaligned bytes into alignment buffer 375 */ 376 else if ((int)ptr & 1) { 377 pa = kvtop((caddr_t)&csc->sc_alignbuf); 378 xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf)); 379 NCR_DMA(("cbsc_dma_setup: align read by %d bytes\n", xfer)); 380 csc->sc_xfr_align = 1; 381 } 382 ++cbsc_cnt_dma; /* number of DMA operations */ 383 384 while (xfer < csc->sc_dmasize) { 385 if ((pa + xfer) != kvtop(*addr + xfer)) 386 break; 387 if ((csc->sc_dmasize - xfer) < NBPG) 388 xfer = csc->sc_dmasize; 389 else 390 xfer += NBPG; 391 ++cbsc_cnt_dma3; 392 } 393 if (xfer != *len) 394 ++cbsc_cnt_dma2; 395 396 csc->sc_dmasize = xfer; 397 *dmasize = csc->sc_dmasize; 398 csc->sc_pa = pa; 399 #if defined(M68040) || defined(M68060) 400 if (mmutype == MMU_68040) { 401 if (csc->sc_xfr_align) { 402 dma_cachectl(csc->sc_alignbuf, 403 sizeof(csc->sc_alignbuf)); 404 } 405 else 406 dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize); 407 } 408 #endif 409 410 if (csc->sc_datain) 411 pa &= ~1; 412 else 413 pa |= 1; 414 csc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 415 csc->sc_dmabase[2] = (u_int8_t)(pa >> 16); 416 csc->sc_dmabase[4] = (u_int8_t)(pa >> 8); 417 csc->sc_dmabase[6] = (u_int8_t)(pa); 418 if (csc->sc_datain) 419 csc->sc_portbits &= ~CBSC_PB_WRITE; 420 else 421 csc->sc_portbits |= CBSC_PB_WRITE; 422 csc->sc_reg[0x802] = csc->sc_portbits; 423 csc->sc_active = 1; 424 return 0; 425 } 426 427 void 428 cbsc_dma_go(struct ncr53c9x_softc *sc) 429 { 430 } 431 432 void 433 cbsc_dma_stop(struct ncr53c9x_softc *sc) 434 { 435 } 436 437 int 438 cbsc_dma_isactive(struct ncr53c9x_softc *sc) 439 { 440 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 441 442 return csc->sc_active; 443 } 444 445 #ifdef DEBUG 446 void 447 cbsc_dump(void) 448 { 449 int i; 450 451 i = cbsc_trace_ptr; 452 printf("cbsc_trace dump: ptr %x\n", cbsc_trace_ptr); 453 do { 454 if (cbsc_trace[i].hardbits == 0) { 455 i = (i + 1) & 127; 456 continue; 457 } 458 printf("%02x%02x%02x%02x(", cbsc_trace[i].hardbits, 459 cbsc_trace[i].status, cbsc_trace[i].xx, cbsc_trace[i].yy); 460 if (cbsc_trace[i].status & NCRSTAT_INT) 461 printf("NCRINT/"); 462 if (cbsc_trace[i].status & NCRSTAT_TC) 463 printf("NCRTC/"); 464 switch(cbsc_trace[i].status & NCRSTAT_PHASE) { 465 case 0: 466 printf("dataout"); break; 467 case 1: 468 printf("datain"); break; 469 case 2: 470 printf("cmdout"); break; 471 case 3: 472 printf("status"); break; 473 case 6: 474 printf("msgout"); break; 475 case 7: 476 printf("msgin"); break; 477 default: 478 printf("phase%d?", cbsc_trace[i].status & NCRSTAT_PHASE); 479 } 480 printf(") "); 481 i = (i + 1) & 127; 482 } while (i != cbsc_trace_ptr); 483 printf("\n"); 484 } 485 #endif 486