1 /* $NetBSD: flsc.c,v 1.45 2010/12/20 00:25:25 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Initial amiga Fastlane driver by Daniel Widenfalk. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 42 */ 43 44 #include "opt_ddb.h" 45 #ifdef __m68k__ 46 #include "opt_m68k_arch.h" 47 #endif 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: flsc.c,v 1.45 2010/12/20 00:25:25 matt Exp $"); 51 52 #include <sys/types.h> 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/errno.h> 57 #include <sys/ioctl.h> 58 #include <sys/device.h> 59 #include <sys/buf.h> 60 #include <sys/proc.h> 61 #include <sys/queue.h> 62 63 #include <dev/scsipi/scsi_all.h> 64 #include <dev/scsipi/scsipi_all.h> 65 #include <dev/scsipi/scsiconf.h> 66 #include <dev/scsipi/scsi_message.h> 67 68 #include <machine/cpu.h> 69 #include <machine/param.h> 70 71 #include <dev/ic/ncr53c9xreg.h> 72 #include <dev/ic/ncr53c9xvar.h> 73 74 #include <amiga/amiga/isr.h> 75 #include <amiga/dev/flscvar.h> 76 #include <amiga/dev/zbusvar.h> 77 78 int flscmatch(device_t, cfdata_t, void *); 79 void flscattach(device_t, device_t, void *); 80 81 /* Linkup to the rest of the kernel */ 82 CFATTACH_DECL_NEW(flsc, sizeof(struct flsc_softc), 83 flscmatch, flscattach, NULL, NULL); 84 85 /* 86 * Functions and the switch for the MI code. 87 */ 88 uint8_t flsc_read_reg(struct ncr53c9x_softc *, int); 89 void flsc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 90 int flsc_dma_isintr(struct ncr53c9x_softc *); 91 void flsc_dma_reset(struct ncr53c9x_softc *); 92 int flsc_dma_intr(struct ncr53c9x_softc *); 93 int flsc_dma_setup(struct ncr53c9x_softc *, uint8_t **, 94 size_t *, int, size_t *); 95 void flsc_dma_go(struct ncr53c9x_softc *); 96 void flsc_dma_stop(struct ncr53c9x_softc *); 97 int flsc_dma_isactive(struct ncr53c9x_softc *); 98 void flsc_clear_latched_intr(struct ncr53c9x_softc *); 99 100 struct ncr53c9x_glue flsc_glue = { 101 flsc_read_reg, 102 flsc_write_reg, 103 flsc_dma_isintr, 104 flsc_dma_reset, 105 flsc_dma_intr, 106 flsc_dma_setup, 107 flsc_dma_go, 108 flsc_dma_stop, 109 flsc_dma_isactive, 110 flsc_clear_latched_intr, 111 }; 112 113 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 114 u_long flsc_max_dma = 1024; 115 extern int ser_open_speed; 116 117 extern int ncr53c9x_debug; 118 extern u_long scsi_nosync; 119 extern int shift_nosync; 120 121 /* 122 * if we are an Advanced Systems & Software FastlaneZ3 123 */ 124 int 125 flscmatch(device_t parent, cfdata_t cf, void *aux) 126 { 127 struct zbus_args *zap; 128 129 if (!is_a4000() && !is_a3000()) 130 return 0; 131 132 zap = aux; 133 if (zap->manid == 0x2140 && zap->prodid == 11 134 && iszthreepa(zap->pa)) 135 return 1; 136 137 return 0; 138 } 139 140 /* 141 * Attach this instance, and then all the sub-devices 142 */ 143 void 144 flscattach(device_t parent, device_t self, void *aux) 145 { 146 struct flsc_softc *fsc = device_private(self); 147 struct ncr53c9x_softc *sc = &fsc->sc_ncr53c9x; 148 struct zbus_args *zap; 149 150 /* 151 * Set up the glue for MI code early; we use some of it here. 152 */ 153 sc->sc_dev = self; 154 sc->sc_glue = &flsc_glue; 155 156 /* 157 * Save the regs 158 */ 159 zap = aux; 160 fsc->sc_dmabase = (volatile uint8_t *)zap->va; 161 fsc->sc_reg = &((volatile uint8_t *)zap->va)[0x1000001]; 162 163 sc->sc_freq = 40; /* Clocked at 40 MHz */ 164 165 aprint_normal(": address %p", fsc->sc_reg); 166 167 sc->sc_id = 7; 168 169 /* 170 * It is necessary to try to load the 2nd config register here, 171 * to find out what rev the flsc chip is, else the flsc_reset 172 * will not set up the defaults correctly. 173 */ 174 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 175 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 176 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 177 sc->sc_rev = NCR_VARIANT_FAS216; 178 179 /* 180 * This is the value used to start sync negotiations 181 * Note that the NCR register "SYNCTP" is programmed 182 * in "clocks per byte", and has a minimum value of 4. 183 * The SCSI period used in negotiation is one-fourth 184 * of the time (in nanoseconds) needed to transfer one byte. 185 * Since the chip's clock is given in MHz, we have the following 186 * formula: 4 * period = (1000 / freq) * 4 187 */ 188 sc->sc_minsync = 1000 / sc->sc_freq; 189 190 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 191 sc->sc_minsync = 0; 192 193 /* Really no limit, but since we want to fit into the TCR... */ 194 sc->sc_maxxfer = 64 * 1024; 195 196 fsc->sc_portbits = 0xa0 | FLSC_PB_EDI | FLSC_PB_ESI; 197 fsc->sc_hardbits = fsc->sc_reg[0x40]; 198 199 fsc->sc_alignbuf = (uint8_t *)((u_long)fsc->sc_unalignbuf & -4); 200 201 device_cfdata(self)->cf_flags |= 202 (scsi_nosync >> shift_nosync) & 0xffff; 203 shift_nosync += 16; 204 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 205 shift_nosync += 16; 206 207 /* 208 * Configure interrupts. 209 */ 210 fsc->sc_isr.isr_intr = ncr53c9x_intr; 211 fsc->sc_isr.isr_arg = sc; 212 fsc->sc_isr.isr_ipl = 2; 213 add_isr(&fsc->sc_isr); 214 215 fsc->sc_reg[0x40] = fsc->sc_portbits; 216 217 /* 218 * Now try to attach all the sub-devices 219 */ 220 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 221 sc->sc_adapter.adapt_minphys = minphys; 222 ncr53c9x_attach(sc); 223 } 224 225 /* 226 * Glue functions. 227 */ 228 229 uint8_t 230 flsc_read_reg(struct ncr53c9x_softc *sc, int reg) 231 { 232 struct flsc_softc *fsc = (struct flsc_softc *)sc; 233 234 return fsc->sc_reg[reg * 4]; 235 } 236 237 void 238 flsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 239 { 240 struct flsc_softc *fsc = (struct flsc_softc *)sc; 241 struct ncr53c9x_tinfo *ti; 242 uint8_t v = val; 243 244 if (fsc->sc_piomode && reg == NCR_CMD && 245 v == (NCRCMD_TRANS | NCRCMD_DMA)) { 246 v = NCRCMD_TRANS; 247 } 248 /* 249 * Can't do synchronous transfers in XS_CTL_POLL mode: 250 * If starting XS_CTL_POLL command, clear defer sync negotiation 251 * by clearing the T_NEGOTIATE flag. If starting XS_CTL_POLL and 252 * the device is currently running synchronous, force another 253 * T_NEGOTIATE with 0 offset. 254 */ 255 if (reg == NCR_SELID) { 256 ti = &sc->sc_tinfo[ 257 sc->sc_nexus->xs->xs_periph->periph_target]; 258 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 259 if (ti->flags & T_SYNCMODE) { 260 ti->flags ^= T_SYNCMODE | T_NEGOTIATE; 261 } else if (ti->flags & T_NEGOTIATE) { 262 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 263 /* save T_NEGOTIATE in private flags? */ 264 } 265 } else { 266 /* 267 * If we haven't attempted sync negotiation yet, 268 * do it now. 269 */ 270 if ((ti->flags & (T_SYNCMODE | T_SYNCHOFF)) == 271 T_SYNCHOFF && 272 sc->sc_minsync != 0) /* XXX */ 273 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 274 } 275 } 276 if (reg == NCR_CMD && v == NCRCMD_SETATN && 277 sc->sc_flags & NCR_SYNCHNEGO && 278 sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 279 ti = &sc->sc_tinfo[ 280 sc->sc_nexus->xs->xs_periph->periph_target]; 281 ti->offset = 0; 282 } 283 fsc->sc_reg[reg * 4] = v; 284 } 285 286 int 287 flsc_dma_isintr(struct ncr53c9x_softc *sc) 288 { 289 struct flsc_softc *fsc = (struct flsc_softc *)sc; 290 unsigned int hardbits; 291 292 hardbits = fsc->sc_reg[0x40]; 293 if ((hardbits & FLSC_HB_IACT) != 0) 294 return (fsc->sc_csr = 0); 295 296 if (sc->sc_state == NCR_CONNECTED || sc->sc_state == NCR_SELECTING) 297 fsc->sc_portbits |= FLSC_PB_LED; 298 else 299 fsc->sc_portbits &= ~FLSC_PB_LED; 300 301 if ((hardbits & FLSC_HB_CREQ) != 0 && (hardbits & FLSC_HB_MINT) == 0 && 302 (fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) != 0) { 303 return 1; 304 } 305 /* Do I still need this? */ 306 if (fsc->sc_piomode && (fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) != 0 && 307 (hardbits & FLSC_HB_MINT) == 0) 308 return 1; 309 310 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 311 fsc->sc_reg[0x40] = fsc->sc_portbits; 312 return 0; 313 } 314 315 void 316 flsc_clear_latched_intr(struct ncr53c9x_softc *sc) 317 { 318 struct flsc_softc *fsc = (struct flsc_softc *)sc; 319 320 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 321 fsc->sc_reg[0x40] = fsc->sc_portbits; 322 } 323 324 void 325 flsc_dma_reset(struct ncr53c9x_softc *sc) 326 { 327 struct flsc_softc *fsc = (struct flsc_softc *)sc; 328 struct ncr53c9x_tinfo *ti; 329 330 if (sc->sc_nexus) 331 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 332 else 333 ti = &sc->sc_tinfo[1]; /* XXX */ 334 if (fsc->sc_active) { 335 printf("dmaaddr %p dmasize %d stat %x flags %x off %d ", 336 *fsc->sc_dmaaddr, fsc->sc_dmasize, 337 fsc->sc_reg[NCR_STAT * 4], ti->flags, ti->offset); 338 printf("per %d ff %x intr %x\n", 339 ti->period, fsc->sc_reg[NCR_FFLAG * 4], 340 fsc->sc_reg[NCR_INTR * 4]); 341 #ifdef DDB 342 Debugger(); 343 #endif 344 } 345 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 346 fsc->sc_reg[0x40] = fsc->sc_portbits; 347 fsc->sc_reg[0x80] = 0; 348 *((volatile uint32_t *)fsc->sc_dmabase) = 0; 349 fsc->sc_active = 0; 350 fsc->sc_piomode = 0; 351 } 352 353 int 354 flsc_dma_intr(struct ncr53c9x_softc *sc) 355 { 356 register struct flsc_softc *fsc = (struct flsc_softc *)sc; 357 uint8_t *p; 358 volatile uint8_t *cmdreg, *intrreg, *statreg, *fiforeg; 359 u_int flscphase, flscstat, flscintr; 360 int cnt; 361 362 NCR_DMA(("flsc_dma_intr: pio %d cnt %d int %x stat %x fifo %d ", 363 fsc->sc_piomode, fsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 364 fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 365 if ((fsc->sc_reg[0x40] & FLSC_HB_CREQ) == 0) 366 printf("flsc_dma_intr: csr %x stat %x intr %x\n", fsc->sc_csr, 367 sc->sc_espstat, sc->sc_espintr); 368 if (fsc->sc_active == 0) { 369 printf("flsc_intr--inactive DMA\n"); 370 return -1; 371 } 372 373 /* if DMA transfer, update sc_dmaaddr and sc_pdmalen, else PIO xfer */ 374 if (fsc->sc_piomode == 0) { 375 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 376 fsc->sc_reg[0x40] = fsc->sc_portbits; 377 fsc->sc_reg[0x80] = 0; 378 *((volatile uint32_t *)fsc->sc_dmabase) = 0; 379 cnt = fsc->sc_reg[NCR_TCL * 4]; 380 cnt += fsc->sc_reg[NCR_TCM * 4] << 8; 381 cnt += fsc->sc_reg[NCR_TCH * 4] << 16; 382 if (!fsc->sc_datain) { 383 cnt += fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 384 fsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 385 } 386 cnt = fsc->sc_dmasize - cnt; /* number of bytes transferred */ 387 NCR_DMA(("DMA xferred %d\n", cnt)); 388 if (fsc->sc_xfr_align) { 389 int i; 390 for (i = 0; i < cnt; ++i) 391 (*fsc->sc_dmaaddr)[i] = fsc->sc_alignbuf[i]; 392 fsc->sc_xfr_align = 0; 393 } 394 *fsc->sc_dmaaddr += cnt; 395 *fsc->sc_pdmalen -= cnt; 396 fsc->sc_active = 0; 397 return 0; 398 } 399 400 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 401 fsc->sc_active = 0; 402 fsc->sc_piomode = 0; 403 NCR_DMA(("no NCRINTR_BS\n")); 404 return 0; 405 } 406 407 cnt = fsc->sc_dmasize; 408 #if 0 409 if (cnt == 0) { 410 printf("data interrupt, but no count left."); 411 } 412 #endif 413 414 p = *fsc->sc_dmaaddr; 415 flscphase = sc->sc_phase; 416 flscstat = (u_int)sc->sc_espstat; 417 flscintr = (u_int)sc->sc_espintr; 418 cmdreg = fsc->sc_reg + NCR_CMD * 4; 419 fiforeg = fsc->sc_reg + NCR_FIFO * 4; 420 statreg = fsc->sc_reg + NCR_STAT * 4; 421 intrreg = fsc->sc_reg + NCR_INTR * 4; 422 NCR_DMA(("PIO %d datain %d phase %d stat %x intr %x\n", 423 cnt, fsc->sc_datain, flscphase, flscstat, flscintr)); 424 do { 425 if (fsc->sc_datain) { 426 *p++ = *fiforeg; 427 cnt--; 428 if (flscphase == DATA_IN_PHASE) { 429 *cmdreg = NCRCMD_TRANS; 430 } else { 431 fsc->sc_active = 0; 432 } 433 } else { 434 NCR_DMA(("flsc_dma_intr: PIO out- phase %d cnt %d active %d\n", flscphase, cnt, 435 fsc->sc_active)); 436 if ( (flscphase == DATA_OUT_PHASE) 437 || (flscphase == MESSAGE_OUT_PHASE)) { 438 int n; 439 n = 16 - (fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF); 440 if (n > cnt) 441 n = cnt; 442 cnt -= n; 443 while (n-- > 0) 444 *fiforeg = *p++; 445 *cmdreg = NCRCMD_TRANS; 446 } else { 447 fsc->sc_active = 0; 448 } 449 } 450 451 if (fsc->sc_active && cnt) { 452 while ((*statreg & 0x80) == 0) 453 ; 454 flscstat = *statreg; 455 flscintr = *intrreg; 456 flscphase = (flscintr & NCRINTR_DIS) 457 ? /* Disconnected */ BUSFREE_PHASE 458 : flscstat & PHASE_MASK; 459 } 460 } while (cnt && fsc->sc_active && (flscintr & NCRINTR_BS) != 0); 461 #if 1 462 if (fsc->sc_dmasize < 8 && cnt) 463 printf("flsc_dma_intr: short transfer: dmasize %d cnt %d\n", 464 fsc->sc_dmasize, cnt); 465 #endif 466 NCR_DMA(("flsc_dma_intr: PIO transfer [%d], %d->%d phase %d stat %x intr %x\n", 467 *fsc->sc_pdmalen, fsc->sc_dmasize, cnt, flscphase, flscstat, flscintr)); 468 sc->sc_phase = flscphase; 469 sc->sc_espstat = (uint8_t)flscstat; 470 sc->sc_espintr = (uint8_t)flscintr; 471 *fsc->sc_dmaaddr = p; 472 *fsc->sc_pdmalen -= fsc->sc_dmasize - cnt; 473 fsc->sc_dmasize = cnt; 474 475 if (*fsc->sc_pdmalen == 0) { 476 sc->sc_espstat |= NCRSTAT_TC; 477 fsc->sc_piomode = 0; 478 } 479 return 0; 480 } 481 482 int 483 flsc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 484 int datain, size_t *dmasize) 485 { 486 struct flsc_softc *fsc = (struct flsc_softc *)sc; 487 paddr_t pa; 488 uint8_t *ptr; 489 size_t xfer; 490 491 fsc->sc_dmaaddr = addr; 492 fsc->sc_pdmalen = len; 493 fsc->sc_datain = datain; 494 fsc->sc_dmasize = *dmasize; 495 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 496 /* polling mode, use PIO */ 497 *dmasize = fsc->sc_dmasize; 498 NCR_DMA(("pfsc_dma_setup: PIO %p/%d [%d]\n", *addr, 499 fsc->sc_dmasize, *len)); 500 fsc->sc_piomode = 1; 501 if (datain == 0) { 502 int n; 503 n = fsc->sc_dmasize; 504 if (n > 16) 505 n = 16; 506 while (n-- > 0) { 507 fsc->sc_reg[NCR_FIFO * 4] = **fsc->sc_dmaaddr; 508 (*fsc->sc_pdmalen)--; 509 (*fsc->sc_dmaaddr)++; 510 --fsc->sc_dmasize; 511 } 512 } 513 return 0; 514 } 515 /* 516 * DMA can be nasty for high-speed serial input, so limit the 517 * size of this DMA operation if the serial port is running at 518 * a high speed (higher than 19200 for now - should be adjusted 519 * based on CPU type and speed?). 520 * XXX - add serial speed check XXX 521 */ 522 if (ser_open_speed > 19200 && flsc_max_dma != 0 && 523 fsc->sc_dmasize > flsc_max_dma) 524 fsc->sc_dmasize = flsc_max_dma; 525 ptr = *addr; /* Kernel virtual address */ 526 pa = kvtop(ptr); /* Physical address of DMA */ 527 xfer = min(fsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 528 fsc->sc_xfr_align = 0; 529 fsc->sc_piomode = 0; 530 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 531 fsc->sc_reg[0x40] = fsc->sc_portbits; 532 fsc->sc_reg[0x80] = 0; 533 *((volatile uint32_t *)fsc->sc_dmabase) = 0; 534 535 /* 536 * If output and length < 16, copy to fifo 537 */ 538 if (datain == 0 && fsc->sc_dmasize < 16) { 539 int n; 540 for (n = 0; n < fsc->sc_dmasize; ++n) 541 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 542 NCR_DMA(("flsc_dma_setup: %d bytes written to fifo\n", n)); 543 fsc->sc_piomode = 1; 544 fsc->sc_active = 1; 545 *fsc->sc_pdmalen -= fsc->sc_dmasize; 546 *fsc->sc_dmaaddr += fsc->sc_dmasize; 547 *dmasize = fsc->sc_dmasize; 548 fsc->sc_dmasize = 0; 549 return 0; /* All done */ 550 } 551 /* 552 * If output and unaligned, copy unaligned data to fifo 553 */ 554 else if (datain == 0 && (int)ptr & 3) { 555 int n = 4 - ((int)ptr & 3); 556 NCR_DMA(("flsc_dma_setup: align %d bytes written to fifo\n", n)); 557 pa += n; 558 xfer -= n; 559 while (n--) 560 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 561 } 562 /* 563 * If unaligned address, read unaligned bytes into alignment buffer 564 */ 565 else if ((int)ptr & 3 || xfer & 3) { 566 pa = kvtop((void *)fsc->sc_alignbuf); 567 xfer = fsc->sc_dmasize = min(xfer, sizeof(fsc->sc_unalignbuf)); 568 NCR_DMA(("flsc_dma_setup: align read by %d bytes\n", xfer)); 569 fsc->sc_xfr_align = 1; 570 } 571 /* 572 * If length smaller than longword, read into alignment buffer 573 * XXX doesn't work for 1 or 2 bytes !!!! 574 */ 575 else if (fsc->sc_dmasize < 4) { 576 NCR_DMA(("flsc_dma_setup: read remaining %d bytes\n", 577 fsc->sc_dmasize)); 578 pa = kvtop((void *)fsc->sc_alignbuf); 579 fsc->sc_xfr_align = 1; 580 } 581 /* 582 * Finally, limit transfer length to multiple of 4 bytes. 583 */ 584 else { 585 fsc->sc_dmasize &= -4; 586 xfer &= -4; 587 } 588 589 while (xfer < fsc->sc_dmasize) { 590 if ((pa + xfer) != kvtop(*addr + xfer)) 591 break; 592 if ((fsc->sc_dmasize - xfer) < PAGE_SIZE) 593 xfer = fsc->sc_dmasize; 594 else 595 xfer += PAGE_SIZE; 596 } 597 598 fsc->sc_dmasize = xfer; 599 *dmasize = fsc->sc_dmasize; 600 fsc->sc_pa = pa; 601 #if defined(M68040) || defined(M68060) 602 if (mmutype == MMU_68040) { 603 if (fsc->sc_xfr_align) { 604 int n; 605 for (n = 0; n < sizeof(fsc->sc_unalignbuf); ++n) 606 fsc->sc_alignbuf[n] = n | 0x80; 607 dma_cachectl(fsc->sc_alignbuf, 608 sizeof(fsc->sc_unalignbuf)); 609 } 610 else 611 dma_cachectl(*fsc->sc_dmaaddr, fsc->sc_dmasize); 612 } 613 #endif 614 fsc->sc_reg[0x80] = 0; 615 *((volatile uint32_t *)(fsc->sc_dmabase + (pa & 0x00fffffc))) = pa; 616 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 617 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 618 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 619 fsc->sc_reg[0x40] = fsc->sc_portbits; 620 NCR_DMA(("flsc_dma_setup: DMA %p->%lx/%d [%d]\n", 621 ptr, pa, fsc->sc_dmasize, *len)); 622 fsc->sc_active = 1; 623 return 0; 624 } 625 626 void 627 flsc_dma_go(struct ncr53c9x_softc *sc) 628 { 629 struct flsc_softc *fsc = (struct flsc_softc *)sc; 630 631 NCR_DMA(("flsc_dma_go: datain %d size %d\n", fsc->sc_datain, 632 fsc->sc_dmasize)); 633 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 634 fsc->sc_active = 1; 635 return; 636 } else if (fsc->sc_piomode == 0) { 637 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 638 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 639 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 640 fsc->sc_reg[0x40] = fsc->sc_portbits; 641 } 642 } 643 644 void 645 flsc_dma_stop(struct ncr53c9x_softc *sc) 646 { 647 struct flsc_softc *fsc = (struct flsc_softc *)sc; 648 649 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 650 fsc->sc_reg[0x40] = fsc->sc_portbits; 651 652 fsc->sc_reg[0x80] = 0; 653 *((volatile uint32_t *)fsc->sc_dmabase) = 0; 654 fsc->sc_piomode = 0; 655 } 656 657 int 658 flsc_dma_isactive(struct ncr53c9x_softc *sc) 659 { 660 struct flsc_softc *fsc = (struct flsc_softc *)sc; 661 662 return fsc->sc_active; 663 } 664