1 /* $NetBSD: flsc.c,v 1.29 2002/01/28 09:56:55 aymeric Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Initial amiga Fastlane driver by Daniel Widenfalk. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 42 */ 43 44 #include "opt_ddb.h" 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: flsc.c,v 1.29 2002/01/28 09:56:55 aymeric Exp $"); 48 49 #include <sys/types.h> 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/errno.h> 54 #include <sys/ioctl.h> 55 #include <sys/device.h> 56 #include <sys/buf.h> 57 #include <sys/proc.h> 58 #include <sys/user.h> 59 #include <sys/queue.h> 60 61 #include <dev/scsipi/scsi_all.h> 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsiconf.h> 64 #include <dev/scsipi/scsi_message.h> 65 66 #include <machine/cpu.h> 67 #include <machine/param.h> 68 69 #include <dev/ic/ncr53c9xreg.h> 70 #include <dev/ic/ncr53c9xvar.h> 71 72 #include <amiga/amiga/isr.h> 73 #include <amiga/dev/flscvar.h> 74 #include <amiga/dev/zbusvar.h> 75 76 void flscattach(struct device *, struct device *, void *); 77 int flscmatch(struct device *, struct cfdata *, void *); 78 79 /* Linkup to the rest of the kernel */ 80 struct cfattach flsc_ca = { 81 sizeof(struct flsc_softc), flscmatch, flscattach 82 }; 83 84 /* 85 * Functions and the switch for the MI code. 86 */ 87 u_char flsc_read_reg(struct ncr53c9x_softc *, int); 88 void flsc_write_reg(struct ncr53c9x_softc *, int, u_char); 89 int flsc_dma_isintr(struct ncr53c9x_softc *); 90 void flsc_dma_reset(struct ncr53c9x_softc *); 91 int flsc_dma_intr(struct ncr53c9x_softc *); 92 int flsc_dma_setup(struct ncr53c9x_softc *, caddr_t *, 93 size_t *, int, size_t *); 94 void flsc_dma_go(struct ncr53c9x_softc *); 95 void flsc_dma_stop(struct ncr53c9x_softc *); 96 int flsc_dma_isactive(struct ncr53c9x_softc *); 97 void flsc_clear_latched_intr(struct ncr53c9x_softc *); 98 99 struct ncr53c9x_glue flsc_glue = { 100 flsc_read_reg, 101 flsc_write_reg, 102 flsc_dma_isintr, 103 flsc_dma_reset, 104 flsc_dma_intr, 105 flsc_dma_setup, 106 flsc_dma_go, 107 flsc_dma_stop, 108 flsc_dma_isactive, 109 flsc_clear_latched_intr, 110 }; 111 112 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 113 u_long flsc_max_dma = 1024; 114 extern int ser_open_speed; 115 116 extern int ncr53c9x_debug; 117 extern u_long scsi_nosync; 118 extern int shift_nosync; 119 120 /* 121 * if we are an Advanced Systems & Software FastlaneZ3 122 */ 123 int 124 flscmatch(struct device *parent, struct cfdata *cf, void *aux) 125 { 126 struct zbus_args *zap; 127 128 if (!is_a4000() && !is_a3000()) 129 return(0); 130 131 zap = aux; 132 if (zap->manid == 0x2140 && zap->prodid == 11 133 && iszthreepa(zap->pa)) 134 return(1); 135 136 return(0); 137 } 138 139 /* 140 * Attach this instance, and then all the sub-devices 141 */ 142 void 143 flscattach(struct device *parent, struct device *self, void *aux) 144 { 145 struct flsc_softc *fsc = (void *)self; 146 struct ncr53c9x_softc *sc = &fsc->sc_ncr53c9x; 147 struct zbus_args *zap; 148 149 /* 150 * Set up the glue for MI code early; we use some of it here. 151 */ 152 sc->sc_glue = &flsc_glue; 153 154 /* 155 * Save the regs 156 */ 157 zap = aux; 158 fsc->sc_dmabase = (volatile u_char *)zap->va; 159 fsc->sc_reg = &((volatile u_char *)zap->va)[0x1000001]; 160 161 sc->sc_freq = 40; /* Clocked at 40Mhz */ 162 163 printf(": address %p", fsc->sc_reg); 164 165 sc->sc_id = 7; 166 167 /* 168 * It is necessary to try to load the 2nd config register here, 169 * to find out what rev the flsc chip is, else the flsc_reset 170 * will not set up the defaults correctly. 171 */ 172 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 173 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 174 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 175 sc->sc_rev = NCR_VARIANT_FAS216; 176 177 /* 178 * This is the value used to start sync negotiations 179 * Note that the NCR register "SYNCTP" is programmed 180 * in "clocks per byte", and has a minimum value of 4. 181 * The SCSI period used in negotiation is one-fourth 182 * of the time (in nanoseconds) needed to transfer one byte. 183 * Since the chip's clock is given in MHz, we have the following 184 * formula: 4 * period = (1000 / freq) * 4 185 */ 186 sc->sc_minsync = 1000 / sc->sc_freq; 187 188 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 189 sc->sc_minsync = 0; 190 191 /* Really no limit, but since we want to fit into the TCR... */ 192 sc->sc_maxxfer = 64 * 1024; 193 194 fsc->sc_portbits = 0xa0 | FLSC_PB_EDI | FLSC_PB_ESI; 195 fsc->sc_hardbits = fsc->sc_reg[0x40]; 196 197 fsc->sc_alignbuf = (char *)((u_long)fsc->sc_unalignbuf & -4); 198 199 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) & 0xffff; 200 shift_nosync += 16; 201 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 202 shift_nosync += 16; 203 204 /* 205 * Configure interrupts. 206 */ 207 fsc->sc_isr.isr_intr = ncr53c9x_intr; 208 fsc->sc_isr.isr_arg = sc; 209 fsc->sc_isr.isr_ipl = 2; 210 add_isr(&fsc->sc_isr); 211 212 fsc->sc_reg[0x40] = fsc->sc_portbits; 213 214 /* 215 * Now try to attach all the sub-devices 216 */ 217 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 218 sc->sc_adapter.adapt_minphys = minphys; 219 ncr53c9x_attach(sc); 220 } 221 222 /* 223 * Glue functions. 224 */ 225 226 u_char 227 flsc_read_reg(struct ncr53c9x_softc *sc, int reg) 228 { 229 struct flsc_softc *fsc = (struct flsc_softc *)sc; 230 231 return fsc->sc_reg[reg * 4]; 232 } 233 234 void 235 flsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 236 { 237 struct flsc_softc *fsc = (struct flsc_softc *)sc; 238 struct ncr53c9x_tinfo *ti; 239 u_char v = val; 240 241 if (fsc->sc_piomode && reg == NCR_CMD && 242 v == (NCRCMD_TRANS|NCRCMD_DMA)) { 243 v = NCRCMD_TRANS; 244 } 245 /* 246 * Can't do synchronous transfers in XS_CTL_POLL mode: 247 * If starting XS_CTL_POLL command, clear defer sync negotiation 248 * by clearing the T_NEGOTIATE flag. If starting XS_CTL_POLL and 249 * the device is currently running synchronous, force another 250 * T_NEGOTIATE with 0 offset. 251 */ 252 if (reg == NCR_SELID) { 253 ti = &sc->sc_tinfo[ 254 sc->sc_nexus->xs->xs_periph->periph_target]; 255 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 256 if (ti->flags & T_SYNCMODE) { 257 ti->flags ^= T_SYNCMODE | T_NEGOTIATE; 258 } else if (ti->flags & T_NEGOTIATE) { 259 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 260 /* save T_NEGOTIATE in private flags? */ 261 } 262 } else { 263 /* 264 * If we haven't attempted sync negotiation yet, 265 * do it now. 266 */ 267 if ((ti->flags & (T_SYNCMODE | T_SYNCHOFF)) == 268 T_SYNCHOFF && 269 sc->sc_minsync != 0) /* XXX */ 270 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 271 } 272 } 273 if (reg == NCR_CMD && v == NCRCMD_SETATN && 274 sc->sc_flags & NCR_SYNCHNEGO && 275 sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 276 ti = &sc->sc_tinfo[ 277 sc->sc_nexus->xs->xs_periph->periph_target]; 278 ti->offset = 0; 279 } 280 fsc->sc_reg[reg * 4] = v; 281 } 282 283 int 284 flsc_dma_isintr(struct ncr53c9x_softc *sc) 285 { 286 struct flsc_softc *fsc = (struct flsc_softc *)sc; 287 unsigned hardbits; 288 289 hardbits = fsc->sc_reg[0x40]; 290 if (hardbits & FLSC_HB_IACT) 291 return (fsc->sc_csr = 0); 292 293 if (sc->sc_state == NCR_CONNECTED || sc->sc_state == NCR_SELECTING) 294 fsc->sc_portbits |= FLSC_PB_LED; 295 else 296 fsc->sc_portbits &= ~FLSC_PB_LED; 297 298 if ((hardbits & FLSC_HB_CREQ) && !(hardbits & FLSC_HB_MINT) && 299 fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) { 300 return 1; 301 } 302 /* Do I still need this? */ 303 if (fsc->sc_piomode && fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT && 304 !(hardbits & FLSC_HB_MINT)) 305 return 1; 306 307 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 308 fsc->sc_reg[0x40] = fsc->sc_portbits; 309 return 0; 310 } 311 312 void 313 flsc_clear_latched_intr(struct ncr53c9x_softc *sc) 314 { 315 struct flsc_softc *fsc = (struct flsc_softc *)sc; 316 317 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 318 fsc->sc_reg[0x40] = fsc->sc_portbits; 319 } 320 321 void 322 flsc_dma_reset(struct ncr53c9x_softc *sc) 323 { 324 struct flsc_softc *fsc = (struct flsc_softc *)sc; 325 struct ncr53c9x_tinfo *ti; 326 327 if (sc->sc_nexus) 328 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 329 else 330 ti = &sc->sc_tinfo[1]; /* XXX */ 331 if (fsc->sc_active) { 332 printf("dmaaddr %p dmasize %d stat %x flags %x off %d per %d ff %x", 333 *fsc->sc_dmaaddr, fsc->sc_dmasize, fsc->sc_reg[NCR_STAT * 4], 334 ti->flags, ti->offset, ti->period, fsc->sc_reg[NCR_FFLAG * 4]); 335 printf(" intr %x\n", fsc->sc_reg[NCR_INTR * 4]); 336 #ifdef DDB 337 Debugger(); 338 #endif 339 } 340 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 341 fsc->sc_reg[0x40] = fsc->sc_portbits; 342 fsc->sc_reg[0x80] = 0; 343 *((u_long *)fsc->sc_dmabase) = 0; 344 fsc->sc_active = 0; 345 fsc->sc_piomode = 0; 346 } 347 348 int 349 flsc_dma_intr(struct ncr53c9x_softc *sc) 350 { 351 register struct flsc_softc *fsc = (struct flsc_softc *)sc; 352 register u_char *p; 353 volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg; 354 register u_int flscphase, flscstat, flscintr; 355 register int cnt; 356 357 NCR_DMA(("flsc_dma_intr: pio %d cnt %d int %x stat %x fifo %d ", 358 fsc->sc_piomode, fsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 359 fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 360 if (!(fsc->sc_reg[0x40] & FLSC_HB_CREQ)) 361 printf("flsc_dma_intr: csr %x stat %x intr %x\n", fsc->sc_csr, 362 sc->sc_espstat, sc->sc_espintr); 363 if (fsc->sc_active == 0) { 364 printf("flsc_intr--inactive DMA\n"); 365 return -1; 366 } 367 368 /* if DMA transfer, update sc_dmaaddr and sc_pdmalen, else PIO xfer */ 369 if (fsc->sc_piomode == 0) { 370 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 371 fsc->sc_reg[0x40] = fsc->sc_portbits; 372 fsc->sc_reg[0x80] = 0; 373 *((u_long *)fsc->sc_dmabase) = 0; 374 cnt = fsc->sc_reg[NCR_TCL * 4]; 375 cnt += fsc->sc_reg[NCR_TCM * 4] << 8; 376 cnt += fsc->sc_reg[NCR_TCH * 4] << 16; 377 if (!fsc->sc_datain) { 378 cnt += fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 379 fsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 380 } 381 cnt = fsc->sc_dmasize - cnt; /* number of bytes transferred */ 382 NCR_DMA(("DMA xferred %d\n", cnt)); 383 if (fsc->sc_xfr_align) { 384 int i; 385 for (i = 0; i < cnt; ++i) 386 (*fsc->sc_dmaaddr)[i] = fsc->sc_alignbuf[i]; 387 fsc->sc_xfr_align = 0; 388 } 389 *fsc->sc_dmaaddr += cnt; 390 *fsc->sc_pdmalen -= cnt; 391 fsc->sc_active = 0; 392 return 0; 393 } 394 395 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 396 fsc->sc_active = 0; 397 fsc->sc_piomode = 0; 398 NCR_DMA(("no NCRINTR_BS\n")); 399 return 0; 400 } 401 402 cnt = fsc->sc_dmasize; 403 #if 0 404 if (cnt == 0) { 405 printf("data interrupt, but no count left."); 406 } 407 #endif 408 409 p = *fsc->sc_dmaaddr; 410 flscphase = sc->sc_phase; 411 flscstat = (u_int) sc->sc_espstat; 412 flscintr = (u_int) sc->sc_espintr; 413 cmdreg = fsc->sc_reg + NCR_CMD * 4; 414 fiforeg = fsc->sc_reg + NCR_FIFO * 4; 415 statreg = fsc->sc_reg + NCR_STAT * 4; 416 intrreg = fsc->sc_reg + NCR_INTR * 4; 417 NCR_DMA(("PIO %d datain %d phase %d stat %x intr %x\n", 418 cnt, fsc->sc_datain, flscphase, flscstat, flscintr)); 419 do { 420 if (fsc->sc_datain) { 421 *p++ = *fiforeg; 422 cnt--; 423 if (flscphase == DATA_IN_PHASE) { 424 *cmdreg = NCRCMD_TRANS; 425 } else { 426 fsc->sc_active = 0; 427 } 428 } else { 429 NCR_DMA(("flsc_dma_intr: PIO out- phase %d cnt %d active %d\n", flscphase, cnt, 430 fsc->sc_active)); 431 if ( (flscphase == DATA_OUT_PHASE) 432 || (flscphase == MESSAGE_OUT_PHASE)) { 433 int n; 434 n = 16 - (fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF); 435 if (n > cnt) 436 n = cnt; 437 cnt -= n; 438 while (n-- > 0) 439 *fiforeg = *p++; 440 *cmdreg = NCRCMD_TRANS; 441 } else { 442 fsc->sc_active = 0; 443 } 444 } 445 446 if (fsc->sc_active && cnt) { 447 while (!(*statreg & 0x80)); 448 flscstat = *statreg; 449 flscintr = *intrreg; 450 flscphase = (flscintr & NCRINTR_DIS) 451 ? /* Disconnected */ BUSFREE_PHASE 452 : flscstat & PHASE_MASK; 453 } 454 } while (cnt && fsc->sc_active && (flscintr & NCRINTR_BS)); 455 #if 1 456 if (fsc->sc_dmasize < 8 && cnt) 457 printf("flsc_dma_intr: short transfer: dmasize %d cnt %d\n", 458 fsc->sc_dmasize, cnt); 459 #endif 460 NCR_DMA(("flsc_dma_intr: PIO transfer [%d], %d->%d phase %d stat %x intr %x\n", 461 *fsc->sc_pdmalen, fsc->sc_dmasize, cnt, flscphase, flscstat, flscintr)); 462 sc->sc_phase = flscphase; 463 sc->sc_espstat = (u_char) flscstat; 464 sc->sc_espintr = (u_char) flscintr; 465 *fsc->sc_dmaaddr = p; 466 *fsc->sc_pdmalen -= fsc->sc_dmasize - cnt; 467 fsc->sc_dmasize = cnt; 468 469 if (*fsc->sc_pdmalen == 0) { 470 sc->sc_espstat |= NCRSTAT_TC; 471 fsc->sc_piomode = 0; 472 } 473 return 0; 474 } 475 476 int 477 flsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 478 int datain, size_t *dmasize) 479 { 480 struct flsc_softc *fsc = (struct flsc_softc *)sc; 481 paddr_t pa; 482 u_char *ptr; 483 size_t xfer; 484 485 fsc->sc_dmaaddr = addr; 486 fsc->sc_pdmalen = len; 487 fsc->sc_datain = datain; 488 fsc->sc_dmasize = *dmasize; 489 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 490 /* polling mode, use PIO */ 491 *dmasize = fsc->sc_dmasize; 492 NCR_DMA(("pfsc_dma_setup: PIO %p/%d [%d]\n", *addr, 493 fsc->sc_dmasize, *len)); 494 fsc->sc_piomode = 1; 495 if (datain == 0) { 496 int n; 497 n = fsc->sc_dmasize; 498 if (n > 16) 499 n = 16; 500 while (n-- > 0) { 501 fsc->sc_reg[NCR_FIFO * 4] = **fsc->sc_dmaaddr; 502 (*fsc->sc_pdmalen)--; 503 (*fsc->sc_dmaaddr)++; 504 --fsc->sc_dmasize; 505 } 506 } 507 return 0; 508 } 509 /* 510 * DMA can be nasty for high-speed serial input, so limit the 511 * size of this DMA operation if the serial port is running at 512 * a high speed (higher than 19200 for now - should be adjusted 513 * based on cpu type and speed?). 514 * XXX - add serial speed check XXX 515 */ 516 if (ser_open_speed > 19200 && flsc_max_dma != 0 && 517 fsc->sc_dmasize > flsc_max_dma) 518 fsc->sc_dmasize = flsc_max_dma; 519 ptr = *addr; /* Kernel virtual address */ 520 pa = kvtop(ptr); /* Physical address of DMA */ 521 xfer = min(fsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 522 fsc->sc_xfr_align = 0; 523 fsc->sc_piomode = 0; 524 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 525 fsc->sc_reg[0x40] = fsc->sc_portbits; 526 fsc->sc_reg[0x80] = 0; 527 *((u_long *)fsc->sc_dmabase) = 0; 528 529 /* 530 * If output and length < 16, copy to fifo 531 */ 532 if (datain == 0 && fsc->sc_dmasize < 16) { 533 int n; 534 for (n = 0; n < fsc->sc_dmasize; ++n) 535 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 536 NCR_DMA(("flsc_dma_setup: %d bytes written to fifo\n", n)); 537 fsc->sc_piomode = 1; 538 fsc->sc_active = 1; 539 *fsc->sc_pdmalen -= fsc->sc_dmasize; 540 *fsc->sc_dmaaddr += fsc->sc_dmasize; 541 *dmasize = fsc->sc_dmasize; 542 fsc->sc_dmasize = 0; 543 return 0; /* All done */ 544 } 545 /* 546 * If output and unaligned, copy unaligned data to fifo 547 */ 548 else if (datain == 0 && (int)ptr & 3) { 549 int n = 4 - ((int)ptr & 3); 550 NCR_DMA(("flsc_dma_setup: align %d bytes written to fifo\n", n)); 551 pa += n; 552 xfer -= n; 553 while (n--) 554 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 555 } 556 /* 557 * If unaligned address, read unaligned bytes into alignment buffer 558 */ 559 else if ((int)ptr & 3 || xfer & 3) { 560 pa = kvtop((caddr_t)fsc->sc_alignbuf); 561 xfer = fsc->sc_dmasize = min(xfer, sizeof (fsc->sc_unalignbuf)); 562 NCR_DMA(("flsc_dma_setup: align read by %d bytes\n", xfer)); 563 fsc->sc_xfr_align = 1; 564 } 565 /* 566 * If length smaller than longword, read into alignment buffer 567 * XXX doesn't work for 1 or 2 bytes !!!! 568 */ 569 else if (fsc->sc_dmasize < 4) { 570 NCR_DMA(("flsc_dma_setup: read remaining %d bytes\n", 571 fsc->sc_dmasize)); 572 pa = kvtop((caddr_t)fsc->sc_alignbuf); 573 fsc->sc_xfr_align = 1; 574 } 575 /* 576 * Finally, limit transfer length to multiple of 4 bytes. 577 */ 578 else { 579 fsc->sc_dmasize &= -4; 580 xfer &= -4; 581 } 582 583 while (xfer < fsc->sc_dmasize) { 584 if ((pa + xfer) != kvtop(*addr + xfer)) 585 break; 586 if ((fsc->sc_dmasize - xfer) < NBPG) 587 xfer = fsc->sc_dmasize; 588 else 589 xfer += NBPG; 590 } 591 592 fsc->sc_dmasize = xfer; 593 *dmasize = fsc->sc_dmasize; 594 fsc->sc_pa = pa; 595 #if defined(M68040) || defined(M68060) 596 if (mmutype == MMU_68040) { 597 if (fsc->sc_xfr_align) { 598 int n; 599 for (n = 0; n < sizeof (fsc->sc_unalignbuf); ++n) 600 fsc->sc_alignbuf[n] = n | 0x80; 601 dma_cachectl(fsc->sc_alignbuf, 602 sizeof(fsc->sc_unalignbuf)); 603 } 604 else 605 dma_cachectl(*fsc->sc_dmaaddr, fsc->sc_dmasize); 606 } 607 #endif 608 fsc->sc_reg[0x80] = 0; 609 *((u_long *)(fsc->sc_dmabase + (pa & 0x00fffffc))) = pa; 610 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 611 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 612 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 613 fsc->sc_reg[0x40] = fsc->sc_portbits; 614 NCR_DMA(("flsc_dma_setup: DMA %p->%lx/%d [%d]\n", 615 ptr, pa, fsc->sc_dmasize, *len)); 616 fsc->sc_active = 1; 617 return 0; 618 } 619 620 void 621 flsc_dma_go(struct ncr53c9x_softc *sc) 622 { 623 struct flsc_softc *fsc = (struct flsc_softc *)sc; 624 625 NCR_DMA(("flsc_dma_go: datain %d size %d\n", fsc->sc_datain, 626 fsc->sc_dmasize)); 627 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 628 fsc->sc_active = 1; 629 return; 630 } else if (fsc->sc_piomode == 0) { 631 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 632 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 633 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 634 fsc->sc_reg[0x40] = fsc->sc_portbits; 635 } 636 } 637 638 void 639 flsc_dma_stop(struct ncr53c9x_softc *sc) 640 { 641 struct flsc_softc *fsc = (struct flsc_softc *)sc; 642 643 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 644 fsc->sc_reg[0x40] = fsc->sc_portbits; 645 646 fsc->sc_reg[0x80] = 0; 647 *((u_long *)fsc->sc_dmabase) = 0; 648 fsc->sc_piomode = 0; 649 } 650 651 int 652 flsc_dma_isactive(struct ncr53c9x_softc *sc) 653 { 654 struct flsc_softc *fsc = (struct flsc_softc *)sc; 655 656 return fsc->sc_active; 657 } 658