1*e0040f99Schristos /* $NetBSD: grf_cvreg.h,v 1.20 2014/01/22 00:25:16 christos Exp $ */
20cd79344Sjtc
3cc6ab4e6Schopps /*
4cc6ab4e6Schopps * Copyright (c) 1995 Michael Teske
5cc6ab4e6Schopps * All rights reserved.
6cc6ab4e6Schopps *
7cc6ab4e6Schopps * Redistribution and use in source and binary forms, with or without
8cc6ab4e6Schopps * modification, are permitted provided that the following conditions
9cc6ab4e6Schopps * are met:
10cc6ab4e6Schopps * 1. Redistributions of source code must retain the above copyright
11cc6ab4e6Schopps * notice, this list of conditions and the following disclaimer.
12cc6ab4e6Schopps * 2. Redistributions in binary form must reproduce the above copyright
13cc6ab4e6Schopps * notice, this list of conditions and the following disclaimer in the
14cc6ab4e6Schopps * documentation and/or other materials provided with the distribution.
15cc6ab4e6Schopps * 3. All advertising materials mentioning features or use of this software
16cc6ab4e6Schopps * must display the following acknowledgement:
17cc6ab4e6Schopps * This product includes software developed by Ezra Story, by Kari
18cc6ab4e6Schopps * Mettinen and by Bernd Ernesti.
19cc6ab4e6Schopps * 4. The name of the author may not be used to endorse or promote products
20cc6ab4e6Schopps * derived from this software without specific prior written permission
21cc6ab4e6Schopps *
22cc6ab4e6Schopps * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23cc6ab4e6Schopps * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24cc6ab4e6Schopps * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25cc6ab4e6Schopps * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26cc6ab4e6Schopps * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27cc6ab4e6Schopps * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28cc6ab4e6Schopps * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29cc6ab4e6Schopps * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30cc6ab4e6Schopps * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31cc6ab4e6Schopps * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32cc6ab4e6Schopps */
33cc6ab4e6Schopps
34cc6ab4e6Schopps #ifndef _GRF_CVREG_H
35cc6ab4e6Schopps #define _GRF_CVREG_H
36cc6ab4e6Schopps
373055d8c0Sphx #include <machine/cpu.h>
383055d8c0Sphx
39cc6ab4e6Schopps /*
40de2e89deSphx * This is derived from Cirrus driver source
41cc6ab4e6Schopps */
42cc6ab4e6Schopps
43cc6ab4e6Schopps /* Extension to grfvideo_mode to support text modes.
44cc6ab4e6Schopps * This can be passed to both text & gfx functions
45cc6ab4e6Schopps * without worry. If gv.depth == 4, then the extended
46cc6ab4e6Schopps * fields for a text mode are present.
47cc6ab4e6Schopps */
48cc6ab4e6Schopps
49cc6ab4e6Schopps struct grfcvtext_mode {
50cc6ab4e6Schopps struct grfvideo_mode gv;
51cc6ab4e6Schopps unsigned short fx; /* font x dimension */
52cc6ab4e6Schopps unsigned short fy; /* font y dimension */
53cc6ab4e6Schopps unsigned short cols; /* screen dimensions */
54cc6ab4e6Schopps unsigned short rows;
55cc6ab4e6Schopps void *fdata; /* font data */
56cc6ab4e6Schopps unsigned short fdstart;
57cc6ab4e6Schopps unsigned short fdend;
58cc6ab4e6Schopps };
59cc6ab4e6Schopps
600d233c80Sphx
61cc6ab4e6Schopps /* read VGA register */
62ae95aa4aSphx #define vgar(ba, reg) \
63ae95aa4aSphx (*(((volatile char *)ba)+reg))
64cc6ab4e6Schopps
65cc6ab4e6Schopps /* write VGA register */
66cc6ab4e6Schopps #define vgaw(ba, reg, val) \
67ae95aa4aSphx *(((volatile char *)ba)+reg) = ((val) & 0xff); \
68ae95aa4aSphx amiga_membarrier()
6918fd2ce9Sveego
7018fd2ce9Sveego /* read 32 Bit VGA register */
718247f5f1She #define vgar32(ba, reg) \
728247f5f1She ( *((volatile unsigned long *) (((volatile char *)ba)+reg)) )
7318fd2ce9Sveego
7418fd2ce9Sveego /* write 32 Bit VGA register */
7518fd2ce9Sveego #define vgaw32(ba, reg, val) \
76ae95aa4aSphx *((unsigned long *) (((volatile char *)ba)+reg)) = val; \
77ae95aa4aSphx amiga_membarrier()
7818fd2ce9Sveego
7918fd2ce9Sveego /* read 16 Bit VGA register */
808247f5f1She #define vgar16(ba, reg) \
818247f5f1She ( *((volatile unsigned short *) (((volatile char *)ba)+reg)) )
8218fd2ce9Sveego
8318fd2ce9Sveego /* write 16 Bit VGA register */
8418fd2ce9Sveego #define vgaw16(ba, reg, val) \
85ae95aa4aSphx *((volatile unsigned short *) (((volatile char *)ba)+reg)) = val; \
86ae95aa4aSphx amiga_membarrier()
8718fd2ce9Sveego
88bf3440b2Smhitch #ifdef _KERNEL
899382c873Saymeric int grfcv_cnprobe(void);
909382c873Saymeric void grfcv_iteinit(struct grf_softc *);
9153524e44Schristos static inline void GfxBusyWait(volatile void *);
9253524e44Schristos static inline void GfxFifoWait(volatile void *);
9353524e44Schristos static inline unsigned char RAttr(volatile void *, short);
9453524e44Schristos static inline unsigned char RSeq(volatile void *, short);
9553524e44Schristos static inline unsigned char RCrt(volatile void *, short);
9653524e44Schristos static inline unsigned char RGfx(volatile void *, short);
97bf3440b2Smhitch #endif
9818fd2ce9Sveego
9918fd2ce9Sveego
100cc6ab4e6Schopps /*
101cc6ab4e6Schopps * defines for the used register addresses (mw)
102cc6ab4e6Schopps *
103cc6ab4e6Schopps * NOTE: there are some registers that have different addresses when
104cc6ab4e6Schopps * in mono or color mode. We only support color mode, and thus
105cc6ab4e6Schopps * some addresses won't work in mono-mode!
106cc6ab4e6Schopps *
107cc6ab4e6Schopps * General and VGA-registers taken from retina driver. Fixed a few
108cc6ab4e6Schopps * bugs in it. (SR and GR read address is Port + 1, NOT Port)
109cc6ab4e6Schopps *
110cc6ab4e6Schopps */
111cc6ab4e6Schopps
112cc6ab4e6Schopps /* General Registers: */
113cc6ab4e6Schopps #define GREG_MISC_OUTPUT_R 0x03CC
114cc6ab4e6Schopps #define GREG_MISC_OUTPUT_W 0x03C2
115cc6ab4e6Schopps #define GREG_FEATURE_CONTROL_R 0x03CA
116cc6ab4e6Schopps #define GREG_FEATURE_CONTROL_W 0x03DA
117cc6ab4e6Schopps #define GREG_INPUT_STATUS0_R 0x03C2
118cc6ab4e6Schopps #define GREG_INPUT_STATUS1_R 0x03DA
119cc6ab4e6Schopps
120cc6ab4e6Schopps /* Setup Registers: */
121cc6ab4e6Schopps #define SREG_OPTION_SELECT 0x0102
122cc6ab4e6Schopps #define SREG_VIDEO_SUBS_ENABLE 0x46E8
123cc6ab4e6Schopps
124cc6ab4e6Schopps /* Attribute Controller: */
125cc6ab4e6Schopps #define ACT_ADDRESS 0x03C0
126cc6ab4e6Schopps #define ACT_ADDRESS_R 0x03C1
127cc6ab4e6Schopps #define ACT_ADDRESS_W 0x03C0
128cc6ab4e6Schopps #define ACT_ADDRESS_RESET 0x03DA
129cc6ab4e6Schopps #define ACT_ID_PALETTE0 0x00
130cc6ab4e6Schopps #define ACT_ID_PALETTE1 0x01
131cc6ab4e6Schopps #define ACT_ID_PALETTE2 0x02
132cc6ab4e6Schopps #define ACT_ID_PALETTE3 0x03
133cc6ab4e6Schopps #define ACT_ID_PALETTE4 0x04
134cc6ab4e6Schopps #define ACT_ID_PALETTE5 0x05
135cc6ab4e6Schopps #define ACT_ID_PALETTE6 0x06
136cc6ab4e6Schopps #define ACT_ID_PALETTE7 0x07
137cc6ab4e6Schopps #define ACT_ID_PALETTE8 0x08
138cc6ab4e6Schopps #define ACT_ID_PALETTE9 0x09
139cc6ab4e6Schopps #define ACT_ID_PALETTE10 0x0A
140cc6ab4e6Schopps #define ACT_ID_PALETTE11 0x0B
141cc6ab4e6Schopps #define ACT_ID_PALETTE12 0x0C
142cc6ab4e6Schopps #define ACT_ID_PALETTE13 0x0D
143cc6ab4e6Schopps #define ACT_ID_PALETTE14 0x0E
144cc6ab4e6Schopps #define ACT_ID_PALETTE15 0x0F
145cc6ab4e6Schopps #define ACT_ID_ATTR_MODE_CNTL 0x10
146cc6ab4e6Schopps #define ACT_ID_OVERSCAN_COLOR 0x11
147cc6ab4e6Schopps #define ACT_ID_COLOR_PLANE_ENA 0x12
148cc6ab4e6Schopps #define ACT_ID_HOR_PEL_PANNING 0x13
149cc6ab4e6Schopps #define ACT_ID_COLOR_SELECT 0x14
150cc6ab4e6Schopps
151cc6ab4e6Schopps /* Graphics Controller: */
152cc6ab4e6Schopps #define GCT_ADDRESS 0x03CE
153cc6ab4e6Schopps #define GCT_ADDRESS_R 0x03CF
154cc6ab4e6Schopps #define GCT_ADDRESS_W 0x03CF
155cc6ab4e6Schopps #define GCT_ID_SET_RESET 0x00
156cc6ab4e6Schopps #define GCT_ID_ENABLE_SET_RESET 0x01
157cc6ab4e6Schopps #define GCT_ID_COLOR_COMPARE 0x02
158cc6ab4e6Schopps #define GCT_ID_DATA_ROTATE 0x03
159cc6ab4e6Schopps #define GCT_ID_READ_MAP_SELECT 0x04
160cc6ab4e6Schopps #define GCT_ID_GRAPHICS_MODE 0x05
161cc6ab4e6Schopps #define GCT_ID_MISC 0x06
162cc6ab4e6Schopps #define GCT_ID_COLOR_XCARE 0x07
163cc6ab4e6Schopps #define GCT_ID_BITMASK 0x08
164cc6ab4e6Schopps
165cc6ab4e6Schopps /* Sequencer: */
166cc6ab4e6Schopps #define SEQ_ADDRESS 0x03C4
167cc6ab4e6Schopps #define SEQ_ADDRESS_R 0x03C5
168cc6ab4e6Schopps #define SEQ_ADDRESS_W 0x03C5
169cc6ab4e6Schopps #define SEQ_ID_RESET 0x00
170cc6ab4e6Schopps #define SEQ_ID_CLOCKING_MODE 0x01
171cc6ab4e6Schopps #define SEQ_ID_MAP_MASK 0x02
172cc6ab4e6Schopps #define SEQ_ID_CHAR_MAP_SELECT 0x03
173cc6ab4e6Schopps #define SEQ_ID_MEMORY_MODE 0x04
174cc6ab4e6Schopps #define SEQ_ID_UNKNOWN1 0x05
175cc6ab4e6Schopps #define SEQ_ID_UNKNOWN2 0x06
176cc6ab4e6Schopps #define SEQ_ID_UNKNOWN3 0x07
177cc6ab4e6Schopps /* S3 extensions */
178cc6ab4e6Schopps #define SEQ_ID_UNLOCK_EXT 0x08
179cc6ab4e6Schopps #define SEQ_ID_EXT_SEQ_REG9 0x09
180cc6ab4e6Schopps #define SEQ_ID_BUS_REQ_CNTL 0x0A
181cc6ab4e6Schopps #define SEQ_ID_EXT_MISC_SEQ 0x0B
182cc6ab4e6Schopps #define SEQ_ID_UNKNOWN4 0x0C
183cc6ab4e6Schopps #define SEQ_ID_EXT_SEQ 0x0D
184cc6ab4e6Schopps #define SEQ_ID_UNKNOWN5 0x0E
185cc6ab4e6Schopps #define SEQ_ID_UNKNOWN6 0x0F
186cc6ab4e6Schopps #define SEQ_ID_MCLK_LO 0x10
187cc6ab4e6Schopps #define SEQ_ID_MCLK_HI 0x11
188cc6ab4e6Schopps #define SEQ_ID_DCLK_LO 0x12
189cc6ab4e6Schopps #define SEQ_ID_DCLK_HI 0x13
190cc6ab4e6Schopps #define SEQ_ID_CLKSYN_CNTL_1 0x14
191cc6ab4e6Schopps #define SEQ_ID_CLKSYN_CNTL_2 0x15
192cc6ab4e6Schopps #define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */
193cc6ab4e6Schopps #define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */
194cc6ab4e6Schopps #define SEQ_ID_RAMDAC_CNTL 0x18
195dafae56aSchopps #define SEQ_ID_MORE_MAGIC 0x1A
196cc6ab4e6Schopps
197cc6ab4e6Schopps /* CRT Controller: */
198cc6ab4e6Schopps #define CRT_ADDRESS 0x03D4
199cc6ab4e6Schopps #define CRT_ADDRESS_R 0x03D5
200cc6ab4e6Schopps #define CRT_ADDRESS_W 0x03D5
201cc6ab4e6Schopps #define CRT_ID_HOR_TOTAL 0x00
202cc6ab4e6Schopps #define CRT_ID_HOR_DISP_ENA_END 0x01
203cc6ab4e6Schopps #define CRT_ID_START_HOR_BLANK 0x02
204cc6ab4e6Schopps #define CRT_ID_END_HOR_BLANK 0x03
205cc6ab4e6Schopps #define CRT_ID_START_HOR_RETR 0x04
206cc6ab4e6Schopps #define CRT_ID_END_HOR_RETR 0x05
207cc6ab4e6Schopps #define CRT_ID_VER_TOTAL 0x06
208cc6ab4e6Schopps #define CRT_ID_OVERFLOW 0x07
209cc6ab4e6Schopps #define CRT_ID_PRESET_ROW_SCAN 0x08
210cc6ab4e6Schopps #define CRT_ID_MAX_SCAN_LINE 0x09
211cc6ab4e6Schopps #define CRT_ID_CURSOR_START 0x0A
212cc6ab4e6Schopps #define CRT_ID_CURSOR_END 0x0B
213cc6ab4e6Schopps #define CRT_ID_START_ADDR_HIGH 0x0C
214cc6ab4e6Schopps #define CRT_ID_START_ADDR_LOW 0x0D
215cc6ab4e6Schopps #define CRT_ID_CURSOR_LOC_HIGH 0x0E
216cc6ab4e6Schopps #define CRT_ID_CURSOR_LOC_LOW 0x0F
217cc6ab4e6Schopps #define CRT_ID_START_VER_RETR 0x10
218cc6ab4e6Schopps #define CRT_ID_END_VER_RETR 0x11
219cc6ab4e6Schopps #define CRT_ID_VER_DISP_ENA_END 0x12
220cc6ab4e6Schopps #define CRT_ID_SCREEN_OFFSET 0x13
221cc6ab4e6Schopps #define CRT_ID_UNDERLINE_LOC 0x14
222cc6ab4e6Schopps #define CRT_ID_START_VER_BLANK 0x15
223cc6ab4e6Schopps #define CRT_ID_END_VER_BLANK 0x16
224cc6ab4e6Schopps #define CRT_ID_MODE_CONTROL 0x17
225cc6ab4e6Schopps #define CRT_ID_LINE_COMPARE 0x18
226cc6ab4e6Schopps #define CRT_ID_GD_LATCH_RBACK 0x22
227cc6ab4e6Schopps #define CRT_ID_ACT_TOGGLE_RBACK 0x24
228cc6ab4e6Schopps #define CRT_ID_ACT_INDEX_RBACK 0x26
229cc6ab4e6Schopps /* S3 extensions: S3 VGA Registers */
230cc6ab4e6Schopps #define CRT_ID_DEVICE_HIGH 0x2D
231cc6ab4e6Schopps #define CRT_ID_DEVICE_LOW 0x2E
232cc6ab4e6Schopps #define CRT_ID_REVISION 0x2F
233cc6ab4e6Schopps #define CRT_ID_CHIP_ID_REV 0x30
234cc6ab4e6Schopps #define CRT_ID_MEMORY_CONF 0x31
235cc6ab4e6Schopps #define CRT_ID_BACKWAD_COMP_1 0x32
236cc6ab4e6Schopps #define CRT_ID_BACKWAD_COMP_2 0x33
237cc6ab4e6Schopps #define CRT_ID_BACKWAD_COMP_3 0x34
238cc6ab4e6Schopps #define CRT_ID_REGISTER_LOCK 0x35
239cc6ab4e6Schopps #define CRT_ID_CONFIG_1 0x36
240cc6ab4e6Schopps #define CRT_ID_CONFIG_2 0x37
241cc6ab4e6Schopps #define CRT_ID_REGISTER_LOCK_1 0x38
242cc6ab4e6Schopps #define CRT_ID_REGISTER_LOCK_2 0x39
243cc6ab4e6Schopps #define CRT_ID_MISC_1 0x3A
244cc6ab4e6Schopps #define CRT_ID_DISPLAY_FIFO 0x3B
245cc6ab4e6Schopps #define CRT_ID_LACE_RETR_START 0x3C
246cc6ab4e6Schopps /* S3 extensions: System Control Registers */
247cc6ab4e6Schopps #define CRT_ID_SYSTEM_CONFIG 0x40
248cc6ab4e6Schopps #define CRT_ID_BIOS_FLAG 0x41
249cc6ab4e6Schopps #define CRT_ID_LACE_CONTROL 0x42
250cc6ab4e6Schopps #define CRT_ID_EXT_MODE 0x43
251cc6ab4e6Schopps #define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */
252cc6ab4e6Schopps #define CRT_ID_HWGC_ORIGIN_X_HI 0x46
253cc6ab4e6Schopps #define CRT_ID_HWGC_ORIGIN_X_LO 0x47
254cc6ab4e6Schopps #define CRT_ID_HWGC_ORIGIN_Y_HI 0x48
255cc6ab4e6Schopps #define CRT_ID_HWGC_ORIGIN_Y_LO 0x49
256cc6ab4e6Schopps #define CRT_ID_HWGC_FG_STACK 0x4A
257cc6ab4e6Schopps #define CRT_ID_HWGC_BG_STACK 0x4B
258cc6ab4e6Schopps #define CRT_ID_HWGC_START_AD_HI 0x4C
259cc6ab4e6Schopps #define CRT_ID_HWGC_START_AD_LO 0x4D
260cc6ab4e6Schopps #define CRT_ID_HWGC_DSTART_X 0x4E
261cc6ab4e6Schopps #define CRT_ID_HWGC_DSTART_Y 0x4F
262cc6ab4e6Schopps /* S3 extensions: System Extension Registers */
263cc6ab4e6Schopps #define CRT_ID_EXT_SYS_CNTL_1 0x50
264cc6ab4e6Schopps #define CRT_ID_EXT_SYS_CNTL_2 0x51
265cc6ab4e6Schopps #define CRT_ID_EXT_BIOS_FLAG_1 0x52
266cc6ab4e6Schopps #define CRT_ID_EXT_MEM_CNTL_1 0x53
267cc6ab4e6Schopps #define CRT_ID_EXT_MEM_CNTL_2 0x54
268cc6ab4e6Schopps #define CRT_ID_EXT_DAC_CNTL 0x55
269cc6ab4e6Schopps #define CRT_ID_EX_SYNC_1 0x56
270cc6ab4e6Schopps #define CRT_ID_EX_SYNC_2 0x57
271cc6ab4e6Schopps #define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */
272cc6ab4e6Schopps #define CRT_ID_LAW_POS_HI 0x59
273cc6ab4e6Schopps #define CRT_ID_LAW_POS_LO 0x5A
274cc6ab4e6Schopps #define CRT_ID_GOUT_PORT 0x5C
275cc6ab4e6Schopps #define CRT_ID_EXT_HOR_OVF 0x5D
276cc6ab4e6Schopps #define CRT_ID_EXT_VER_OVF 0x5E
277cc6ab4e6Schopps #define CRT_ID_EXT_MEM_CNTL_3 0x60
278cc6ab4e6Schopps #define CRT_ID_EX_SYNC_3 0x63
279cc6ab4e6Schopps #define CRT_ID_EXT_MISC_CNTL 0x65
280cc6ab4e6Schopps #define CRT_ID_EXT_MISC_CNTL_1 0x66
281cc6ab4e6Schopps #define CRT_ID_EXT_MISC_CNTL_2 0x67
282cc6ab4e6Schopps #define CRT_ID_CONFIG_3 0x68
283cc6ab4e6Schopps #define CRT_ID_EXT_SYS_CNTL_3 0x69
284cc6ab4e6Schopps #define CRT_ID_EXT_SYS_CNTL_4 0x6A
285cc6ab4e6Schopps #define CRT_ID_EXT_BIOS_FLAG_3 0x6B
286cc6ab4e6Schopps #define CRT_ID_EXT_BIOS_FLAG_4 0x6C
287cc6ab4e6Schopps
288cc6ab4e6Schopps /* Enhanced Commands Registers: */
289cc6ab4e6Schopps #define ECR_SUBSYSTEM_STAT 0x42E8
290cc6ab4e6Schopps #define ECR_SUBSYSTEM_CNTL 0x42E8
291cc6ab4e6Schopps #define ECR_ADV_FUNC_CNTL 0x4AE8
292cc6ab4e6Schopps #define ECR_CURRENT_Y_POS 0x82E8
293cc6ab4e6Schopps #define ECR_CURRENT_Y_POS2 0x82EA /* Trio64 only */
294cc6ab4e6Schopps #define ECR_CURRENT_X_POS 0x86E8
295cc6ab4e6Schopps #define ECR_CURRENT_X_POS2 0x86EA /* Trio64 only */
296cc6ab4e6Schopps #define ECR_DEST_Y__AX_STEP 0x8AE8
297cc6ab4e6Schopps #define ECR_DEST_Y2__AX_STEP2 0x8AEA /* Trio64 only */
298cc6ab4e6Schopps #define ECR_DEST_X__DIA_STEP 0x8EE8
299cc6ab4e6Schopps #define ECR_DEST_X2__DIA_STEP2 0x8EEA /* Trio64 only */
300cc6ab4e6Schopps #define ECR_ERR_TERM 0x92E8
301cc6ab4e6Schopps #define ECR_ERR_TERM2 0x92EA /* Trio64 only */
302cc6ab4e6Schopps #define ECR_MAJ_AXIS_PIX_CNT 0x96E8
303cc6ab4e6Schopps #define ECR_MAJ_AXIS_PIX_CNT2 0x96EA /* Trio64 only */
304cc6ab4e6Schopps #define ECR_GP_STAT 0x9AE8 /* GP = Graphics Processor */
305cc6ab4e6Schopps #define ECR_DRAW_CMD 0x9AE8
306cc6ab4e6Schopps #define ECR_DRAW_CMD2 0x9AEA /* Trio64 only */
307cc6ab4e6Schopps #define ECR_SHORT_STROKE 0x9EE8
308cc6ab4e6Schopps #define ECR_BKGD_COLOR 0xA2E8 /* BKGD = Background */
309cc6ab4e6Schopps #define ECR_FRGD_COLOR 0xA6E8 /* FRGD = Foreground */
310cc6ab4e6Schopps #define ECR_BITPLANE_WRITE_MASK 0xAAE8
311cc6ab4e6Schopps #define ECR_BITPLANE_READ_MASK 0xAEE8
312cc6ab4e6Schopps #define ECR_COLOR_COMPARE 0xB2E8
313cc6ab4e6Schopps #define ECR_BKGD_MIX 0xB6E8
314cc6ab4e6Schopps #define ECR_FRGD_MIX 0xBAE8
315cc6ab4e6Schopps #define ECR_READ_REG_DATA 0xBEE8
316cc6ab4e6Schopps #define ECR_ID_MIN_AXIS_PIX_CNT 0x00
317cc6ab4e6Schopps #define ECR_ID_SCISSORS_TOP 0x01
318cc6ab4e6Schopps #define ECR_ID_SCISSORS_LEFT 0x02
319cc6ab4e6Schopps #define ECR_ID_SCISSORS_BUTTOM 0x03
320cc6ab4e6Schopps #define ECR_ID_SCISSORS_RIGHT 0x04
321cc6ab4e6Schopps #define ECR_ID_PIX_CNTL 0x0A
322cc6ab4e6Schopps #define ECR_ID_MULT_CNTL_MISC_2 0x0D
323cc6ab4e6Schopps #define ECR_ID_MULT_CNTL_MISC 0x0E
324cc6ab4e6Schopps #define ECR_ID_READ_SEL 0x0F
325cc6ab4e6Schopps #define ECR_PIX_TRANS 0xE2E8
326cc6ab4e6Schopps #define ECR_PIX_TRANS_EXT 0xE2EA
327cc6ab4e6Schopps #define ECR_PATTERN_Y 0xEAE8 /* Trio64 only */
328cc6ab4e6Schopps #define ECR_PATTERN_X 0xEAEA /* Trio64 only */
329cc6ab4e6Schopps
330cc6ab4e6Schopps
331cc6ab4e6Schopps /* Pass-through */
332cc6ab4e6Schopps #define PASS_ADDRESS 0x40001
333cc6ab4e6Schopps #define PASS_ADDRESS_W 0x40001
334cc6ab4e6Schopps
335cc6ab4e6Schopps /* Video DAC */
336cc6ab4e6Schopps #define VDAC_ADDRESS 0x03c8
337cc6ab4e6Schopps #define VDAC_ADDRESS_W 0x03c8
338cc6ab4e6Schopps #define VDAC_ADDRESS_R 0x03c7
339cc6ab4e6Schopps #define VDAC_STATE 0x03c7
340cc6ab4e6Schopps #define VDAC_DATA 0x03c9
341cc6ab4e6Schopps #define VDAC_MASK 0x03c6
342cc6ab4e6Schopps
343cc6ab4e6Schopps
344cc6ab4e6Schopps #define WGfx(ba, idx, val) \
345cc6ab4e6Schopps do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0)
346cc6ab4e6Schopps
347cc6ab4e6Schopps #define WSeq(ba, idx, val) \
348cc6ab4e6Schopps do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0)
349cc6ab4e6Schopps
350cc6ab4e6Schopps #define WCrt(ba, idx, val) \
351cc6ab4e6Schopps do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0)
352cc6ab4e6Schopps
353cc6ab4e6Schopps #define WAttr(ba, idx, val) \
354cc6ab4e6Schopps do { \
355cc6ab4e6Schopps unsigned char tmp;\
356cc6ab4e6Schopps tmp = vgar(ba, ACT_ADDRESS_RESET);\
357*e0040f99Schristos __USE(tmp);\
358cc6ab4e6Schopps vgaw(ba, ACT_ADDRESS_W, idx);\
359cc6ab4e6Schopps vgaw(ba, ACT_ADDRESS_W, val);\
360cc6ab4e6Schopps } while (0)
361cc6ab4e6Schopps
362cc6ab4e6Schopps
363cc6ab4e6Schopps #define SetTextPlane(ba, m) \
364cc6ab4e6Schopps do { \
365cc6ab4e6Schopps WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\
366cc6ab4e6Schopps WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\
367cc6ab4e6Schopps } while (0)
368cc6ab4e6Schopps
36918fd2ce9Sveego
37018fd2ce9Sveego /* Gfx engine busy wait */
3713d5f5c73Schristos #ifdef _KERNEL
3725f1c88d7Sperry static inline void
GfxBusyWait(volatile void * ba)37341ba3596Smatt GfxBusyWait (volatile void *ba)
37418fd2ce9Sveego {
37518fd2ce9Sveego int test;
37618fd2ce9Sveego
37718fd2ce9Sveego do {
37818fd2ce9Sveego test = vgar16 (ba, ECR_GP_STAT);
379ae95aa4aSphx amiga_cpu_sync();
38018fd2ce9Sveego } while (test & (1 << 9));
38118fd2ce9Sveego }
38218fd2ce9Sveego
38318fd2ce9Sveego
3845f1c88d7Sperry static inline void
GfxFifoWait(volatile void * ba)38541ba3596Smatt GfxFifoWait(volatile void *ba)
38618fd2ce9Sveego {
38718fd2ce9Sveego int test;
38818fd2ce9Sveego
38918fd2ce9Sveego do {
39018fd2ce9Sveego test = vgar16 (ba, ECR_GP_STAT);
39118fd2ce9Sveego } while (test & 0x0f);
39218fd2ce9Sveego }
39318fd2ce9Sveego
39418fd2ce9Sveego
395cc6ab4e6Schopps /* Special wakeup/passthrough registers on graphics boards
396cc6ab4e6Schopps *
397cc6ab4e6Schopps * The methods have diverged a bit for each board, so
398cc6ab4e6Schopps * WPass(P) has been converted into a set of specific
3995f1c88d7Sperry * inline functions.
400cc6ab4e6Schopps */
401cc6ab4e6Schopps
4025f1c88d7Sperry static inline unsigned char
RAttr(volatile void * ba,short idx)40341ba3596Smatt RAttr(volatile void *ba, short idx)
404cc6ab4e6Schopps {
405cc6ab4e6Schopps
406cc6ab4e6Schopps vgaw(ba, ACT_ADDRESS_W, idx);
407cc6ab4e6Schopps delay(0);
408cc6ab4e6Schopps return vgar(ba, ACT_ADDRESS_R);
409cc6ab4e6Schopps }
410cc6ab4e6Schopps
4115f1c88d7Sperry static inline unsigned char
RSeq(volatile void * ba,short idx)41241ba3596Smatt RSeq(volatile void *ba, short idx)
413cc6ab4e6Schopps {
414cc6ab4e6Schopps vgaw(ba, SEQ_ADDRESS, idx);
415cc6ab4e6Schopps return vgar(ba, SEQ_ADDRESS_R);
416cc6ab4e6Schopps }
417cc6ab4e6Schopps
4185f1c88d7Sperry static inline unsigned char
RCrt(volatile void * ba,short idx)41941ba3596Smatt RCrt(volatile void *ba, short idx)
420cc6ab4e6Schopps {
421cc6ab4e6Schopps vgaw(ba, CRT_ADDRESS, idx);
422cc6ab4e6Schopps return vgar(ba, CRT_ADDRESS_R);
423cc6ab4e6Schopps }
424cc6ab4e6Schopps
4255f1c88d7Sperry static inline unsigned char
RGfx(volatile void * ba,short idx)42641ba3596Smatt RGfx(volatile void *ba, short idx)
427cc6ab4e6Schopps {
428cc6ab4e6Schopps vgaw(ba, GCT_ADDRESS, idx);
429cc6ab4e6Schopps return vgar(ba, GCT_ADDRESS_R);
430cc6ab4e6Schopps }
4313d5f5c73Schristos #endif
432cc6ab4e6Schopps
433de2e89deSphx #endif /* _GRF_CVREG_H */
434