1 /* $NetBSD: grf_cvreg.h,v 1.16 2010/02/09 18:13:10 phx Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Michael Teske 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ezra Story, by Kari 18 * Mettinen and by Bernd Ernesti. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _GRF_CVREG_H 35 #define _GRF_CVREG_H 36 37 #include <machine/cpu.h> 38 39 /* 40 * This is derived from ciruss driver source 41 */ 42 43 /* Extension to grfvideo_mode to support text modes. 44 * This can be passed to both text & gfx functions 45 * without worry. If gv.depth == 4, then the extended 46 * fields for a text mode are present. 47 */ 48 49 struct grfcvtext_mode { 50 struct grfvideo_mode gv; 51 unsigned short fx; /* font x dimension */ 52 unsigned short fy; /* font y dimension */ 53 unsigned short cols; /* screen dimensions */ 54 unsigned short rows; 55 void *fdata; /* font data */ 56 unsigned short fdstart; 57 unsigned short fdend; 58 }; 59 60 /* maximum console size */ 61 #define MAXROWS 200 62 #define MAXCOLS 200 63 64 65 /* read VGA register */ 66 #define vgar(ba, reg) \ 67 (*(((volatile char *)ba)+reg)) 68 69 /* write VGA register */ 70 #define vgaw(ba, reg, val) \ 71 *(((volatile char *)ba)+reg) = ((val) & 0xff); \ 72 amiga_membarrier() 73 74 /* read 32 Bit VGA register */ 75 #define vgar32(ba, reg) \ 76 ( *((volatile unsigned long *) (((volatile char *)ba)+reg)) ) 77 78 /* write 32 Bit VGA register */ 79 #define vgaw32(ba, reg, val) \ 80 *((unsigned long *) (((volatile char *)ba)+reg)) = val; \ 81 amiga_membarrier() 82 83 /* read 16 Bit VGA register */ 84 #define vgar16(ba, reg) \ 85 ( *((volatile unsigned short *) (((volatile char *)ba)+reg)) ) 86 87 /* write 16 Bit VGA register */ 88 #define vgaw16(ba, reg, val) \ 89 *((volatile unsigned short *) (((volatile char *)ba)+reg)) = val; \ 90 amiga_membarrier() 91 92 #ifdef _KERNEL 93 int grfcv_cnprobe(void); 94 void grfcv_iteinit(struct grf_softc *); 95 static inline void GfxBusyWait(volatile void *); 96 static inline void GfxFifoWait(volatile void *); 97 static inline unsigned char RAttr(volatile void *, short); 98 static inline unsigned char RSeq(volatile void *, short); 99 static inline unsigned char RCrt(volatile void *, short); 100 static inline unsigned char RGfx(volatile void *, short); 101 #endif 102 103 104 /* 105 * defines for the used register addresses (mw) 106 * 107 * NOTE: there are some registers that have different addresses when 108 * in mono or color mode. We only support color mode, and thus 109 * some addresses won't work in mono-mode! 110 * 111 * General and VGA-registers taken from retina driver. Fixed a few 112 * bugs in it. (SR and GR read address is Port + 1, NOT Port) 113 * 114 */ 115 116 /* General Registers: */ 117 #define GREG_MISC_OUTPUT_R 0x03CC 118 #define GREG_MISC_OUTPUT_W 0x03C2 119 #define GREG_FEATURE_CONTROL_R 0x03CA 120 #define GREG_FEATURE_CONTROL_W 0x03DA 121 #define GREG_INPUT_STATUS0_R 0x03C2 122 #define GREG_INPUT_STATUS1_R 0x03DA 123 124 /* Setup Registers: */ 125 #define SREG_OPTION_SELECT 0x0102 126 #define SREG_VIDEO_SUBS_ENABLE 0x46E8 127 128 /* Attribute Controller: */ 129 #define ACT_ADDRESS 0x03C0 130 #define ACT_ADDRESS_R 0x03C1 131 #define ACT_ADDRESS_W 0x03C0 132 #define ACT_ADDRESS_RESET 0x03DA 133 #define ACT_ID_PALETTE0 0x00 134 #define ACT_ID_PALETTE1 0x01 135 #define ACT_ID_PALETTE2 0x02 136 #define ACT_ID_PALETTE3 0x03 137 #define ACT_ID_PALETTE4 0x04 138 #define ACT_ID_PALETTE5 0x05 139 #define ACT_ID_PALETTE6 0x06 140 #define ACT_ID_PALETTE7 0x07 141 #define ACT_ID_PALETTE8 0x08 142 #define ACT_ID_PALETTE9 0x09 143 #define ACT_ID_PALETTE10 0x0A 144 #define ACT_ID_PALETTE11 0x0B 145 #define ACT_ID_PALETTE12 0x0C 146 #define ACT_ID_PALETTE13 0x0D 147 #define ACT_ID_PALETTE14 0x0E 148 #define ACT_ID_PALETTE15 0x0F 149 #define ACT_ID_ATTR_MODE_CNTL 0x10 150 #define ACT_ID_OVERSCAN_COLOR 0x11 151 #define ACT_ID_COLOR_PLANE_ENA 0x12 152 #define ACT_ID_HOR_PEL_PANNING 0x13 153 #define ACT_ID_COLOR_SELECT 0x14 154 155 /* Graphics Controller: */ 156 #define GCT_ADDRESS 0x03CE 157 #define GCT_ADDRESS_R 0x03CF 158 #define GCT_ADDRESS_W 0x03CF 159 #define GCT_ID_SET_RESET 0x00 160 #define GCT_ID_ENABLE_SET_RESET 0x01 161 #define GCT_ID_COLOR_COMPARE 0x02 162 #define GCT_ID_DATA_ROTATE 0x03 163 #define GCT_ID_READ_MAP_SELECT 0x04 164 #define GCT_ID_GRAPHICS_MODE 0x05 165 #define GCT_ID_MISC 0x06 166 #define GCT_ID_COLOR_XCARE 0x07 167 #define GCT_ID_BITMASK 0x08 168 169 /* Sequencer: */ 170 #define SEQ_ADDRESS 0x03C4 171 #define SEQ_ADDRESS_R 0x03C5 172 #define SEQ_ADDRESS_W 0x03C5 173 #define SEQ_ID_RESET 0x00 174 #define SEQ_ID_CLOCKING_MODE 0x01 175 #define SEQ_ID_MAP_MASK 0x02 176 #define SEQ_ID_CHAR_MAP_SELECT 0x03 177 #define SEQ_ID_MEMORY_MODE 0x04 178 #define SEQ_ID_UNKNOWN1 0x05 179 #define SEQ_ID_UNKNOWN2 0x06 180 #define SEQ_ID_UNKNOWN3 0x07 181 /* S3 extensions */ 182 #define SEQ_ID_UNLOCK_EXT 0x08 183 #define SEQ_ID_EXT_SEQ_REG9 0x09 184 #define SEQ_ID_BUS_REQ_CNTL 0x0A 185 #define SEQ_ID_EXT_MISC_SEQ 0x0B 186 #define SEQ_ID_UNKNOWN4 0x0C 187 #define SEQ_ID_EXT_SEQ 0x0D 188 #define SEQ_ID_UNKNOWN5 0x0E 189 #define SEQ_ID_UNKNOWN6 0x0F 190 #define SEQ_ID_MCLK_LO 0x10 191 #define SEQ_ID_MCLK_HI 0x11 192 #define SEQ_ID_DCLK_LO 0x12 193 #define SEQ_ID_DCLK_HI 0x13 194 #define SEQ_ID_CLKSYN_CNTL_1 0x14 195 #define SEQ_ID_CLKSYN_CNTL_2 0x15 196 #define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */ 197 #define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */ 198 #define SEQ_ID_RAMDAC_CNTL 0x18 199 #define SEQ_ID_MORE_MAGIC 0x1A 200 201 /* CRT Controller: */ 202 #define CRT_ADDRESS 0x03D4 203 #define CRT_ADDRESS_R 0x03D5 204 #define CRT_ADDRESS_W 0x03D5 205 #define CRT_ID_HOR_TOTAL 0x00 206 #define CRT_ID_HOR_DISP_ENA_END 0x01 207 #define CRT_ID_START_HOR_BLANK 0x02 208 #define CRT_ID_END_HOR_BLANK 0x03 209 #define CRT_ID_START_HOR_RETR 0x04 210 #define CRT_ID_END_HOR_RETR 0x05 211 #define CRT_ID_VER_TOTAL 0x06 212 #define CRT_ID_OVERFLOW 0x07 213 #define CRT_ID_PRESET_ROW_SCAN 0x08 214 #define CRT_ID_MAX_SCAN_LINE 0x09 215 #define CRT_ID_CURSOR_START 0x0A 216 #define CRT_ID_CURSOR_END 0x0B 217 #define CRT_ID_START_ADDR_HIGH 0x0C 218 #define CRT_ID_START_ADDR_LOW 0x0D 219 #define CRT_ID_CURSOR_LOC_HIGH 0x0E 220 #define CRT_ID_CURSOR_LOC_LOW 0x0F 221 #define CRT_ID_START_VER_RETR 0x10 222 #define CRT_ID_END_VER_RETR 0x11 223 #define CRT_ID_VER_DISP_ENA_END 0x12 224 #define CRT_ID_SCREEN_OFFSET 0x13 225 #define CRT_ID_UNDERLINE_LOC 0x14 226 #define CRT_ID_START_VER_BLANK 0x15 227 #define CRT_ID_END_VER_BLANK 0x16 228 #define CRT_ID_MODE_CONTROL 0x17 229 #define CRT_ID_LINE_COMPARE 0x18 230 #define CRT_ID_GD_LATCH_RBACK 0x22 231 #define CRT_ID_ACT_TOGGLE_RBACK 0x24 232 #define CRT_ID_ACT_INDEX_RBACK 0x26 233 /* S3 extensions: S3 VGA Registers */ 234 #define CRT_ID_DEVICE_HIGH 0x2D 235 #define CRT_ID_DEVICE_LOW 0x2E 236 #define CRT_ID_REVISION 0x2F 237 #define CRT_ID_CHIP_ID_REV 0x30 238 #define CRT_ID_MEMORY_CONF 0x31 239 #define CRT_ID_BACKWAD_COMP_1 0x32 240 #define CRT_ID_BACKWAD_COMP_2 0x33 241 #define CRT_ID_BACKWAD_COMP_3 0x34 242 #define CRT_ID_REGISTER_LOCK 0x35 243 #define CRT_ID_CONFIG_1 0x36 244 #define CRT_ID_CONFIG_2 0x37 245 #define CRT_ID_REGISTER_LOCK_1 0x38 246 #define CRT_ID_REGISTER_LOCK_2 0x39 247 #define CRT_ID_MISC_1 0x3A 248 #define CRT_ID_DISPLAY_FIFO 0x3B 249 #define CRT_ID_LACE_RETR_START 0x3C 250 /* S3 extensions: System Control Registers */ 251 #define CRT_ID_SYSTEM_CONFIG 0x40 252 #define CRT_ID_BIOS_FLAG 0x41 253 #define CRT_ID_LACE_CONTROL 0x42 254 #define CRT_ID_EXT_MODE 0x43 255 #define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */ 256 #define CRT_ID_HWGC_ORIGIN_X_HI 0x46 257 #define CRT_ID_HWGC_ORIGIN_X_LO 0x47 258 #define CRT_ID_HWGC_ORIGIN_Y_HI 0x48 259 #define CRT_ID_HWGC_ORIGIN_Y_LO 0x49 260 #define CRT_ID_HWGC_FG_STACK 0x4A 261 #define CRT_ID_HWGC_BG_STACK 0x4B 262 #define CRT_ID_HWGC_START_AD_HI 0x4C 263 #define CRT_ID_HWGC_START_AD_LO 0x4D 264 #define CRT_ID_HWGC_DSTART_X 0x4E 265 #define CRT_ID_HWGC_DSTART_Y 0x4F 266 /* S3 extensions: System Extension Registers */ 267 #define CRT_ID_EXT_SYS_CNTL_1 0x50 268 #define CRT_ID_EXT_SYS_CNTL_2 0x51 269 #define CRT_ID_EXT_BIOS_FLAG_1 0x52 270 #define CRT_ID_EXT_MEM_CNTL_1 0x53 271 #define CRT_ID_EXT_MEM_CNTL_2 0x54 272 #define CRT_ID_EXT_DAC_CNTL 0x55 273 #define CRT_ID_EX_SYNC_1 0x56 274 #define CRT_ID_EX_SYNC_2 0x57 275 #define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */ 276 #define CRT_ID_LAW_POS_HI 0x59 277 #define CRT_ID_LAW_POS_LO 0x5A 278 #define CRT_ID_GOUT_PORT 0x5C 279 #define CRT_ID_EXT_HOR_OVF 0x5D 280 #define CRT_ID_EXT_VER_OVF 0x5E 281 #define CRT_ID_EXT_MEM_CNTL_3 0x60 282 #define CRT_ID_EX_SYNC_3 0x63 283 #define CRT_ID_EXT_MISC_CNTL 0x65 284 #define CRT_ID_EXT_MISC_CNTL_1 0x66 285 #define CRT_ID_EXT_MISC_CNTL_2 0x67 286 #define CRT_ID_CONFIG_3 0x68 287 #define CRT_ID_EXT_SYS_CNTL_3 0x69 288 #define CRT_ID_EXT_SYS_CNTL_4 0x6A 289 #define CRT_ID_EXT_BIOS_FLAG_3 0x6B 290 #define CRT_ID_EXT_BIOS_FLAG_4 0x6C 291 292 /* Enhanced Commands Registers: */ 293 #define ECR_SUBSYSTEM_STAT 0x42E8 294 #define ECR_SUBSYSTEM_CNTL 0x42E8 295 #define ECR_ADV_FUNC_CNTL 0x4AE8 296 #define ECR_CURRENT_Y_POS 0x82E8 297 #define ECR_CURRENT_Y_POS2 0x82EA /* Trio64 only */ 298 #define ECR_CURRENT_X_POS 0x86E8 299 #define ECR_CURRENT_X_POS2 0x86EA /* Trio64 only */ 300 #define ECR_DEST_Y__AX_STEP 0x8AE8 301 #define ECR_DEST_Y2__AX_STEP2 0x8AEA /* Trio64 only */ 302 #define ECR_DEST_X__DIA_STEP 0x8EE8 303 #define ECR_DEST_X2__DIA_STEP2 0x8EEA /* Trio64 only */ 304 #define ECR_ERR_TERM 0x92E8 305 #define ECR_ERR_TERM2 0x92EA /* Trio64 only */ 306 #define ECR_MAJ_AXIS_PIX_CNT 0x96E8 307 #define ECR_MAJ_AXIS_PIX_CNT2 0x96EA /* Trio64 only */ 308 #define ECR_GP_STAT 0x9AE8 /* GP = Graphics Processor */ 309 #define ECR_DRAW_CMD 0x9AE8 310 #define ECR_DRAW_CMD2 0x9AEA /* Trio64 only */ 311 #define ECR_SHORT_STROKE 0x9EE8 312 #define ECR_BKGD_COLOR 0xA2E8 /* BKGD = Background */ 313 #define ECR_FRGD_COLOR 0xA6E8 /* FRGD = Foreground */ 314 #define ECR_BITPLANE_WRITE_MASK 0xAAE8 315 #define ECR_BITPLANE_READ_MASK 0xAEE8 316 #define ECR_COLOR_COMPARE 0xB2E8 317 #define ECR_BKGD_MIX 0xB6E8 318 #define ECR_FRGD_MIX 0xBAE8 319 #define ECR_READ_REG_DATA 0xBEE8 320 #define ECR_ID_MIN_AXIS_PIX_CNT 0x00 321 #define ECR_ID_SCISSORS_TOP 0x01 322 #define ECR_ID_SCISSORS_LEFT 0x02 323 #define ECR_ID_SCISSORS_BUTTOM 0x03 324 #define ECR_ID_SCISSORS_RIGHT 0x04 325 #define ECR_ID_PIX_CNTL 0x0A 326 #define ECR_ID_MULT_CNTL_MISC_2 0x0D 327 #define ECR_ID_MULT_CNTL_MISC 0x0E 328 #define ECR_ID_READ_SEL 0x0F 329 #define ECR_PIX_TRANS 0xE2E8 330 #define ECR_PIX_TRANS_EXT 0xE2EA 331 #define ECR_PATTERN_Y 0xEAE8 /* Trio64 only */ 332 #define ECR_PATTERN_X 0xEAEA /* Trio64 only */ 333 334 335 /* Pass-through */ 336 #define PASS_ADDRESS 0x40001 337 #define PASS_ADDRESS_W 0x40001 338 339 /* Video DAC */ 340 #define VDAC_ADDRESS 0x03c8 341 #define VDAC_ADDRESS_W 0x03c8 342 #define VDAC_ADDRESS_R 0x03c7 343 #define VDAC_STATE 0x03c7 344 #define VDAC_DATA 0x03c9 345 #define VDAC_MASK 0x03c6 346 347 348 #define WGfx(ba, idx, val) \ 349 do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0) 350 351 #define WSeq(ba, idx, val) \ 352 do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0) 353 354 #define WCrt(ba, idx, val) \ 355 do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0) 356 357 #define WAttr(ba, idx, val) \ 358 do { \ 359 unsigned char tmp;\ 360 tmp = vgar(ba, ACT_ADDRESS_RESET);\ 361 vgaw(ba, ACT_ADDRESS_W, idx);\ 362 vgaw(ba, ACT_ADDRESS_W, val);\ 363 } while (0) 364 365 366 #define SetTextPlane(ba, m) \ 367 do { \ 368 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\ 369 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\ 370 } while (0) 371 372 373 /* Gfx engine busy wait */ 374 375 static inline void 376 GfxBusyWait (ba) 377 volatile void *ba; 378 { 379 int test; 380 381 do { 382 test = vgar16 (ba, ECR_GP_STAT); 383 amiga_cpu_sync(); 384 } while (test & (1 << 9)); 385 } 386 387 388 static inline void 389 GfxFifoWait(ba) 390 volatile void *ba; 391 { 392 int test; 393 394 do { 395 test = vgar16 (ba, ECR_GP_STAT); 396 } while (test & 0x0f); 397 } 398 399 400 /* Special wakeup/passthrough registers on graphics boards 401 * 402 * The methods have diverged a bit for each board, so 403 * WPass(P) has been converted into a set of specific 404 * inline functions. 405 */ 406 407 static inline unsigned char 408 RAttr(ba, idx) 409 volatile void *ba; 410 short idx; 411 { 412 413 vgaw(ba, ACT_ADDRESS_W, idx); 414 delay(0); 415 return vgar(ba, ACT_ADDRESS_R); 416 } 417 418 static inline unsigned char 419 RSeq(ba, idx) 420 volatile void *ba; 421 short idx; 422 { 423 vgaw(ba, SEQ_ADDRESS, idx); 424 return vgar(ba, SEQ_ADDRESS_R); 425 } 426 427 static inline unsigned char 428 RCrt(ba, idx) 429 volatile void *ba; 430 short idx; 431 { 432 vgaw(ba, CRT_ADDRESS, idx); 433 return vgar(ba, CRT_ADDRESS_R); 434 } 435 436 static inline unsigned char 437 RGfx(ba, idx) 438 volatile void *ba; 439 short idx; 440 { 441 vgaw(ba, GCT_ADDRESS, idx); 442 return vgar(ba, GCT_ADDRESS_R); 443 } 444 445 #endif /* _GRF_RHREG_H */ 446