1 /* $NetBSD: siopreg.h,v 1.11 2001/03/28 17:33:07 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)siopreg.h 7.3 (Berkeley) 2/5/91 39 */ 40 41 /* 42 * NCR 53C710 SCSI interface hardware description. 43 * 44 * From the Mach scsi driver for the 53C700 45 */ 46 47 typedef struct { 48 49 #ifndef ARCH_720 50 51 /*00*/ volatile unsigned char siop_sien; /* rw: SCSI Interrupt Enable */ 52 /*01*/ volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */ 53 /*02*/ volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */ 54 /*03*/ volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */ 55 56 /*04*/ volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */ 57 /*05*/ volatile unsigned char siop_sodl; /* rw: SCSI Output Data Latch */ 58 /*06*/ volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */ 59 /*07*/ volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */ 60 61 /*08*/ volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */ 62 /*09*/ volatile unsigned char siop_sbdl; /* ro: SCSI Bus Data Lines */ 63 /*0a*/ volatile unsigned char siop_sidl; /* ro: SCSI Input Data Latch */ 64 /*0b*/ volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */ 65 66 /*0c*/ volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */ 67 /*0d*/ volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */ 68 /*0e*/ volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */ 69 /*0f*/ volatile unsigned char siop_dstat; /* ro: DMA status */ 70 71 /*10*/ volatile unsigned long siop_dsa; /* rw: Data Structure Address */ 72 73 /*14*/ volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */ 74 /*15*/ volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */ 75 /*16*/ volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */ 76 /*17*/ volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */ 77 78 /*18*/ volatile unsigned char siop_ctest7; /* rw: Chip test register 7 */ 79 /*19*/ volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */ 80 /*1a*/ volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */ 81 /*1b*/ volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */ 82 83 /*1c*/ volatile unsigned long siop_temp; /* rw: Temporary Stack reg */ 84 85 /*20*/ volatile unsigned char siop_lcrc; /* rw: LCRC value */ 86 /*21*/ volatile unsigned char siop_ctest8; /* rw: Chip test register 8 */ 87 /*22*/ volatile unsigned char siop_istat; /* rw: Interrupt Status reg */ 88 /*23*/ volatile unsigned char siop_dfifo; /* rw: DMA FIFO */ 89 90 /*24*/ volatile unsigned char siop_dcmd; /* rw: DMA Command Register */ 91 /*25*/ volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */ 92 /*26*/ volatile unsigned char siop_dbc1; 93 /*27*/ volatile unsigned char siop_dbc0; 94 95 /*28*/ volatile unsigned long siop_dnad; /* rw: DMA Next Address */ 96 97 /*2c*/ volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */ 98 99 /*30*/ volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */ 100 101 /*34*/ volatile unsigned long siop_scratch; /* rw: Scratch Register */ 102 103 /*38*/ volatile unsigned char siop_dcntl; /* rw: DMA Control reg */ 104 /*39*/ volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */ 105 /*3a*/ volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */ 106 /*3b*/ volatile unsigned char siop_dmode; /* rw: DMA Mode reg */ 107 108 /*3c*/ volatile unsigned long siop_adder; 109 110 #else 111 112 /*00*/ volatile unsigned char siop_scntl3; /* rw: SCSI control reg 3 */ 113 /*01*/ volatile unsigned char siop_scntl2; /* rw: SCSI control reg 2 */ 114 /*02*/ volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */ 115 /*03*/ volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */ 116 117 /*04*/ volatile unsigned char siop_gpreg; /* rw: SCSI */ 118 /*05*/ volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */ 119 /*06*/ volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */ 120 /*07*/ volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */ 121 122 /*08*/ volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */ 123 /*09*/ volatile unsigned char siop_ssid; /* ro: SCSI */ 124 /*0a*/ volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */ 125 /*0b*/ volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */ 126 127 /*0c*/ volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */ 128 /*0d*/ volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */ 129 /*0e*/ volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */ 130 /*0f*/ volatile unsigned char siop_dstat; /* ro: DMA status */ 131 132 /*10*/ volatile unsigned long siop_dsa; /* rw: Data Structure Address */ 133 134 /*14*/ volatile unsigned char siop_14_; /* ??: */ 135 /*15*/ volatile unsigned char siop_15_; /* ??: */ 136 /*16*/ volatile unsigned char siop_16_; /* ??: */ 137 /*17*/ volatile unsigned char siop_istat; /* rw: Interrupt Status reg */ 138 139 /*18*/ volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */ 140 /*19*/ volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */ 141 /*1a*/ volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */ 142 /*1b*/ volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */ 143 144 /*1c*/ volatile unsigned long siop_temp; /* rw: Temporary Stack reg */ 145 146 /*20*/ volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */ 147 /*21*/ volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */ 148 /*22*/ volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */ 149 /*23*/ volatile unsigned char siop_dfifo; /* rw: DMA FIFO */ 150 151 /*24*/ volatile unsigned char siop_dcmd; /* rw: DMA Command Register */ 152 /*25*/ volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */ 153 /*26*/ volatile unsigned char siop_dbc1; 154 /*27*/ volatile unsigned char siop_dbc0; 155 156 /*28*/ volatile unsigned long siop_dnad; /* rw: DMA Next Address */ 157 158 /*2c*/ volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */ 159 160 /*30*/ volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */ 161 162 /*34*/ volatile unsigned long siop_scratcha; /* rw: Scratch Register A */ 163 164 /*38*/ volatile unsigned char siop_dcntl; /* rw: DMA Control reg */ 165 /*39*/ volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */ 166 /*3a*/ volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */ 167 /*3b*/ volatile unsigned char siop_dmode; /* rw: DMA Mode reg */ 168 169 /*3c*/ volatile unsigned long siop_adder; 170 171 /*40*/ volatile unsigned short siop_sist; /* rw: SCSI Interrupt Status */ 172 #define SIOP_SIST_STO 0x0400 /* timeout (select) */ 173 #define SIOP_SIST_GEN 0x0200 /* timeout (general) */ 174 #define SIOP_SIST_HTH 0x0100 /* handshake timer expired */ 175 #define SIOP_SIST_MA 0x0080 /* phase mismatch */ 176 #define SIOP_SIST_CMP 0x0040 /* function complete */ 177 #define SIOP_SIST_SEL 0x0020 /* selected */ 178 #define SIOP_SIST_RSL 0x0010 /* reselected */ 179 #define SIOP_SIST_SGE 0x0008 /* gross error (over/underflow) */ 180 #define SIOP_SIST_UDC 0x0004 /* unexpected disconnect */ 181 #define SIOP_SIST_RST 0x0002 /* RST received */ 182 #define SIOP_SIST_PAR 0x0001 /* scsi parity error */ 183 /*42*/ volatile unsigned short siop_sien; /* rw: SCSI Interrupt Enable */ 184 #define SIOP_SIEN_STO 0x0400 /* timeout (select) */ 185 #define SIOP_SIEN_GEN 0x0200 /* timeout (general) */ 186 #define SIOP_SIEN_HTH 0x0100 /* handshake timer expired */ 187 #define SIOP_SIEN_MA 0x0080 /* phase mispatch */ 188 #define SIOP_SIEN_CMP 0x0040 /* function complete */ 189 #define SIOP_SIEN_SEL 0x0020 /* selected */ 190 #define SIOP_SIEN_RSL 0x0010 /* reselected */ 191 #define SIOP_SIEN_SGE 0x0008 /* gross error (over/underflow) */ 192 #define SIOP_SIEN_UDC 0x0004 /* unexpected disconnect */ 193 #define SIOP_SIEN_RST 0x0002 /* scsi bus reset */ 194 #define SIOP_SIEN_PAR 0x0001 /* scsi parity error */ 195 196 /*44*/ volatile unsigned char siop_gpcntl; /* rw: SCSI */ 197 /*45*/ volatile unsigned char siop_macntl; /* rw: SCSI */ 198 /*46*/ volatile unsigned char siop_swide; /* rw: SCSI */ 199 /*47*/ volatile unsigned char siop_slpar; /* rw: SCSI */ 200 201 /*48*/ volatile unsigned short siop_respid; /* rw: SCSI Reselect-IDS */ 202 /*4a*/ volatile unsigned char siop_stime1; /* rw: SCSI */ 203 /*4b*/ volatile unsigned char siop_stime0; /* rw: SCSI */ 204 205 /*4c*/ volatile unsigned char siop_stest3; /* ro: Chip test register 3 */ 206 #define SIOP_STEST3_HSC 0x20 /* Halt SCSI Clock */ 207 /*4d*/ volatile unsigned char siop_stest2; /* ro: Chip test register 2 */ 208 /*4e*/ volatile unsigned char siop_stest1; /* ro: Chip test register 1 */ 209 #define SIOP_STEST1_DBLEN 0x08 /* SCLK Double Enable */ 210 #define SIOP_STEST1_DBLSEL 0x04 /* SCLK Doubler Select */ 211 /*4f*/ volatile unsigned char siop_stest0; /* ro: Chip test register 0 */ 212 213 /*50*/ volatile unsigned char siop_50_; /* rw: SCSI */ 214 /*51*/ volatile unsigned char siop_stest4; /* rw: SCSI */ 215 /*52*/ volatile unsigned short siop_sidl; /* ro: SCSI Input Data Latch */ 216 217 /*54*/ volatile unsigned short siop_54_; /* rw: SCSI */ 218 /*56*/ volatile unsigned short siop_sodl; /* rw: SCSI Output Data Latch */ 219 220 /*58*/ volatile unsigned short siop_58_; /* rw: SCSI */ 221 /*5a*/ volatile unsigned short siop_sbdl; /* ro: SCSI Bus Data Lines */ 222 223 /*5c*/ volatile unsigned long siop_scratchb; /* rw: Scratch Register B */ 224 #endif 225 226 } siop_regmap_t; 227 typedef volatile siop_regmap_t *siop_regmap_p; 228 229 /* 230 * Register defines 231 */ 232 233 /* Scsi control register 0 (scntl0) */ 234 235 #define SIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */ 236 # define SIOP_ARB_SIMPLE 0x00 237 # define SIOP_ARB_FULL 0xc0 238 #define SIOP_SCNTL0_START 0x20 /* Start Sequence */ 239 #define SIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */ 240 #define SIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */ 241 #define SIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */ 242 #define SIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */ 243 #define SIOP_SCNTL0_TRG 0x01 /* Target Mode */ 244 245 /* Scsi control register 1 (scntl1) */ 246 247 #define SIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */ 248 #define SIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */ 249 #ifndef ARCH_720 250 #define SIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */ 251 #else 252 #define SIOP_SCNTL1_DHP 0x20 /* Disable Halt on Parity or ATN */ 253 #endif 254 #define SIOP_SCNTL1_CON 0x10 /* Connected */ 255 #define SIOP_SCNTL1_RST 0x08 /* Assert RST */ 256 #define SIOP_SCNTL1_AESP 0x04 /* Assert even SCSI parity */ 257 #ifndef ARCH_720 258 #define SIOP_SCNTL1_RES0 0x02 /* Reserved */ 259 #define SIOP_SCNTL1_RES1 0x01 /* Reserved */ 260 #else 261 #define SIOP_SCNTL1_IARB 0x02 /* Immediate Arbitration */ 262 #define SIOP_SCNTL1_SST 0x01 /* Start SCSI Transfer */ 263 #endif 264 265 /* Scsi control register 3 (scntl3) */ 266 267 #ifdef ARCH_720 268 #define SIOP_SCNTL3_ULTRA 0x80 /* Ultra Enable */ 269 #define SIOP_SCNTL3_SCF 0x70 /* Synch Clock Conversion Factor */ 270 #define SIOP_SCNTL3_EWS 0x08 /* Enable Wide SCSI */ 271 #define SIOP_SCNTL3_CCF 0x07 /* Clock Conversion Factor */ 272 #endif 273 274 /* Scsi interrupt enable register (sien) */ 275 276 #ifndef ARCH_720 277 #define SIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */ 278 #define SIOP_SIEN_FCMP 0x40 /* Function Complete */ 279 #define SIOP_SIEN_STO 0x20 /* (Re)Selection timeout */ 280 #define SIOP_SIEN_SEL 0x10 /* (Re)Selected */ 281 #define SIOP_SIEN_SGE 0x08 /* SCSI Gross Error */ 282 #define SIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */ 283 #define SIOP_SIEN_RST 0x02 /* RST asserted */ 284 #define SIOP_SIEN_PAR 0x01 /* Parity Error */ 285 #endif 286 287 /* Scsi chip ID (scid) */ 288 289 #define SIOP_SCID_VALUE(i) (1<<i) 290 #ifdef ARCH_720 291 #define SIOP_SCID_RRE 0x40 /* Enable Response to Reselection */ 292 #define SIOP_SCID_SRE 0x20 /* Enable Response to Selection */ 293 #endif 294 295 /* Scsi transfer register (sxfer) */ 296 297 #ifndef ARCH_720 298 #define SIOP_SXFER_DHP 0x80 /* Disable Halt on Parity error/ ATN asserted */ 299 #define SIOP_SXFER_TP 0x70 /* Synch Transfer Period */ 300 /* see specs for formulas: 301 Period = TCP * (4 + XFERP ) 302 TCP = 1 + CLK + 1..2; 303 */ 304 #define SIOP_SXFER_MO 0x0f /* Synch Max Offset */ 305 # define SIOP_MAX_OFFSET 8 306 #else 307 #define SIOP_SXFER_TP 0xe0 /* Synch Transfer Period */ 308 /* see specs for formulas: 309 Period = TCP * (4 + XFERP ) 310 TCP = 1 + CLK + 1..2; 311 */ 312 #define SIOP_SXFER_MO 0x1f /* Synch Max Offset */ 313 # define SIOP_MAX_OFFSET 16 314 #endif 315 316 /* Scsi output data latch register (sodl) */ 317 318 /* Scsi output control latch register (socl) */ 319 320 #define SIOP_REQ 0x80 /* SCSI signal <x> asserted */ 321 #define SIOP_ACK 0x40 322 #define SIOP_BSY 0x20 323 #define SIOP_SEL 0x10 324 #define SIOP_ATN 0x08 325 #define SIOP_MSG 0x04 326 #define SIOP_CD 0x02 327 #define SIOP_IO 0x01 328 329 #define SIOP_PHASE(socl) SCSI_PHASE(socl) 330 331 /* Scsi first byte received register (sfbr) */ 332 333 /* Scsi input data latch register (sidl) */ 334 335 /* Scsi bus data lines register (sbdl) */ 336 337 /* Scsi bus control lines register (sbcl). Same as socl */ 338 339 /* DMA status register (dstat) */ 340 341 #define SIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */ 342 #ifndef ARCH_720 343 #define SIOP_DSTAT_RES 0x40 344 #else 345 #define SIOP_DSTAT_HPE 0x40 /* Host Parity Error */ 346 #endif 347 #define SIOP_DSTAT_BF 0x20 /* Bus fault */ 348 #define SIOP_DSTAT_ABRT 0x10 /* Aborted */ 349 #define SIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */ 350 #define SIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */ 351 #define SIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */ 352 #define SIOP_DSTAT_IID 0x01 /* Invalid Instruction Detected */ 353 354 /* Scsi status register 0 (sstat0) */ 355 356 #ifndef ARCH_720 357 #define SIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */ 358 #define SIOP_SSTAT0_FCMP 0x40 /* Function Complete */ 359 #define SIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */ 360 #define SIOP_SSTAT0_SEL 0x10 /* (Re)Selected */ 361 #define SIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */ 362 #define SIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */ 363 #define SIOP_SSTAT0_RST 0x02 /* RST asserted */ 364 #define SIOP_SSTAT0_PAR 0x01 /* Parity Error */ 365 #else 366 #define SIOP_SSTAT0_ILF 0x80 /* SIDL lsb full */ 367 #define SIOP_SSTAT0_ORF 0x40 /* SODR lsb full */ 368 #define SIOP_SSTAT0_OLF 0x20 /* SODL lsb full */ 369 #define SIOP_SSTAT0_AIP 0x10 /* Arbitration in progress */ 370 #define SIOP_SSTAT0_LOA 0x08 /* Lost Arbitration */ 371 #define SIOP_SSTAT0_WOA 0x04 /* Won Arbitration */ 372 #define SIOP_SSTAT0_RST 0x02 /* SCSI RST/ signal */ 373 #define SIOP_SSTAT0_SDP0 0x01 /* SCSI SDP0/ parity signal */ 374 #endif 375 376 /* Scsi status register 1 (sstat1) */ 377 378 #ifndef ARCH_720 379 #define SIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */ 380 #define SIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */ 381 #define SIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */ 382 #define SIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */ 383 #define SIOP_SSTAT1_LOA 0x08 /* Lost arbitration */ 384 #define SIOP_SSTAT1_WOA 0x04 /* Won arbitration */ 385 #define SIOP_SSTAT1_RST 0x02 /* SCSI RST current value */ 386 #define SIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */ 387 #else 388 #define SIOP_SSTAT1_FF 0xf0 /* SCSI FIFO flags (bytecount) */ 389 #define SIOP_SSTAT1_SDP0 0x08 /* Latched (on REQ) SCSI Parity */ 390 #define SIOP_SSTAT1_MSG 0x04 /* Latched SCSI phase */ 391 #define SIOP_SSTAT1_CD 0x02 392 #define SIOP_SSTAT1_IO 0x01 393 #endif 394 395 /* Scsi status register 2 (sstat2) */ 396 397 #ifndef ARCH_720 398 #define SIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */ 399 # define SIOP_SCSI_FIFO_DEEP 8 400 #define SIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */ 401 #define SIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */ 402 #define SIOP_SSTAT2_CD 0x02 403 #define SIOP_SSTAT2_IO 0x01 404 #else 405 #define SIOP_SSTAT2_ILF1 0x80 /* SIDL msb full */ 406 #define SIOP_SSTAT2_ORF1 0x40 /* SODR msb full */ 407 #define SIOP_SSTAT2_OLF1 0x20 /* SODL msb full */ 408 #define SIOP_SSTAT2_FF4 0x10 /* FIFO flags bit 4 */ 409 #define SIOP_SSTAT2_SPL1 0x08 /* Latched Parity for SD15-8 */ 410 #define SIOP_SSTAT2_DIFF 0x04 /* DIFFSENSE Sense */ 411 #define SIOP_SSTAT2_LDSC 0x02 /* Last Disconnect */ 412 #define SIOP_SSTAT2_SDP1 0x01 /* SCSI SDP1 Parity */ 413 #endif 414 415 /* Chip test register 0 (ctest0) */ 416 417 #ifndef ARCH_720 418 #define SIOP_CTEST0_RES0 0x80 419 #define SIOP_CTEST0_BTD 0x40 /* Byte-to-byte Timer Disable */ 420 #define SIOP_CTEST0_GRP 0x20 /* Generate Receive Parity for Passthrough */ 421 #define SIOP_CTEST0_EAN 0x10 /* Enable Active Negation */ 422 #define SIOP_CTEST0_HSC 0x08 /* Halt SCSI clock */ 423 #define SIOP_CTEST0_ERF 0x04 /* Extend REQ/ACK Filtering */ 424 #define SIOP_CTEST0_RES1 0x02 425 #define SIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */ 426 #endif 427 428 /* Chip test register 1 (ctest1) */ 429 430 #define SIOP_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom (high->byte3) */ 431 #define SIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */ 432 433 /* Chip test register 2 (ctest2) */ 434 435 #ifndef ARCH_720 436 #define SIOP_CTEST2_RES 0x80 437 #else 438 #define SIOP_CTETS2_DDIR 0x80 /* Data Transfer Direction */ 439 #endif 440 #define SIOP_CTEST2_SIGP 0x40 /* Signal process */ 441 #ifndef ARCH_720 442 #define SIOP_CTEST2_SOFF 0x20 /* Synch Offset compare (1-> zero Init, max Tgt */ 443 #define SIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */ 444 #else 445 #define SIOP_CTEST2_RES5 0x20 446 #define SIOP_CTEST2_RES4 0x10 447 #endif 448 #define SIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */ 449 #define SIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */ 450 #define SIOP_CTEST2_DREQ 0x02 /* DREQ status */ 451 #define SIOP_CTEST2_DACK 0x01 /* DACK status */ 452 453 /* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */ 454 455 #ifdef ARCH_720 456 #define SIOP_CTEST3_V 0xf0 /* Chip revision level */ 457 #define SIOP_CTEST3_FLF 0x08 /* Flush DMA FIFO */ 458 #define SIOP_CTEST3_CLF 0x04 /* Clear DMA FIFO */ 459 #define SIOP_CTEST3_FM 0x02 /* Fetch pin mode */ 460 #define SIOP_CTEST3_SM 0x01 /* Snoop pins mode */ 461 #endif 462 463 /* Chip test register 4 (ctest4) */ 464 465 #define SIOP_CTEST4_MUX 0x80 /* Host bus multiplex mode */ 466 #define SIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */ 467 #define SIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */ 468 #ifndef ARCH_720 469 #define SIOP_CTEST4_SLBE 0x10 /* SCSI loobpack enable */ 470 #define SIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */ 471 #else 472 #define SIOP_CTEST4_SRTM 0x10 /* Shadow Register Test Mode */ 473 #define SIOP_CTEST4_EHPC 0x08 /* Enable Host Parity Check */ 474 #endif 475 #define SIOP_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select (from ctest6) 476 4->0, .. 7->3 */ 477 478 /* Chip test register 5 (ctest5) */ 479 480 #define SIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */ 481 #define SIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */ 482 #ifndef ARCH_720 483 #define SIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */ 484 #else 485 #define SIOP_CTEST5_RES 0x20 486 #endif 487 #define SIOP_CTEST5_MASR 0x10 /* Master set/reset pulses (of bits 3-0) */ 488 #define SIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */ 489 #ifndef ARCH_720 490 #define SIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */ 491 #define SIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */ 492 #define SIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */ 493 #else 494 #define SIOP_CTEST5_RAM 0x06 /* SCRIPTS RAM 1-0 */ 495 #define SIOP_CTEST5 RAMEN 0x01 /* RAM Base Address Enable */ 496 #endif 497 498 /* Chip test register 6 (ctest6) DMA FIFO access */ 499 500 /* Chip test register 7 (ctest7) */ 501 502 #ifndef ARCH_720 503 #define SIOP_CTEST7_CDIS 0x80 /* Cache burst disable */ 504 #define SIOP_CTEST7_SC1 0x40 /* Snoop control 1 */ 505 #define SIOP_CTEST7_SC0 0x20 /* Snoop contorl 0 */ 506 #define SIOP_CTEST7_STD 0x10 /* Selection timeout disable */ 507 #define SIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */ 508 #define SIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */ 509 #define SIOP_CTEST7_TT1 0x02 /* Transfer type bit */ 510 #define SIOP_CTEST7_DIFF 0x01 /* Differential mode */ 511 #endif 512 513 /* DMA FIFO register (dfifo) */ 514 515 #define SIOP_DFIFO_RES 0x80 516 #define SIOP_DFIFO_BO 0x7f /* FIFO byte offset counter */ 517 518 /* Interrupt status register (istat) */ 519 520 #define SIOP_ISTAT_ABRT 0x80 /* Abort operation */ 521 #define SIOP_ISTAT_RST 0x40 /* Software reset */ 522 #define SIOP_ISTAT_SIGP 0x20 /* Signal process */ 523 #ifndef ARCH_720 524 #define SIOP_ISTAT_RES 0x10 525 #else 526 #define SIOP_ISTAT_SEM 0x10 /* Semaphore */ 527 #endif 528 #define SIOP_ISTAT_CON 0x08 /* Connected */ 529 #ifndef ARCH_720 530 #define SIOP_ISTAT_RES1 0x04 531 #else 532 #define SIOP_ISTAT_INTF 0x04 /* Interrupt on the Fly */ 533 #endif 534 #define SIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */ 535 #define SIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */ 536 537 /* Chip test register 8 (ctest8) */ 538 539 #define SIOP_CTEST8_V 0xf0 /* Chip revision level */ 540 #define SIOP_CTEST8_FLF 0x08 /* Flush DMA FIFO */ 541 #define SIOP_CTEST8_CLF 0x04 /* Clear DMA and SCSI FIFOs */ 542 #define SIOP_CTEST8_FM 0x02 /* Fetch pin mode */ 543 #define SIOP_CTEST8_SM 0x01 /* Snoop pins mode */ 544 545 /* DMA Mode register (dmode) */ 546 547 #define SIOP_DMODE_BL_MASK 0xc0 /* 0->1 1->2 2->4 3->8 */ 548 #define SIOP_DMODE_FC 0x30 /* Function code */ 549 #define SIOP_DMODE_PD 0x08 /* Program/data */ 550 #define SIOP_DMODE_FAM 0x04 /* Fixed address mode */ 551 #define SIOP_DMODE_U0 0x02 /* User programmable transfer type */ 552 #define SIOP_DMODE_MAN 0x01 /* Manual start mode */ 553 554 /* DMA interrupt enable register (dien) */ 555 556 #define SIOP_DIEN_RES 0xc0 557 #ifdef ARCH_720 558 #define SIOP_DIEN_HPED 0x40 /* Host Parity */ 559 #endif 560 #define SIOP_DIEN_BF 0x20 /* On Bus Fault */ 561 #define SIOP_DIEN_ABRT 0x10 /* On Abort */ 562 #define SIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */ 563 #define SIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */ 564 #define SIOP_DIEN_WTD 0x02 /* On watchdog timeout */ 565 #define SIOP_DIEN_IID 0x01 /* On illegal instruction detected */ 566 567 /* DMA control register (dcntl) */ 568 569 #ifndef ARCH_720 570 #define SIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers: 571 0 --> 37.51..50.00 Mhz, div=2 572 1 --> 25.01..37.50 Mhz, div=1.5 573 2 --> 16.67..25.00 Mhz, div=1 574 3 --> 50.01..66.67 Mhz, div=3 575 */ 576 #else 577 #define SIOP_DCNTL_STE 0x80 /* Size Throttle Enable */ 578 #define SIOP_DCNTL_BSM 0x40 /* Bus Mode */ 579 #endif 580 #define SIOP_DCNTL_EA 0x20 /* Enable ack */ 581 #define SIOP_DCNTL_SSM 0x10 /* Single step mode */ 582 #ifndef ARCH_720 583 #define SIOP_DCNTL_LLM 0x08 /* Enable SCSI Low-level mode */ 584 #else 585 #define SIOP_DCNTL_BW16 0x8 /* Bus Width 16 */ 586 #endif 587 #define SIOP_DCNTL_STD 0x04 /* Start DMA operation */ 588 #define SIOP_DCNTL_FA 0x02 /* Fast arbitration */ 589 #define SIOP_DCNTL_COM 0x01 /* 53C700 compatibility */ 590