1 /* $NetBSD: c_magnum.c,v 1.1 2001/06/13 15:19:28 soda Exp $ */ 2 /* $OpenBSD: machdep.c,v 1.36 1999/05/22 21:22:19 weingart Exp $ */ 3 4 /* 5 * Copyright (c) 1988 University of Utah. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department, The Mach Operating System project at 12 * Carnegie-Mellon University and Ralph Campbell. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by the University of 25 * California, Berkeley and its contributors. 26 * 4. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94 43 */ 44 45 /* 46 * for Magnum derived machines like Microsoft-Jazz and PICA-61. 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <uvm/uvm_extern.h> 53 54 #include <machine/autoconf.h> 55 #include <machine/bus.h> 56 #include <machine/pio.h> 57 #include <machine/platform.h> 58 #include <mips/pte.h> 59 60 #include <dev/isa/isavar.h> 61 62 #include <arc/arc/wired_map.h> 63 #include <arc/dev/mcclockvar.h> 64 #include <arc/jazz/pica.h> 65 #include <arc/jazz/jazziovar.h> 66 #include <arc/jazz/mcclock_jazziovar.h> 67 #include <arc/jazz/timer_jazziovar.h> 68 #include <arc/isa/isabrvar.h> 69 70 extern int cpu_int_mask; 71 72 /* 73 * chipset-dependent mcclock routines. 74 */ 75 76 u_int mc_magnum_read __P((struct mcclock_softc *, u_int)); 77 void mc_magnum_write __P((struct mcclock_softc *, u_int, u_int)); 78 79 struct mcclock_jazzio_config mcclock_magnum_conf = { 80 0x80004000, 1, 81 { mc_magnum_read, mc_magnum_write } 82 }; 83 84 u_int 85 mc_magnum_read(sc, reg) 86 struct mcclock_softc *sc; 87 u_int reg; 88 { 89 int i, as; 90 91 as = in32(PICA_SYS_ISA_AS) & 0x80; 92 out32(PICA_SYS_ISA_AS, as | reg); 93 i = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 0); 94 return (i); 95 } 96 97 void 98 mc_magnum_write(sc, reg, datum) 99 struct mcclock_softc *sc; 100 u_int reg, datum; 101 { 102 int as; 103 104 as = in32(PICA_SYS_ISA_AS) & 0x80; 105 out32(PICA_SYS_ISA_AS, as | reg); 106 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 0, datum); 107 } 108 109 /* 110 * chipset-dependent timer routine. 111 */ 112 113 int timer_magnum_intr __P((u_int, struct clockframe *)); 114 void timer_magnum_init(int); 115 116 struct timer_jazzio_config timer_magnum_conf = { 117 MIPS_INT_MASK_4, 118 timer_magnum_intr, 119 timer_magnum_init, 120 }; 121 122 int 123 timer_magnum_intr(mask, cf) 124 u_int mask; 125 struct clockframe *cf; 126 { 127 int temp; 128 129 temp = inw(R4030_SYS_IT_STAT); 130 hardclock(cf); 131 132 /* Re-enable clock interrupts */ 133 splx(MIPS_INT_MASK_4 | MIPS_SR_INT_IE); 134 135 return (~MIPS_INT_MASK_4); /* Keep clock interrupts enabled */ 136 } 137 138 void 139 timer_magnum_init(interval) 140 int interval; /* milliseconds */ 141 { 142 if (interval <= 0) 143 panic("timer_nec_jazz_init: invalid interval %d", interval); 144 145 out32(R4030_SYS_IT_VALUE, interval - 1); 146 147 /* Enable periodic clock interrupt */ 148 out32(R4030_SYS_EXT_IMASK, cpu_int_mask); 149 } 150 151 /* 152 * chipset-dependent isa bus configuration 153 */ 154 155 int isabr_magnum_intr_status __P((void)); 156 157 struct isabr_config isabr_magnum_conf = { 158 isabr_magnum_intr_status, 159 }; 160 161 int 162 isabr_magnum_intr_status() 163 { 164 return (in32(R4030_SYS_ISA_VECTOR) & (ICU_LEN - 1)); 165 } 166 167 /* 168 * chipset-dependent jazzio bus configuration 169 */ 170 171 void jazzio_magnum_set_iointr_mask __P((int)); 172 173 struct jazzio_config jazzio_magnum_conf = { 174 PVIS, 175 jazzio_magnum_set_iointr_mask, 176 R4030_SYS_TL_BASE, 177 R4030_SYS_DMA1_REGS, 178 }; 179 180 void 181 jazzio_magnum_set_iointr_mask(mask) 182 int mask; 183 { 184 out16(PICA_SYS_LB_IE, mask); 185 } 186 187 /* 188 * chipset-dependent platform routines. 189 */ 190 191 void 192 c_magnum_set_intr(mask, int_hand, prio) 193 int mask; 194 int (*int_hand)(u_int, struct clockframe *); 195 int prio; 196 { 197 arc_set_intr(mask, int_hand, prio); 198 199 /* Update external interrupt mask but don't enable clock. */ 200 out32(R4030_SYS_EXT_IMASK, cpu_int_mask & (~MIPS_INT_MASK_4 >> 10)); 201 } 202 203 /* 204 * critial i/o space, interrupt, and other chipset related initialization. 205 */ 206 void 207 c_magnum_init() 208 { 209 /* 210 * Initialize I/O address offset 211 */ 212 arc_bus_space_init(&jazzio_bus, "jazzio", 213 R4030_P_LOCAL_IO_BASE, R4030_V_LOCAL_IO_BASE, 214 R4030_V_LOCAL_IO_BASE, R4030_S_LOCAL_IO_BASE); 215 arc_bus_space_init(&arc_bus_io, "picaisaio", 216 PICA_P_ISA_IO, PICA_V_ISA_IO, 0, PICA_S_ISA_IO); 217 arc_bus_space_init(&arc_bus_mem, "picaisamem", 218 PICA_P_ISA_MEM, PICA_V_ISA_MEM, 0, PICA_S_ISA_MEM); 219 220 /* 221 * Initialize wired TLB for I/O space which is used on early stage 222 */ 223 arc_enter_wired(R4030_V_LOCAL_IO_BASE, R4030_P_LOCAL_IO_BASE, 224 PICA_P_INT_SOURCE, MIPS3_PG_SIZE_256K); 225 arc_enter_wired(PICA_V_ISA_IO, PICA_P_ISA_IO, PICA_P_ISA_MEM, 226 MIPS3_PG_SIZE_16M); 227 228 /* 229 * Initialize interrupt priority 230 */ 231 splvec.splnet = MIPS_INT_MASK_SPL3; 232 splvec.splbio = MIPS_INT_MASK_SPL3; 233 splvec.splvm = MIPS_INT_MASK_SPL3; 234 splvec.spltty = MIPS_INT_MASK_SPL3; 235 splvec.splclock = MIPS_INT_MASK_SPL5; 236 splvec.splstatclock = MIPS_INT_MASK_SPL5; 237 238 /* 239 * Disable all interrupts. New masks will be set up 240 * during system configuration 241 */ 242 out16(PICA_SYS_LB_IE,0x000); 243 out32(R4030_SYS_EXT_IMASK, 0x00); 244 245 /* common configuration for Magnum derived and NEC EISA machines */ 246 c_jazz_eisa_init(); 247 248 /* chipset-dependent mcclock configuration */ 249 mcclock_jazzio_conf = &mcclock_magnum_conf; 250 251 /* chipset-dependent timer configuration */ 252 timer_jazzio_conf = &timer_magnum_conf; 253 254 /* chipset-dependent jazzio bus configuration */ 255 jazzio_conf = &jazzio_magnum_conf; 256 257 /* chipset-dependent isa bus configuration */ 258 isabr_conf = &isabr_magnum_conf; 259 } 260