1 /* $NetBSD: c_nec_eisa.c,v 1.15 2008/05/14 13:29:27 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 Izumi Tsutsui. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (C) 2000 Shuichiro URATA. All rights reserved. 29 * 30 * Redistribution and use in source and binary forms, with or without 31 * modification, are permitted provided that the following conditions 32 * are met: 33 * 1. Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * 2. Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in the 37 * documentation and/or other materials provided with the distribution. 38 * 3. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * for NEC EISA generation machines. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: c_nec_eisa.c,v 1.15 2008/05/14 13:29:27 tsutsui Exp $"); 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/kcore.h> 63 #include <sys/device.h> 64 #include <uvm/uvm_extern.h> 65 66 #include <machine/autoconf.h> 67 #include <machine/pio.h> 68 #include <machine/platform.h> 69 #include <machine/wired_map.h> 70 #include <mips/pte.h> 71 72 #include <dev/isa/isavar.h> 73 74 #include <arc/arc/arcbios.h> 75 #include <arc/jazz/pica.h> 76 #include <arc/jazz/rd94.h> 77 #include <arc/jazz/jazziovar.h> 78 #include <arc/isa/isabrvar.h> 79 80 #include "vga_isa.h" 81 #if NVGA_ISA > 0 82 #include <dev/ic/mc6845reg.h> 83 #include <dev/ic/pcdisplayvar.h> 84 #include <dev/ic/vgareg.h> 85 #include <dev/ic/vgavar.h> 86 87 #ifdef VGA_RESET 88 static void gd54xx_initregs(struct vga_handle *); 89 #endif 90 #endif 91 92 /* 93 * chipset-dependent isa bus configuration 94 */ 95 96 int isabr_nec_eisa_intr_status(void); 97 98 struct isabr_config isabr_nec_eisa_conf = { 99 isabr_nec_eisa_intr_status, 100 }; 101 102 /* 103 * This is a mask of bits to clear in the SR when we go to a 104 * given interrupt priority level. 105 */ 106 static const uint32_t nec_eisa_ipl_sr_bits[_IPL_N] = { 107 [IPL_NONE] = 0, 108 [IPL_SOFTCLOCK] = 109 MIPS_SOFT_INT_MASK_0, 110 [IPL_SOFTNET] = 111 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1, 112 [IPL_VM] = 113 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | 114 MIPS_INT_MASK_0 | 115 MIPS_INT_MASK_1 | 116 MIPS_INT_MASK_2, 117 [IPL_SCHED] = 118 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | 119 MIPS_INT_MASK_0 | 120 MIPS_INT_MASK_1 | 121 MIPS_INT_MASK_2 | 122 MIPS_INT_MASK_3 | 123 MIPS_INT_MASK_4 | 124 MIPS_INT_MASK_5, 125 }; 126 127 int 128 isabr_nec_eisa_intr_status(void) 129 { 130 131 return in32(RD94_SYS_INTSTAT2) & (ICU_LEN - 1); 132 } 133 134 /* 135 * chipset-dependent jazzio bus configuration 136 */ 137 138 void jazzio_nec_eisa_set_iointr_mask(int); 139 140 struct jazzio_config jazzio_nec_eisa_conf = { 141 RD94_SYS_INTSTAT1, 142 jazzio_nec_eisa_set_iointr_mask, 143 RD94_SYS_TL_BASE, 144 RD94_SYS_DMA0_REGS, 145 }; 146 147 void 148 jazzio_nec_eisa_set_iointr_mask(int mask) 149 { 150 151 out16(RD94_SYS_LB_IE2, mask); 152 } 153 154 /* 155 * critial i/o space, interrupt, and other chipset related initialization. 156 */ 157 void 158 c_nec_eisa_init(void) 159 { 160 161 /* 162 * Initialize interrupt priority 163 */ 164 ipl_sr_bits = nec_eisa_ipl_sr_bits; 165 166 /* 167 * Initialize I/O address offset 168 */ 169 arc_bus_space_init(&jazzio_bus, "jazzio", 170 RD94_P_LOCAL_IO_BASE, RD94_V_LOCAL_IO_BASE, 171 RD94_V_LOCAL_IO_BASE, RD94_S_LOCAL_IO_BASE); 172 173 arc_bus_space_init(&arc_bus_io, "r94eisaio", 174 RD94_P_PCI_IO, RD94_V_EISA_IO, 0, RD94_S_EISA_IO); 175 arc_bus_space_init(&arc_bus_mem, "r94eisamem", 176 RD94_P_PCI_MEM, RD94_V_EISA_MEM, 0, RD94_S_EISA_MEM); 177 178 /* 179 * Initialize wired TLB for I/O space which is used on early stage 180 */ 181 arc_init_wired_map(); 182 arc_wired_enter_page(RD94_V_LOCAL_IO_BASE, RD94_P_LOCAL_IO_BASE, 183 RD94_S_LOCAL_IO_BASE); 184 185 arc_wired_enter_page(RD94_V_EISA_IO, RD94_P_EISA_IO, RD94_S_EISA_IO); 186 arc_wired_enter_page(RD94_V_EISA_MEM, RD94_P_EISA_MEM, 187 MIPS3_PG_SIZE_MASK_TO_SIZE(MIPS3_PG_SIZE_16M)); 188 189 /* 190 * Disable all interrupts. New masks will be set up 191 * during system configuration 192 */ 193 out16(RD94_SYS_LB_IE1, 0); 194 out16(RD94_SYS_LB_IE2, 0); 195 out32(RD94_SYS_EXT_IMASK, 0); 196 197 /* 198 * common configuration between NEC EISA and PCI platforms 199 */ 200 c_nec_jazz_init(); 201 202 /* common configuration for Magnum derived and NEC EISA machines */ 203 c_jazz_eisa_init(); 204 205 /* chipset-dependent isa bus configuration */ 206 isabr_conf = &isabr_nec_eisa_conf; 207 208 /* chipset-dependent jazzio bus configuration */ 209 jazzio_conf = &jazzio_nec_eisa_conf; 210 } 211 212 void 213 c_nec_eisa_cons_init(void) 214 { 215 216 #if NVGA_ISA > 0 217 if (!com_console) { 218 if (strcmp(arc_displayc_id, "necvdfrb") == 0) { 219 /* NEC RISCserver 2200 R4400 EISA [NEC-R96] */ 220 /* NEC Express5800/240 R4400 EISA [NEC-J96A] */ 221 #ifdef VGA_RESET 222 struct vga_handle handle; 223 224 handle.vh_memt = &arc_bus_mem; 225 handle.vh_iot = &arc_bus_io; 226 vga_reset(&handle, gd54xx_initregs); 227 #endif 228 229 vga_no_builtinfont = 1; 230 } 231 } 232 #endif 233 234 c_jazz_eisa_cons_init(); 235 } 236 237 #if NVGA_ISA > 0 && defined(VGA_RESET) 238 239 /* values to intialize cirrus GD54xx specific ext registers */ 240 /* XXX these values are taken from PC XXX */ 241 static const uint8_t vga_ts_gd54xx[] = { 242 0x0f, /* 05: ??? */ 243 0x12, /* 06: enable ext reg (?) */ 244 0x00, /* 07: reset ext sequence (?) */ 245 0x00, /* 08: ??? */ 246 0x5c, /* 09: ??? */ 247 0x09, /* 0A: BIOS Scratch register for 542x (?) */ 248 0x4a, /* 0B: ??? */ 249 0x5b, /* 0C: ??? */ 250 0x42, /* 0D: VCLK2 frequency */ 251 0x00, /* 0E: VCLK3 frequency */ 252 0x09, /* 0F: ??? */ 253 0x00, /* 10: ??? */ 254 0x00, /* 11: ??? */ 255 0x00, /* 12: ??? */ 256 0x00, /* 13: ??? */ 257 0x00, /* 14: BIOS scratch register for 546x (?) */ 258 0x00, /* 15: ??? */ 259 0xd8, /* 16: ??? */ 260 0x39, /* 17: ??? */ 261 0x00, /* 18: ??? */ 262 0x01, /* 19: ??? */ 263 0x00, /* 1A: ??? */ 264 0x2b, /* 1B: ??? */ 265 0x2f, /* 1C: ??? */ 266 0x1f, /* 1D: VCLK2 denominator and post-scalar value */ 267 0x00, /* 1E: VCLK3 denominator and post-scalar value */ 268 0x19 /* 1F: MCLK (?) */ 269 }; 270 271 static void 272 gd54xx_initregs(struct vga_handle *vh) 273 { 274 int i; 275 276 /* disable video */ 277 vga_ts_write(vh, mode, vga_ts_read(vh, mode) | VGA_TS_MODE_BLANK); 278 279 /* enable access to GD54xx ext regs */ 280 _vga_ts_write(vh, 0x06, 0x12); 281 282 /* setup GD54xx ext regs */ 283 for (i = 0; i < sizeof(vga_ts_gd54xx); i++) 284 _vga_ts_write(vh, VGA_TS_NREGS + i, vga_ts_gd54xx[i]); 285 286 /* disable access to GD54xx ext regs */ 287 _vga_ts_write(vh, 0x06, 0x0); 288 289 /* reenable video */ 290 vga_ts_write(vh, mode, vga_ts_read(vh, mode) & ~VGA_TS_MODE_BLANK); 291 } 292 #endif 293