1 /* $NetBSD: c_nec_pci.c,v 1.17 2007/12/03 15:33:13 ad Exp $ */ 2 3 /*- 4 * Copyright (C) 2000 Shuichiro URATA. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * for NEC PCI generation machines. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: c_nec_pci.c,v 1.17 2007/12/03 15:33:13 ad Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kcore.h> 39 #include <sys/device.h> 40 #include <uvm/uvm_extern.h> 41 42 #include <machine/autoconf.h> 43 #include <machine/bus.h> 44 #include <machine/pio.h> 45 #include <machine/platform.h> 46 #include <machine/wired_map.h> 47 #include <mips/pte.h> 48 49 #include <dev/clock_subr.h> 50 #include <dev/ic/mc146818var.h> 51 52 #include <dev/pci/pcivar.h> 53 54 #include <arc/arc/arcbios.h> 55 #include <arc/jazz/pica.h> 56 #include <arc/jazz/rd94.h> 57 #include <arc/jazz/jazziovar.h> 58 #include <arc/jazz/mcclock_jazziovar.h> 59 #include <arc/pci/necpbvar.h> 60 61 #include "tga.h" 62 #if NTGA > 0 63 #include <dev/pci/tgavar.h> 64 #endif 65 66 #include "vga_pci.h" 67 #if NVGA_PCI > 0 68 #include <dev/pci/vga_pcivar.h> 69 #endif 70 71 #include "rasdisplay_jazzio.h" 72 #if NRASDISPLAY_JAZZIO > 0 73 #include <arc/jazz/rasdisplay_jazziovar.h> 74 #endif 75 76 #include "pckbc_jazzio.h" 77 #if NPCKBC_JAZZIO > 0 78 #include <dev/ic/pckbcvar.h> 79 #include <arc/jazz/pckbc_jazzioreg.h> 80 #endif 81 82 #include "com.h" 83 #if NCOM > 0 84 #include <sys/termios.h> 85 #include <dev/ic/comreg.h> 86 #include <dev/ic/comvar.h> 87 #endif 88 89 const char *c_nec_pci_mainbusdevs[] = { 90 "jazzio", 91 "necpb", 92 NULL, 93 }; 94 95 /* 96 * chipset-dependent mcclock routines. 97 */ 98 99 static u_int mc_nec_pci_read(struct mc146818_softc *, u_int); 100 static void mc_nec_pci_write(struct mc146818_softc *, u_int, u_int); 101 102 struct mcclock_jazzio_config mcclock_nec_pci_conf = { 103 0x80004000, /* I/O base */ 104 2, /* I/O size */ 105 mc_nec_pci_read, /* read function */ 106 mc_nec_pci_write /* write function */ 107 }; 108 109 /* 110 * This is a mask of bits to clear in the SR when we go to a 111 * given interrupt priority level. 112 */ 113 static const uint32_t nec_pci_ipl_sr_bits[_IPL_N] = { 114 [IPL_NONE] = 0, 115 [IPL_SOFTCLOCK] = 116 MIPS_SOFT_INT_MASK_0, 117 [IPL_SOFTNET] = 118 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1, 119 [IPL_VM] = 120 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | 121 MIPS_INT_MASK_0 | 122 MIPS_INT_MASK_1 | 123 MIPS_INT_MASK_2, 124 [IPL_SCHED] = 125 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | 126 MIPS_INT_MASK_0 | 127 MIPS_INT_MASK_1 | 128 MIPS_INT_MASK_2 | 129 MIPS_INT_MASK_3 | 130 MIPS_INT_MASK_4 | 131 MIPS_INT_MASK_5, 132 }; 133 134 static u_int 135 mc_nec_pci_read(struct mc146818_softc *sc, u_int reg) 136 { 137 u_int i, as; 138 139 as = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 1) & 0x80; 140 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1, as | reg); 141 i = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 0); 142 return i; 143 } 144 145 static void 146 mc_nec_pci_write(struct mc146818_softc *sc, u_int reg, u_int datum) 147 { 148 u_int as; 149 150 as = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 1) & 0x80; 151 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1, as | reg); 152 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 0, datum); 153 } 154 155 /* 156 * chipset-dependent jazzio bus configuration 157 */ 158 159 void jazzio_nec_pci_set_iointr_mask(int); 160 161 struct jazzio_config jazzio_nec_pci_conf = { 162 RD94_SYS_INTSTAT1, 163 jazzio_nec_pci_set_iointr_mask, 164 RD94_SYS_TL_BASE, 165 RD94_SYS_DMA0_REGS, 166 }; 167 168 void 169 jazzio_nec_pci_set_iointr_mask(int mask) 170 { 171 172 /* XXX: I don't know why, but firmware does. */ 173 if (in32(RD94_V_LOCAL_IO_BASE + 0x560) != 0) 174 out16(RD94_SYS_LB_IE2, mask); 175 else 176 out16(RD94_SYS_LB_IE1, mask); 177 } 178 179 /* 180 * critial i/o space, interrupt, and other chipset related initialization. 181 */ 182 void 183 c_nec_pci_init(void) 184 { 185 186 /* 187 * Initialize interrupt priority 188 */ 189 ipl_sr_bits = nec_pci_ipl_sr_bits; 190 191 /* 192 * Initialize I/O address offset 193 */ 194 arc_bus_space_init(&jazzio_bus, "jazzio", 195 RD94_P_LOCAL_IO_BASE, RD94_V_LOCAL_IO_BASE, 196 RD94_V_LOCAL_IO_BASE, RD94_S_LOCAL_IO_BASE); 197 198 arc_bus_space_init(&arc_bus_io, "rd94pciio", 199 RD94_P_PCI_IO, RD94_V_PCI_IO, 0, RD94_S_PCI_IO); 200 arc_bus_space_init(&arc_bus_mem, "rd94pcimem", 201 RD94_P_PCI_MEM, RD94_V_PCI_MEM, 0, RD94_S_PCI_MEM); 202 203 /* 204 * Initialize wired TLB for I/O space which is used on early stage 205 */ 206 arc_init_wired_map(); 207 arc_wired_enter_page(RD94_V_LOCAL_IO_BASE, RD94_P_LOCAL_IO_BASE, 208 RD94_S_LOCAL_IO_BASE); 209 /* 210 * allocate only 16M for PCM MEM space for now to save wired TLB entry; 211 * Other regions will be allocalted by bus_space_large.c later. 212 */ 213 arc_wired_enter_page(RD94_V_PCI_IO, RD94_P_PCI_IO, RD94_S_PCI_IO); 214 arc_wired_enter_page(RD94_V_PCI_MEM, RD94_P_PCI_MEM, RD94_S_PCI_IO); 215 216 /* 217 * By default, reserve 32MB in KSEG2 for PCI memory space. 218 * Since kseg2iobufsize/NBPG*4 bytes are used for Sysmap, 219 * this consumes 32KB physical memory. 220 * 221 * If a kernel with "options DIAGNOSTIC" panics with 222 * the message "pmap_enter: kva too big", you have to 223 * increase this value by a option like below: 224 * options KSEG2IOBUFSIZE=0x1b000000 # 432MB consumes 432KB 225 * If you met this symptom, please report it to 226 * port-arc-maintainer@NetBSD.org. 227 * 228 * kseg2iobufsize will be refered from pmap_bootstrap(). 229 */ 230 kseg2iobufsize = 0x02000000; /* 32MB: consumes 32KB for PTEs */ 231 232 /* 233 * Disable all interrupts. New masks will be set up 234 * during system configuration 235 */ 236 out16(RD94_SYS_LB_IE1, 0); 237 out16(RD94_SYS_LB_IE2, 0); 238 out32(RD94_SYS_EXT_IMASK, 0); 239 240 /* 241 * common configuration between NEC EISA and PCI platforms 242 */ 243 c_nec_jazz_init(); 244 245 /* chipset-dependent mcclock configuration */ 246 mcclock_jazzio_conf = &mcclock_nec_pci_conf; 247 248 /* chipset-dependent jazzio bus configuration */ 249 jazzio_conf = &jazzio_nec_pci_conf; 250 } 251 252 /* 253 * console initialization 254 */ 255 void 256 c_nec_pci_cons_init(void) 257 { 258 259 if (!com_console) { 260 if (strcmp(arc_displayc_id, "10110004") == 0) { 261 /* NEC RISCstation 2200 PCI TGA [NEC-RA94] */ 262 /* NEC RISCstation 2250 PCI TGA [NEC-RD94] */ 263 /* NEC Express 5800/230 R4400 PCI TGA [NEC-JC94] */ 264 /* NEC Express 5800/230 R10000 PCI TGA [NEC-J95] */ 265 #if NTGA > 0 266 necpb_init(&necpb_main_context); 267 /* XXX device number is hardcoded */ 268 if (tga_cnattach(&necpb_main_context.nc_iot, 269 &necpb_main_context.nc_memt, 270 &necpb_main_context.nc_pc, 0, 3, 0) == 0) { 271 #if NPCKBC_JAZZIO > 0 272 pckbc_cnattach(&jazzio_bus, PICA_SYS_KBD, 273 JAZZIO_KBCMDP, PCKBC_KBD_SLOT); 274 #endif 275 return; 276 } 277 #endif 278 } else if (strcmp(arc_displayc_id, "53335631") == 0 279 /* NEC RISCstation 2200 PCI VGA S3 ViRGE [NEC-RA'94] */ 280 || strcmp(arc_displayc_id, "3D3D0001") == 0 281 /* NEC RISCstation 2200 PCI VGA 3Dlab GLINT 300SX */ 282 ) { 283 /* XXX - the followings are not really tested */ 284 #if NVGA_PCI > 0 285 necpb_init(&necpb_main_context); 286 /* XXX device number is hardcoded */ 287 if (vga_pci_cnattach(&necpb_main_context.nc_iot, 288 &necpb_main_context.nc_memt, 289 &necpb_main_context.nc_pc, 0, 3, 0) == 0) { 290 #if NPCKBC_JAZZIO > 0 291 pckbc_cnattach(&jazzio_bus, PICA_SYS_KBD, 292 JAZZIO_KBCMDP, PCKBC_KBD_SLOT); 293 #endif 294 return; 295 } 296 #endif 297 } else { 298 printf("nec_pci: unknown display controller [%s]\n", 299 arc_displayc_id); 300 } 301 } 302 303 #if NCOM > 0 304 if (com_console_address == 0) 305 com_console_address = RD94_SYS_COM1; 306 comcnattach(&jazzio_bus, com_console_address, 307 com_console_speed, com_freq, COM_TYPE_NORMAL, com_console_mode); 308 #endif 309 } 310