1 /* $NetBSD: p_sni_rm200pci.c,v 1.13 2010/11/12 16:09:57 uebayasi Exp $ */ 2 /* $OpenBSD: machdep.c,v 1.36 1999/05/22 21:22:19 weingart Exp $ */ 3 4 /* 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department, The Mach Operating System project at 11 * Carnegie-Mellon University and Ralph Campbell. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94 38 */ 39 /* 40 * Copyright (c) 1988 University of Utah. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * the Systems Programming Group of the University of Utah Computer 44 * Science Department, The Mach Operating System project at 45 * Carnegie-Mellon University and Ralph Campbell. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. All advertising materials mentioning features or use of this software 56 * must display the following acknowledgement: 57 * This product includes software developed by the University of 58 * California, Berkeley and its contributors. 59 * 4. Neither the name of the University nor the names of its contributors 60 * may be used to endorse or promote products derived from this software 61 * without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 64 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 65 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 73 * SUCH DAMAGE. 74 * 75 * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: p_sni_rm200pci.c,v 1.13 2010/11/12 16:09:57 uebayasi Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/device.h> 84 #include <uvm/uvm.h> 85 86 #include <machine/autoconf.h> 87 #include <machine/bus.h> 88 #include <machine/pio.h> 89 #include <machine/platform.h> 90 #include <machine/wired_map.h> 91 92 #include <mips/pte.h> 93 94 void p_sni_rm200pci_init(void); 95 void p_sni_rm200pci_cons_init(void); 96 97 #include "com.h" 98 #if NCOM > 0 99 #include <sys/termios.h> 100 #include <dev/ic/comreg.h> 101 #include <dev/ic/comvar.h> 102 #endif 103 104 struct platform platform_sni_rm200pci = { 105 "RM200PCI", 106 NULL, /* unknown */ 107 "", 108 "RM200", 109 "Siemens Nixdorf", 110 150, /* MHz ?? */ 111 NULL, /* XXX */ 112 platform_generic_match, 113 p_sni_rm200pci_init, 114 p_sni_rm200pci_cons_init, 115 platform_nop, /* reset */ 116 arc_set_intr, /* ??? */ 117 }; 118 119 /* 120 * This is a mask of bits to clear in the SR when we go to a 121 * given interrupt priority level. 122 */ 123 /* XXX lack of hardware info for sni_rm200pci */ 124 static const uint32_t sni_rm200pci_ipl_sr_bits[_IPL_N] = { 125 [IPL_NONE] = 0, 126 [IPL_SOFTCLOCK] = 127 MIPS_SOFT_INT_MASK_0, 128 [IPL_SOFTNET] = 129 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1, 130 [IPL_VM] = /* XXX */ 131 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | 132 MIPS_INT_MASK_0 | 133 MIPS_INT_MASK_1 | 134 MIPS_INT_MASK_2 | 135 MIPS_INT_MASK_3 | 136 MIPS_INT_MASK_4 | 137 MIPS_INT_MASK_5, 138 [IPL_SCHED] = /* XXX */ 139 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | 140 MIPS_INT_MASK_0 | 141 MIPS_INT_MASK_1 | 142 MIPS_INT_MASK_2 | 143 MIPS_INT_MASK_3 | 144 MIPS_INT_MASK_4 | 145 MIPS_INT_MASK_5, 146 }; 147 148 /* 149 * critial i/o space, interrupt, and other chipset related initialization. 150 */ 151 void 152 p_sni_rm200pci_init(void) 153 { 154 155 /* 156 * Initialize wired TLB for I/O space which is used on early stage 157 */ 158 159 /* 160 * Initialize interrupt priority 161 */ 162 ipl_sr_bits = sni_rm200pci_ipl_sr_bits; 163 164 /* 165 * XXX - should be enabled, if tested. 166 * 167 * We use safe default for now, because this platform is untested. 168 * In other words, the following may not be needed at all. 169 */ 170 vm_page_zero_enable = false; 171 172 /* 173 * Initialize I/O address offset 174 */ 175 arc_init_wired_map(); 176 #if 0 177 arc_bus_space_init(&arc_bus_io, "rm200isaio", 178 RM200_P_ISA_IO, RM200_V_ISA_IO, 0, RM200_S_ISA_IO); 179 arc_bus_space_init(&arc_bus_mem, "rm200isamem", 180 RM200_P_ISA_MEM, RM200_V_ISA_MEM, 0, RM200_S_ISA_MEM); 181 #endif 182 } 183 184 void 185 p_sni_rm200pci_cons_init(void) 186 { 187 188 if (!com_console) { 189 /* XXX For now... */ 190 } 191 if (com_console_address == 0) { 192 #if 0 /* XXX */ 193 com_console_address = xxx; 194 #else 195 panic("console address unknown"); 196 #endif 197 } 198 comcnattach(&arc_bus_io /* XXX? */, com_console_address, 199 com_console_speed, com_freq, COM_TYPE_NORMAL, com_console_mode); 200 } 201