xref: /netbsd/sys/arch/arm/arm/arm_machdep.c (revision bf9ec67e)
1 /*	$NetBSD: arm_machdep.c,v 1.5 2002/04/03 23:33:27 thorpej Exp $	*/
2 
3 /*
4  * Copyright (c) 1994-1998 Mark Brinicombe.
5  * Copyright (c) 1994 Brini.
6  * All rights reserved.
7  *
8  * This code is derived from software written for Brini by Mark Brinicombe
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *	This product includes software developed by Mark Brinicombe
21  *	for the NetBSD Project.
22  * 4. The name of the company nor the name of the author may be used to
23  *    endorse or promote products derived from this software without specific
24  *    prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
27  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36  * SUCH DAMAGE.
37  */
38 
39 #include "opt_compat_netbsd.h"
40 
41 #include <sys/param.h>
42 
43 __KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.5 2002/04/03 23:33:27 thorpej Exp $");
44 
45 #include <sys/exec.h>
46 #include <sys/proc.h>
47 #include <sys/systm.h>
48 #include <sys/user.h>
49 
50 #include <machine/pcb.h>
51 #include <machine/vmparam.h>
52 
53 /*
54  * The ARM architecture places the vector page at address 0.
55  * Later ARM architecture versions, however, allow it to be
56  * relocated to a high address (0xffff0000).  This is primarily
57  * to support the Fast Context Switch Extension.
58  *
59  * This variable contains the address of the vector page.  It
60  * defaults to 0; it only needs to be initialized if we enable
61  * relocated vectors.
62  */
63 vaddr_t	vector_page;
64 
65 /*
66  * Clear registers on exec
67  */
68 
69 void
70 setregs(struct proc *p, struct exec_package *pack, u_long stack)
71 {
72 	struct trapframe *tf;
73 
74 	tf = p->p_addr->u_pcb.pcb_tf;
75 
76 	memset(tf, 0, sizeof(*tf));
77 	tf->tf_r0 = (u_int)p->p_psstr;
78 #ifdef COMPAT_13
79 	tf->tf_r12 = stack;			/* needed by pre 1.4 crt0.c */
80 #endif
81 	tf->tf_usr_sp = stack;
82 	tf->tf_usr_lr = pack->ep_entry;
83 	tf->tf_svc_lr = 0x77777777;		/* Something we can see */
84 	tf->tf_pc = pack->ep_entry;
85 #ifdef __PROG32
86 	tf->tf_spsr = PSR_USR32_MODE;
87 #endif
88 
89 	p->p_addr->u_pcb.pcb_flags = 0;
90 }
91