1/* $NetBSD: bus_space_asm_generic.S,v 1.2 2002/08/29 17:27:48 briggs Exp $ */ 2 3/* 4 * Copyright (c) 1997 Causality Limited. 5 * Copyright (c) 1997 Mark Brinicombe. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37#include <arm/asm.h> 38#include <arm/cpuconf.h> 39 40/* 41 * Generic bus_space functions. 42 */ 43 44/* 45 * read single 46 */ 47 48ENTRY(generic_bs_r_1) 49 ldrb r0, [r1, r2] 50 mov pc, lr 51 52#if (ARM_ARCH_4 + ARM_ARCH_5) > 0 53ENTRY(generic_armv4_bs_r_2) 54 ldrh r0, [r1, r2] 55 mov pc, lr 56#endif 57 58ENTRY(generic_bs_r_4) 59 ldr r0, [r1, r2] 60 mov pc, lr 61 62/* 63 * write single 64 */ 65 66ENTRY(generic_bs_w_1) 67 strb r3, [r1, r2] 68 mov pc, lr 69 70#if (ARM_ARCH_4 + ARM_ARCH_5) > 0 71ENTRY(generic_armv4_bs_w_2) 72 strh r3, [r1, r2] 73 mov pc, lr 74#endif 75 76ENTRY(generic_bs_w_4) 77 str r3, [r1, r2] 78 mov pc, lr 79 80/* 81 * read multiple 82 */ 83 84ENTRY(generic_bs_rm_1) 85 add r0, r1, r2 86 mov r1, r3 87 ldr r2, [sp, #0] 88 teq r2, #0 89 moveq pc, lr 90 911: ldrb r3, [r0] 92 strb r3, [r1], #1 93 subs r2, r2, #1 94 bne 1b 95 96 mov pc, lr 97 98#if (ARM_ARCH_4 + ARM_ARCH_5) > 0 99ENTRY(generic_armv4_bs_rm_2) 100 add r0, r1, r2 101 mov r1, r3 102 ldr r2, [sp, #0] 103 teq r2, #0 104 moveq pc, lr 105 1061: ldrh r3, [r0] 107 strh r3, [r1], #2 108 subs r2, r2, #1 109 bne 1b 110 111 mov pc, lr 112#endif 113 114ENTRY(generic_bs_rm_4) 115 add r0, r1, r2 116 mov r1, r3 117 ldr r2, [sp, #0] 118 teq r2, #0 119 moveq pc, lr 120 1211: ldr r3, [r0] 122 str r3, [r1], #4 123 subs r2, r2, #1 124 bne 1b 125 126 mov pc, lr 127 128/* 129 * write multiple 130 */ 131 132ENTRY(generic_bs_wm_1) 133 add r0, r1, r2 134 mov r1, r3 135 ldr r2, [sp, #0] 136 teq r2, #0 137 moveq pc, lr 138 1391: ldrb r3, [r1], #1 140 strb r3, [r0] 141 subs r2, r2, #1 142 bne 1b 143 144 mov pc, lr 145 146#if (ARM_ARCH_4 + ARM_ARCH_5) > 0 147ENTRY(generic_armv4_bs_wm_2) 148 add r0, r1, r2 149 mov r1, r3 150 ldr r2, [sp, #0] 151 teq r2, #0 152 moveq pc, lr 153 1541: ldrh r3, [r1], #2 155 strh r3, [r0] 156 subs r2, r2, #1 157 bne 1b 158 159 mov pc, lr 160#endif 161 162ENTRY(generic_bs_wm_4) 163 add r0, r1, r2 164 mov r1, r3 165 ldr r2, [sp, #0] 166 teq r2, #0 167 moveq pc, lr 168 1691: ldr r3, [r1], #4 170 str r3, [r0] 171 subs r2, r2, #1 172 bne 1b 173 174 mov pc, lr 175 176/* 177 * read region 178 */ 179 180ENTRY(generic_bs_rr_1) 181 add r0, r1, r2 182 mov r1, r3 183 ldr r2, [sp, #0] 184 teq r2, #0 185 moveq pc, lr 186 1871: ldrb r3, [r0], #1 188 strb r3, [r1], #1 189 subs r2, r2, #1 190 bne 1b 191 192 mov pc, lr 193 194#if (ARM_ARCH_4 + ARM_ARCH_5) > 0 195ENTRY(generic_armv4_bs_rr_2) 196 add r0, r1, r2 197 mov r1, r3 198 ldr r2, [sp, #0] 199 teq r2, #0 200 moveq pc, lr 201 2021: ldrh r3, [r0], #2 203 strh r3, [r1], #2 204 subs r2, r2, #1 205 bne 1b 206 207 mov pc, lr 208#endif 209 210ENTRY(generic_bs_rr_4) 211 add r0, r1, r2 212 mov r1, r3 213 ldr r2, [sp, #0] 214 teq r2, #0 215 moveq pc, lr 216 2171: ldr r3, [r0], #4 218 str r3, [r1], #4 219 subs r2, r2, #1 220 bne 1b 221 222 mov pc, lr 223 224/* 225 * write region. 226 */ 227 228#if (ARM_ARCH_4 + ARM_ARCH_5) > 0 229ENTRY(generic_armv4_bs_wr_2) 230 add r0, r1, r2 231 mov r1, r3 232 ldr r2, [sp, #0] 233 teq r2, #0 234 moveq pc, lr 235 2361: ldrh r3, [r1], #2 237 strh r3, [r0], #2 238 subs r2, r2, #1 239 bne 1b 240 241 mov pc, lr 242#endif 243 244ENTRY(generic_bs_wr_4) 245 add r0, r1, r2 246 mov r1, r3 247 ldr r2, [sp, #0] 248 teq r2, #0 249 moveq pc, lr 250 2511: ldr r3, [r1], #4 252 str r3, [r0], #4 253 subs r2, r2, #1 254 bne 1b 255 256 mov pc, lr 257 258/* 259 * set region 260 */ 261 262#if (ARM_ARCH_4 + ARM_ARCH_5) > 0 263ENTRY(generic_armv4_bs_sr_2) 264 add r0, r1, r2 265 mov r1, r3 266 ldr r2, [sp, #0] 267 teq r2, #0 268 moveq pc, lr 269 2701: strh r1, [r0], #2 271 subs r2, r2, #1 272 bne 1b 273 274 mov pc, lr 275#endif 276 277ENTRY(generic_bs_sr_4) 278 add r0, r1, r2 279 mov r1, r3 280 ldr r2, [sp, #0] 281 teq r2, #0 282 moveq pc, lr 283 2841: str r1, [r0], #4 285 subs r2, r2, #1 286 bne 1b 287 288 mov pc, lr 289 290/* 291 * copy region 292 */ 293 294#if (ARM_ARCH_4 + ARM_ARCH_5) > 0 295ENTRY(generic_armv4_bs_c_2) 296 add r0, r1, r2 297 ldr r2, [sp, #0] 298 add r1, r2, r3 299 ldr r2, [sp, #4] 300 teq r2, #0 301 moveq pc, lr 302 303 cmp r0, r1 304 blt 2f 305 3061: ldrh r3, [r0], #2 307 strh r3, [r1], #2 308 subs r2, r2, #1 309 bne 1b 310 311 mov pc, lr 312 3132: add r0, r0, r2, lsl #1 314 add r1, r1, r2, lsl #1 315 sub r0, r0, #2 316 sub r1, r1, #2 317 3183: ldrh r3, [r0], #-2 319 strh r3, [r1], #-2 320 subs r2, r2, #1 321 bne 3b 322 323 mov pc, lr 324#endif 325