1/* $NetBSD: cpufunc_asm_arm67.S,v 1.1 2001/11/10 23:14:09 thorpej Exp $ */ 2 3/* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * ARM6/ARM7 assembly functions for CPU / MMU / TLB specific operations 36 */ 37 38#include <machine/cpu.h> 39#include <machine/asm.h> 40 41/* 42 * Functions to set the MMU Translation Table Base register 43 * 44 * We need to clean and flush the cache as it uses virtual 45 * addresses that are about to change. 46 */ 47ENTRY(arm67_setttb) 48 mcr p15, 0, r0, c7, c0, 0 49 50 /* Write the TTB */ 51 mcr p15, 0, r0, c2, c0, 0 52 53 /* If we have updated the TTB we must flush the TLB */ 54 mcr p15, 0, r0, c5, c0, 0 55 56 /* For good measure we will flush the IDC as well */ 57 mcr p15, 0, r0, c7, c0, 0 58 59 /* Make sure that pipeline is emptied */ 60 mov r0, r0 61 mov r0, r0 62 63 mov pc, lr 64 65/* 66 * TLB functions 67 */ 68ENTRY(arm67_tlb_flush) 69 mcr p15, 0, r0, c5, c0, 0 70 mov pc, lr 71 72ENTRY(arm67_tlb_purge) 73 mcr p15, 0, r0, c6, c0, 0 74 mov pc, lr 75 76/* 77 * Cache functions 78 */ 79ENTRY(arm67_cache_flush) 80 mcr p15, 0, r0, c7, c0, 0 81 mov pc, lr 82 83/* 84 * Context switch. 85 * 86 * These is the CPU-specific parts of the context switcher cpu_switch() 87 * These functions actually perform the TTB reload. 88 * 89 * NOTE: Special calling convention 90 * r1, r4-r13 must be preserved 91 */ 92ENTRY(arm67_context_switch) 93 /* For good measure we will flush the IDC as well */ 94 mcr p15, 0, r0, c7, c0, 0 /* flush cache */ 95 96 /* Write the TTB */ 97 mcr p15, 0, r0, c2, c0, 0 98 99 /* If we have updated the TTB we must flush the TLB */ 100 mcr p15, 0, r0, c5, c0, 0 101 102#if 0 103 /* For good measure we will flush the IDC as well */ 104 mcr p15, 0, r0, c7, c0, 0 /* flush cache */ 105#endif 106 107 /* Make sure that pipeline is emptied */ 108 mov r0, r0 109 mov r0, r0 110 mov pc, lr 111