1/* $NetBSD: cpufunc_asm_arm9.S,v 1.2 2002/01/29 15:27:29 rearnsha Exp $ */ 2 3/* 4 * Copyright (c) 2001 ARM Limited 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * ARM9 assembly functions for CPU / MMU / TLB specific operations 32 */ 33 34#include <machine/cpu.h> 35#include <machine/asm.h> 36 37/* 38 * Functions to set the MMU Translation Table Base register 39 * 40 * We need to clean and flush the cache as it uses virtual 41 * addresses that are about to change. 42 */ 43ENTRY(arm9_setttb) 44 /* 45 * Since we use the caches in write-through mode, we only have to 46 * drain the write buffers and flush the caches. 47 */ 48 mcr p15, 0, r0, c7, c7, 0 /* flush I+D caches */ 49 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 50 51 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 52 53 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 54 mov pc, lr 55 56/* 57 * TLB functions 58 */ 59ENTRY(arm9_tlb_flushID_SE) 60 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 61 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 62 mov pc, lr 63 64/* 65 * Cache functions 66 */ 67ENTRY(arm9_cache_flushID) 68 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */ 69 mov pc, lr 70 71ENTRY(arm9_cache_flushID_SE) 72 mcr p15, 0, r0, c7, c5, 1 /* flush one entry from I cache */ 73 mcr p15, 0, r0, c7, c6, 1 /* flush one entry from D cache */ 74 mov pc, lr 75 76ENTRY(arm9_cache_flushI) 77 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ 78 mov pc, lr 79 80ENTRY(arm9_cache_flushI_SE) 81 mcr p15, 0, r0, c7, c5, 1 /* flush one entry from I cache */ 82 mov pc, lr 83 84ENTRY(arm9_cache_flushD) 85 mcr p15, 0, r0, c7, c6, 0 /* flush D cache */ 86 mov pc, lr 87 88ENTRY(arm9_cache_flushD_SE) 89 mcr p15, 0, r0, c7, c6, 1 /* flush one entry from D cache */ 90 mov pc, lr 91 92ENTRY(arm9_cache_cleanID) 93 mcr p15, 0, r0, c7, c10, 4 94 mov pc, lr 95 96/* 97 * Soft functions 98 */ 99ENTRY(arm9_cache_syncI) 100 mcr p15, 0, r0, c7, c7, 0 /* flush I+D caches */ 101 mov pc, lr 102 103ENTRY_NP(arm9_cache_flushID_rng) 104 b _C_LABEL(arm9_cache_flushID) 105 106ENTRY_NP(arm9_cache_flushD_rng) 107 /* Same as above, but D cache only */ 108 b _C_LABEL(arm9_cache_flushD) 109 110ENTRY_NP(arm9_cache_syncI_rng) 111 /* Similarly, for I cache sync */ 112 b _C_LABEL(arm9_cache_syncI) 113 114/* 115 * Context switch. 116 * 117 * These is the CPU-specific parts of the context switcher cpu_switch() 118 * These functions actually perform the TTB reload. 119 * 120 * NOTE: Special calling convention 121 * r1, r4-r13 must be preserved 122 */ 123ENTRY(arm9_context_switch) 124 /* 125 * We can assume that the caches will only contain kernel addresses 126 * at this point. So no need to flush them again. 127 */ 128 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 129 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ 130 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */ 131 132 /* Paranoia -- make sure the pipeline is empty. */ 133 nop 134 nop 135 nop 136 mov pc, lr 137