1 /* $NetBSD: disassem.c,v 1.12 2002/03/10 15:47:43 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Mark Brinicombe. 5 * Copyright (c) 1996 Brini. 6 * 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Brini. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * RiscBSD kernel project 37 * 38 * db_disasm.c 39 * 40 * Kernel disassembler 41 * 42 * Created : 10/02/96 43 * 44 * Structured after the sparc/sparc/db_disasm.c by David S. Miller & 45 * Paul Kranenburg 46 * 47 * This code is not complete. Not all instructions are disassembled. 48 */ 49 50 #include <sys/param.h> 51 52 __KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.12 2002/03/10 15:47:43 bjh21 Exp $"); 53 54 #include <sys/systm.h> 55 #include <arch/arm/arm/disassem.h> 56 57 /* 58 * General instruction format 59 * 60 * insn[cc][mod] [operands] 61 * 62 * Those fields with an uppercase format code indicate that the field 63 * follows directly after the instruction before the separator i.e. 64 * they modify the instruction rather than just being an operand to 65 * the instruction. The only exception is the writeback flag which 66 * follows a operand. 67 * 68 * 69 * 2 - print Operand 2 of a data processing instruction 70 * d - destination register (bits 12-15) 71 * n - n register (bits 16-19) 72 * s - s register (bits 8-11) 73 * o - indirect register rn (bits 16-19) (used by swap) 74 * m - m register (bits 0-3) 75 * a - address operand of ldr/str instruction 76 * l - register list for ldm/stm instruction 77 * f - 1st fp operand (register) (bits 12-14) 78 * g - 2nd fp operand (register) (bits 16-18) 79 * h - 3rd fp operand (register/immediate) (bits 0-4) 80 * b - branch address 81 * t - thumb branch address (bits 24, 0-23) 82 * k - breakpoint comment (bits 0-3, 8-19) 83 * X - block transfer type 84 * Y - block transfer type (r13 base) 85 * c - comment field bits(0-23) 86 * p - saved or current status register 87 * F - PSR transfer fields 88 * B - byte transfer flag 89 * D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN 90 * L - co-processor transfer size 91 * S - set status flag 92 * T - user mode transfer 93 * P - fp precision 94 * Q - fp precision (for ldf/stf) 95 * R - fp rounding 96 * v - co-processor data transfer registers + addressing mode 97 * W - writeback flag 98 * x - instruction in hex 99 * # - co-processor number 100 * y - co-processor data processing registers 101 * z - co-processor register transfer registers 102 */ 103 104 struct arm32_insn { 105 u_int mask; 106 u_int pattern; 107 char* name; 108 char* format; 109 }; 110 111 static const struct arm32_insn arm32_i[] = { 112 { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */ 113 { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */ 114 { 0x0f000000, 0x0f000000, "swi", "c" }, 115 { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */ 116 { 0x0f000000, 0x0a000000, "b", "b" }, 117 { 0x0f000000, 0x0b000000, "bl", "b" }, 118 { 0x0fe000f0, 0x00000090, "mul", "Snms" }, 119 { 0x0fe000f0, 0x00200090, "mla", "Snmsd" }, 120 { 0x0fe000f0, 0x00800090, "umull", "Sdnms" }, 121 { 0x0fe000f0, 0x00c00090, "smull", "Sdnms" }, 122 { 0x0fe000f0, 0x00a00090, "umlal", "Sdnms" }, 123 { 0x0fe000f0, 0x00e00090, "smlal", "Sdnms" }, 124 { 0x0e100000, 0x04000000, "str", "BTdaW" }, 125 { 0x0e100000, 0x04100000, "ldr", "BTdaW" }, 126 { 0x0c100010, 0x04000000, "str", "BTdaW" }, 127 { 0x0c100010, 0x04100000, "ldr", "BTdaW" }, 128 { 0x0e1f0000, 0x080d0000, "stm", "YnWl" },/* separate out r13 base */ 129 { 0x0e1f0000, 0x081d0000, "ldm", "YnWl" },/* separate out r13 base */ 130 { 0x0e100000, 0x08000000, "stm", "XnWl" }, 131 { 0x0e100000, 0x08100000, "ldm", "XnWl" }, 132 { 0x0e500ff0, 0x001000b0, "ldrh", "daW" }, 133 { 0x0e500ff0, 0x000000b0, "strh", "daW" }, 134 { 0x0e500ff0, 0x001000d0, "ldrsb", "daW" }, 135 { 0x0e500ff0, 0x001000f0, "ldrsh", "daW" }, 136 { 0x0f200090, 0x00200090, "und", "x" }, /* Before data processing */ 137 { 0x0e1000d0, 0x000000d0, "und", "x" }, /* Before data processing */ 138 { 0x0fb00ff0, 0x01000090, "swp", "Bdmo" }, 139 { 0x0fbf0fff, 0x010f0000, "mrs", "dp" }, /* Before data processing */ 140 { 0x0fb0fff0, 0x0120f000, "msr", "pFm" },/* Before data processing */ 141 { 0x0fb0f000, 0x0320f000, "msr", "pF2" },/* Before data processing */ 142 { 0x0ffffff0, 0x012fff10, "bx", "m" }, 143 { 0x0fff0ff0, 0x016f0f10, "clz", "dm" }, 144 { 0x0ffffff0, 0x012fff30, "blx", "m" }, 145 { 0xfff000f0, 0xe1200070, "bkpt", "k" }, 146 { 0x0de00000, 0x00000000, "and", "Sdn2" }, 147 { 0x0de00000, 0x00200000, "eor", "Sdn2" }, 148 { 0x0de00000, 0x00400000, "sub", "Sdn2" }, 149 { 0x0de00000, 0x00600000, "rsb", "Sdn2" }, 150 { 0x0de00000, 0x00800000, "add", "Sdn2" }, 151 { 0x0de00000, 0x00a00000, "adc", "Sdn2" }, 152 { 0x0de00000, 0x00c00000, "sbc", "Sdn2" }, 153 { 0x0de00000, 0x00e00000, "rsc", "Sdn2" }, 154 { 0x0df00000, 0x01100000, "tst", "Dn2" }, 155 { 0x0df00000, 0x01300000, "teq", "Dn2" }, 156 { 0x0de00000, 0x01400000, "cmp", "Dn2" }, 157 { 0x0de00000, 0x01600000, "cmn", "Dn2" }, 158 { 0x0de00000, 0x01800000, "orr", "Sdn2" }, 159 { 0x0de00000, 0x01a00000, "mov", "Sd2" }, 160 { 0x0de00000, 0x01c00000, "bic", "Sdn2" }, 161 { 0x0de00000, 0x01e00000, "mvn", "Sd2" }, 162 { 0x0ff08f10, 0x0e000100, "adf", "PRfgh" }, 163 { 0x0ff08f10, 0x0e100100, "muf", "PRfgh" }, 164 { 0x0ff08f10, 0x0e200100, "suf", "PRfgh" }, 165 { 0x0ff08f10, 0x0e300100, "rsf", "PRfgh" }, 166 { 0x0ff08f10, 0x0e400100, "dvf", "PRfgh" }, 167 { 0x0ff08f10, 0x0e500100, "rdf", "PRfgh" }, 168 { 0x0ff08f10, 0x0e600100, "pow", "PRfgh" }, 169 { 0x0ff08f10, 0x0e700100, "rpw", "PRfgh" }, 170 { 0x0ff08f10, 0x0e800100, "rmf", "PRfgh" }, 171 { 0x0ff08f10, 0x0e900100, "fml", "PRfgh" }, 172 { 0x0ff08f10, 0x0ea00100, "fdv", "PRfgh" }, 173 { 0x0ff08f10, 0x0eb00100, "frd", "PRfgh" }, 174 { 0x0ff08f10, 0x0ec00100, "pol", "PRfgh" }, 175 { 0x0f008f10, 0x0e000100, "fpbop", "PRfgh" }, 176 { 0x0ff08f10, 0x0e008100, "mvf", "PRfh" }, 177 { 0x0ff08f10, 0x0e108100, "mnf", "PRfh" }, 178 { 0x0ff08f10, 0x0e208100, "abs", "PRfh" }, 179 { 0x0ff08f10, 0x0e308100, "rnd", "PRfh" }, 180 { 0x0ff08f10, 0x0e408100, "sqt", "PRfh" }, 181 { 0x0ff08f10, 0x0e508100, "log", "PRfh" }, 182 { 0x0ff08f10, 0x0e608100, "lgn", "PRfh" }, 183 { 0x0ff08f10, 0x0e708100, "exp", "PRfh" }, 184 { 0x0ff08f10, 0x0e808100, "sin", "PRfh" }, 185 { 0x0ff08f10, 0x0e908100, "cos", "PRfh" }, 186 { 0x0ff08f10, 0x0ea08100, "tan", "PRfh" }, 187 { 0x0ff08f10, 0x0eb08100, "asn", "PRfh" }, 188 { 0x0ff08f10, 0x0ec08100, "acs", "PRfh" }, 189 { 0x0ff08f10, 0x0ed08100, "atn", "PRfh" }, 190 { 0x0f008f10, 0x0e008100, "fpuop", "PRfh" }, 191 { 0x0e100f00, 0x0c000100, "stf", "QLv" }, 192 { 0x0e100f00, 0x0c100100, "ldf", "QLv" }, 193 { 0x0ff00f10, 0x0e000110, "flt", "PRgd" }, 194 { 0x0ff00f10, 0x0e100110, "fix", "PRdh" }, 195 { 0x0ff00f10, 0x0e200110, "wfs", "d" }, 196 { 0x0ff00f10, 0x0e300110, "rfs", "d" }, 197 { 0x0ff00f10, 0x0e400110, "wfc", "d" }, 198 { 0x0ff00f10, 0x0e500110, "rfc", "d" }, 199 { 0x0ff0ff10, 0x0e90f110, "cmf", "PRgh" }, 200 { 0x0ff0ff10, 0x0eb0f110, "cnf", "PRgh" }, 201 { 0x0ff0ff10, 0x0ed0f110, "cmfe", "PRgh" }, 202 { 0x0ff0ff10, 0x0ef0f110, "cnfe", "PRgh" }, 203 { 0xff100010, 0xfe000010, "mcr2", "#z" }, 204 { 0x0f100010, 0x0e000010, "mcr", "#z" }, 205 { 0xff100010, 0xfe100010, "mrc2", "#z" }, 206 { 0x0f100010, 0x0e100010, "mrc", "#z" }, 207 { 0xff000010, 0xfe000000, "cdp2", "#y" }, 208 { 0x0f000010, 0x0e000000, "cdp", "#y" }, 209 { 0xfe100090, 0xfc100000, "ldc2", "L#v" }, 210 { 0x0e100090, 0x0c100000, "ldc", "L#v" }, 211 { 0xfe100090, 0xfc000000, "stc2", "L#v" }, 212 { 0x0e100090, 0x0c000000, "stc", "L#v" }, 213 { 0x00000000, 0x00000000, NULL, NULL } 214 }; 215 216 static char const arm32_insn_conditions[][4] = { 217 "eq", "ne", "cs", "cc", 218 "mi", "pl", "vs", "vc", 219 "hi", "ls", "ge", "lt", 220 "gt", "le", "", "nv" 221 }; 222 223 static char const insn_block_transfers[][4] = { 224 "da", "ia", "db", "ib" 225 }; 226 227 static char const insn_stack_block_transfers[][4] = { 228 "ed", "ea", "fd", "fa" 229 }; 230 231 static char const op_shifts[][4] = { 232 "lsl", "lsr", "asr", "ror" 233 }; 234 235 static char const insn_fpa_rounding[][2] = { 236 "", "p", "m", "z" 237 }; 238 239 static char const insn_fpa_precision[][2] = { 240 "s", "d", "e", "p" 241 }; 242 243 static char const insn_fpaconstants[][8] = { 244 "0.0", "1.0", "2.0", "3.0", 245 "4.0", "5.0", "0.5", "10.0" 246 }; 247 248 #define insn_condition(x) arm32_insn_conditions[(x >> 28) & 0x0f] 249 #define insn_blktrans(x) insn_block_transfers[(x >> 23) & 3] 250 #define insn_stkblktrans(x) insn_stack_block_transfers[(x >> 23) & 3] 251 #define op2_shift(x) op_shifts[(x >> 5) & 3] 252 #define insn_fparnd(x) insn_fpa_rounding[(x >> 5) & 0x03] 253 #define insn_fpaprec(x) insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 1] 254 #define insn_fpaprect(x) insn_fpa_precision[(((x >> 21) & 2)|(x >> 15)) & 1] 255 #define insn_fpaimm(x) insn_fpaconstants[x & 0x07] 256 257 /* Local prototypes */ 258 static void disasm_register_shift(const disasm_interface_t *di, u_int insn); 259 static void disasm_print_reglist(const disasm_interface_t *di, u_int insn); 260 static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, 261 u_int loc); 262 static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, 263 u_int loc); 264 static u_int disassemble_readword(u_int address); 265 static void disassemble_printaddr(u_int address); 266 267 vaddr_t 268 disasm(const disasm_interface_t *di, vaddr_t loc, int altfmt) 269 { 270 struct arm32_insn *i_ptr = (struct arm32_insn *)&arm32_i; 271 272 u_int insn; 273 int matchp; 274 int branch; 275 char* f_ptr; 276 int fmt; 277 278 fmt = 0; 279 matchp = 0; 280 insn = di->di_readword(loc); 281 282 /* di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/ 283 284 while (i_ptr->name) { 285 if ((insn & i_ptr->mask) == i_ptr->pattern) { 286 matchp = 1; 287 break; 288 } 289 i_ptr++; 290 } 291 292 if (!matchp) { 293 di->di_printf("und%s\t%08x\n", insn_condition(insn), insn); 294 return(loc + INSN_SIZE); 295 } 296 297 /* If instruction forces condition code, don't print it. */ 298 if ((i_ptr->mask & 0xf0000000) == 0xf0000000) 299 di->di_printf("%s", i_ptr->name); 300 else 301 di->di_printf("%s%s", i_ptr->name, insn_condition(insn)); 302 303 f_ptr = i_ptr->format; 304 305 /* Insert tab if there are no instruction modifiers */ 306 307 if (*(f_ptr) < 'A' || *(f_ptr) > 'Z') { 308 ++fmt; 309 di->di_printf("\t"); 310 } 311 312 while (*f_ptr) { 313 switch (*f_ptr) { 314 /* 2 - print Operand 2 of a data processing instruction */ 315 case '2': 316 if (insn & 0x02000000) { 317 int rotate= ((insn >> 7) & 0x1e); 318 319 di->di_printf("#0x%08x", 320 (insn & 0xff) << (32 - rotate) | 321 (insn & 0xff) >> rotate); 322 } else { 323 disasm_register_shift(di, insn); 324 } 325 break; 326 /* d - destination register (bits 12-15) */ 327 case 'd': 328 di->di_printf("r%d", ((insn >> 12) & 0x0f)); 329 break; 330 /* D - insert 'p' if Rd is R15 */ 331 case 'D': 332 if (((insn >> 12) & 0x0f) == 15) 333 di->di_printf("p"); 334 break; 335 /* n - n register (bits 16-19) */ 336 case 'n': 337 di->di_printf("r%d", ((insn >> 16) & 0x0f)); 338 break; 339 /* s - s register (bits 8-11) */ 340 case 's': 341 di->di_printf("r%d", ((insn >> 8) & 0x0f)); 342 break; 343 /* o - indirect register rn (bits 16-19) (used by swap) */ 344 case 'o': 345 di->di_printf("[r%d]", ((insn >> 16) & 0x0f)); 346 break; 347 /* m - m register (bits 0-4) */ 348 case 'm': 349 di->di_printf("r%d", ((insn >> 0) & 0x0f)); 350 break; 351 /* a - address operand of ldr/str instruction */ 352 case 'a': 353 disasm_insn_ldrstr(di, insn, loc); 354 break; 355 /* l - register list for ldm/stm instruction */ 356 case 'l': 357 disasm_print_reglist(di, insn); 358 break; 359 /* f - 1st fp operand (register) (bits 12-14) */ 360 case 'f': 361 di->di_printf("f%d", (insn >> 12) & 7); 362 break; 363 /* g - 2nd fp operand (register) (bits 16-18) */ 364 case 'g': 365 di->di_printf("f%d", (insn >> 16) & 7); 366 break; 367 /* h - 3rd fp operand (register/immediate) (bits 0-4) */ 368 case 'h': 369 if (insn & (1 << 3)) 370 di->di_printf("#%s", insn_fpaimm(insn)); 371 else 372 di->di_printf("f%d", insn & 7); 373 break; 374 /* b - branch address */ 375 case 'b': 376 branch = ((insn << 2) & 0x03ffffff); 377 if (branch & 0x02000000) 378 branch |= 0xfc000000; 379 di->di_printaddr(loc + 8 + branch); 380 break; 381 /* t - blx address */ 382 case 't': 383 branch = ((insn << 2) & 0x03ffffff) | 384 (insn >> 23 & 0x00000002); 385 if (branch & 0x02000000) 386 branch |= 0xfc000000; 387 di->di_printaddr(loc + 8 + branch); 388 break; 389 /* X - block transfer type */ 390 case 'X': 391 di->di_printf("%s", insn_blktrans(insn)); 392 break; 393 /* Y - block transfer type (r13 base) */ 394 case 'Y': 395 di->di_printf("%s", insn_stkblktrans(insn)); 396 break; 397 /* c - comment field bits(0-23) */ 398 case 'c': 399 di->di_printf("0x%08x", (insn & 0x00ffffff)); 400 break; 401 /* k - breakpoint comment (bits 0-3, 8-19) */ 402 case 'k': 403 di->di_printf("0x%04x", 404 (insn & 0x000fff00) >> 4 | (insn & 0x0000000f)); 405 break; 406 /* p - saved or current status register */ 407 case 'p': 408 if (insn & 0x00400000) 409 di->di_printf("spsr"); 410 else 411 di->di_printf("cpsr"); 412 break; 413 /* F - PSR transfer fields */ 414 case 'F': 415 di->di_printf("_"); 416 if (insn & (1 << 16)) 417 di->di_printf("c"); 418 if (insn & (1 << 17)) 419 di->di_printf("x"); 420 if (insn & (1 << 18)) 421 di->di_printf("s"); 422 if (insn & (1 << 19)) 423 di->di_printf("f"); 424 break; 425 /* B - byte transfer flag */ 426 case 'B': 427 if (insn & 0x00400000) 428 di->di_printf("b"); 429 break; 430 /* L - co-processor transfer size */ 431 case 'L': 432 if (insn & (1 << 22)) 433 di->di_printf("l"); 434 break; 435 /* S - set status flag */ 436 case 'S': 437 if (insn & 0x00100000) 438 di->di_printf("s"); 439 break; 440 /* T - user mode transfer */ 441 case 'T': 442 if ((insn & 0x01200000) == 0x00200000) 443 di->di_printf("t"); 444 break; 445 case 'P': 446 /* P - fp precision */ 447 di->di_printf("%s", insn_fpaprec(insn)); 448 break; 449 /* Q - fp precision (for ldf/stf) */ 450 case 'Q': 451 break; 452 /* R - fp rounding */ 453 case 'R': 454 di->di_printf("%s", insn_fparnd(insn)); 455 break; 456 /* W - writeback flag */ 457 case 'W': 458 if (insn & (1 << 21)) 459 di->di_printf("!"); 460 break; 461 /* # - co-processor number */ 462 case '#': 463 di->di_printf("p%d", (insn >> 8) & 0x0f); 464 break; 465 /* v - co-processor data transfer registers+addressing mode */ 466 case 'v': 467 disasm_insn_ldcstc(di, insn, loc); 468 break; 469 /* x - instruction in hex */ 470 case 'x': 471 di->di_printf("0x%08x", insn); 472 break; 473 /* y - co-processor data processing registers */ 474 case 'y': 475 di->di_printf("%d, ", (insn >> 20) & 0x0f); 476 477 di->di_printf("c%d, c%d, c%d", (insn >> 12) & 0x0f, 478 (insn >> 16) & 0x0f, insn & 0x0f); 479 480 di->di_printf(", %d", (insn >> 5) & 0x07); 481 break; 482 /* z - co-processor register transfer registers */ 483 case 'z': 484 di->di_printf("%d, ", (insn >> 21) & 0x07); 485 di->di_printf("r%d, c%d, c%d, %d", 486 (insn >> 12) & 0x0f, (insn >> 16) & 0x0f, 487 insn & 0x0f, (insn >> 5) & 0x07); 488 489 /* if (((insn >> 5) & 0x07) != 0) 490 di->di_printf(", %d", (insn >> 5) & 0x07);*/ 491 break; 492 default: 493 di->di_printf("[%c - unknown]", *f_ptr); 494 break; 495 } 496 if (*(f_ptr+1) >= 'A' && *(f_ptr+1) <= 'Z') 497 ++f_ptr; 498 else if (*(++f_ptr)) { 499 ++fmt; 500 if (fmt == 1) 501 di->di_printf("\t"); 502 else 503 di->di_printf(", "); 504 } 505 }; 506 507 di->di_printf("\n"); 508 509 return(loc + INSN_SIZE); 510 } 511 512 513 static void 514 disasm_register_shift(const disasm_interface_t *di, u_int insn) 515 { 516 di->di_printf("r%d", (insn & 0x0f)); 517 if ((insn & 0x00000ff0) == 0) 518 ; 519 else if ((insn & 0x00000ff0) == 0x00000060) 520 di->di_printf(", rrx"); 521 else { 522 if (insn & 0x10) 523 di->di_printf(", %s r%d", op2_shift(insn), 524 (insn >> 8) & 0x0f); 525 else 526 di->di_printf(", %s #%d", op2_shift(insn), 527 (insn >> 7) & 0x1f); 528 } 529 } 530 531 532 static void 533 disasm_print_reglist(const disasm_interface_t *di, u_int insn) 534 { 535 int loop; 536 int start; 537 int comma; 538 539 di->di_printf("{"); 540 start = -1; 541 comma = 0; 542 543 for (loop = 0; loop < 17; ++loop) { 544 if (start != -1) { 545 if (loop == 16 || !(insn & (1 << loop))) { 546 if (comma) 547 di->di_printf(", "); 548 else 549 comma = 1; 550 if (start == loop - 1) 551 di->di_printf("r%d", start); 552 else 553 di->di_printf("r%d-r%d", start, loop - 1); 554 start = -1; 555 } 556 } else { 557 if (insn & (1 << loop)) 558 start = loop; 559 } 560 } 561 di->di_printf("}"); 562 563 if (insn & (1 << 22)) 564 di->di_printf("^"); 565 } 566 567 static void 568 disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc) 569 { 570 if ((((insn >> 16) & 0x0f) == 15) && ((insn & (1 << 21)) == 0) 571 && ((insn & (1 << 24)) != 0) && ((insn & (1 << 25)) == 0)) { 572 if (insn & 0x00800000) 573 loc += (insn & 0xfff); 574 else 575 loc -= (insn & 0xfff); 576 di->di_printaddr(loc + 8); 577 } else { 578 di->di_printf("[r%d", (insn >> 16) & 0x0f); 579 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 580 581 if (!(insn & 0x00800000)) 582 di->di_printf("-"); 583 if (insn & (1 << 25)) 584 disasm_register_shift(di, insn); 585 else 586 di->di_printf("#0x%04x", insn & 0xfff); 587 if (insn & (1 << 24)) 588 di->di_printf("]"); 589 } 590 } 591 592 593 static void 594 disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc) 595 { 596 if (((insn >> 8) & 0xf) == 1) 597 di->di_printf("f%d, ", (insn >> 12) & 0x07); 598 else 599 di->di_printf("c%d, ", (insn >> 12) & 0x0f); 600 601 di->di_printf("[r%d", (insn >> 16) & 0x0f); 602 603 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 604 605 if (!(insn & (1 << 23))) 606 di->di_printf("-"); 607 608 di->di_printf("#0x%03x", (insn & 0xff) << 2); 609 610 if (insn & (1 << 24)) 611 di->di_printf("]"); 612 613 if (insn & (1 << 21)) 614 di->di_printf("!"); 615 } 616 617 static u_int 618 disassemble_readword(u_int address) 619 { 620 return(*((u_int *)address)); 621 } 622 623 static void 624 disassemble_printaddr(u_int address) 625 { 626 printf("0x%08x", address); 627 } 628 629 static const disasm_interface_t disassemble_di = { 630 disassemble_readword, disassemble_printaddr, printf 631 }; 632 633 void 634 disassemble(u_int address) 635 { 636 637 (void)disasm(&disassemble_di, address, 0); 638 } 639 640 /* End of disassem.c */ 641