1 /* $NetBSD: cpu.c,v 1.37 2002/05/12 15:05:41 ichiro Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master cpu 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 46 #include <sys/param.h> 47 48 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.37 2002/05/12 15:05:41 ichiro Exp $"); 49 50 #include <sys/systm.h> 51 #include <sys/malloc.h> 52 #include <sys/device.h> 53 #include <sys/proc.h> 54 #include <uvm/uvm_extern.h> 55 #include <machine/conf.h> 56 #include <machine/cpu.h> 57 58 #include <arm/cpuconf.h> 59 #include <arm/undefined.h> 60 61 #ifdef ARMFPE 62 #include <machine/bootconfig.h> /* For boot args */ 63 #include <arm/fpe-arm/armfpe.h> 64 #endif 65 66 char cpu_model[256]; 67 68 /* Prototypes */ 69 void identify_arm_cpu(struct device *dv, struct cpu_info *); 70 71 /* 72 * Identify the master (boot) CPU 73 */ 74 75 void 76 cpu_attach(struct device *dv) 77 { 78 int usearmfpe; 79 80 usearmfpe = 1; /* when compiled in, its enabled by default */ 81 82 curcpu()->ci_dev = dv; 83 84 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 85 NULL, dv->dv_xname, "arm700swibug"); 86 87 /* Get the cpu ID from coprocessor 15 */ 88 89 curcpu()->ci_cpuid = cpu_id(); 90 curcpu()->ci_cputype = curcpu()->ci_cpuid & CPU_ID_CPU_MASK; 91 curcpu()->ci_cpurev = curcpu()->ci_cpuid & CPU_ID_REVISION_MASK; 92 93 identify_arm_cpu(dv, curcpu()); 94 95 if (curcpu()->ci_cputype == CPU_ID_SA110 && curcpu()->ci_cpurev < 3) { 96 printf("%s: SA-110 with bugged STM^ instruction\n", 97 dv->dv_xname); 98 } 99 100 #ifdef CPU_ARM8 101 if ((curcpu()->ci_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 102 int clock = arm8_clock_config(0, 0); 103 char *fclk; 104 printf("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 105 printf(" clock:%s", (clock & 1) ? " dynamic" : ""); 106 printf("%s", (clock & 2) ? " sync" : ""); 107 switch ((clock >> 2) & 3) { 108 case 0: 109 fclk = "bus clock"; 110 break; 111 case 1: 112 fclk = "ref clock"; 113 break; 114 case 3: 115 fclk = "pll"; 116 break; 117 default: 118 fclk = "illegal"; 119 break; 120 } 121 printf(" fclk source=%s\n", fclk); 122 } 123 #endif 124 125 #ifdef ARMFPE 126 /* 127 * Ok now we test for an FPA 128 * At this point no floating point emulator has been installed. 129 * This means any FP instruction will cause undefined exception. 130 * We install a temporay coproc 1 handler which will modify 131 * undefined_test if it is called. 132 * We then try to read the FP status register. If undefined_test 133 * has been decremented then the instruction was not handled by 134 * an FPA so we know the FPA is missing. If undefined_test is 135 * still 1 then we know the instruction was handled by an FPA. 136 * We then remove our test handler and look at the 137 * FP status register for identification. 138 */ 139 140 /* 141 * Ok if ARMFPE is defined and the boot options request the 142 * ARM FPE then it will be installed as the FPE. 143 * This is just while I work on integrating the new FPE. 144 * It means the new FPE gets installed if compiled int (ARMFPE 145 * defined) and also gives me a on/off option when I boot in 146 * case the new FPE is causing panics. 147 */ 148 149 150 if (boot_args) 151 get_bootconf_option(boot_args, "armfpe", 152 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 153 if (usearmfpe) 154 initialise_arm_fpe(); 155 #endif 156 } 157 158 enum cpu_class { 159 CPU_CLASS_NONE, 160 CPU_CLASS_ARM2, 161 CPU_CLASS_ARM2AS, 162 CPU_CLASS_ARM3, 163 CPU_CLASS_ARM6, 164 CPU_CLASS_ARM7, 165 CPU_CLASS_ARM7TDMI, 166 CPU_CLASS_ARM8, 167 CPU_CLASS_ARM9TDMI, 168 CPU_CLASS_ARM9ES, 169 CPU_CLASS_SA1, 170 CPU_CLASS_XSCALE, 171 CPU_CLASS_ARM10E 172 }; 173 174 static const char *generic_steppings[16] = { 175 "rev 0", "rev 1", "rev 2", "rev 3", 176 "rev 4", "rev 5", "rev 6", "rev 7", 177 "rev 8", "rev 9", "rev 10", "rev 11", 178 "rev 12", "rev 13", "rev 14", "rev 15", 179 }; 180 181 static const char *sa110_steppings[16] = { 182 "rev 0", "step J", "step K", "step S", 183 "step T", "rev 5", "rev 6", "rev 7", 184 "rev 8", "rev 9", "rev 10", "rev 11", 185 "rev 12", "rev 13", "rev 14", "rev 15", 186 }; 187 188 static const char *sa1100_steppings[16] = { 189 "rev 0", "step B", "step C", "rev 3", 190 "rev 4", "rev 5", "rev 6", "rev 7", 191 "step D", "step E", "rev 10" "step G", 192 "rev 12", "rev 13", "rev 14", "rev 15", 193 }; 194 195 static const char *sa1110_steppings[16] = { 196 "step A-0", "rev 1", "rev 2", "rev 3", 197 "step B-0", "step B-1", "step B-2", "step B-3", 198 "step B-4", "step B-5", "rev 10", "rev 11", 199 "rev 12", "rev 13", "rev 14", "rev 15", 200 }; 201 202 static const char *ixp12x0_steppings[16] = { 203 "(IXP1200 step A)", "(IXP1200 step B)", 204 "rev 2", "(IXP1200 step C)", 205 "(IXP1200 step D)", "(IXP1240/1250 step A)", 206 "(IXP1240 step B)", "(IXP1250 step B)", 207 "rev 8", "rev 9", "rev 10", "rev 11", 208 "rev 12", "rev 13", "rev 14", "rev 15", 209 }; 210 211 static const char *xscale_steppings[16] = { 212 "step A-0", "step A-1", "step B-0", "step C-0", 213 "rev 4", "rev 5", "rev 6", "rev 7", 214 "rev 8", "rev 9", "rev 10", "rev 11", 215 "rev 12", "rev 13", "rev 14", "rev 15", 216 }; 217 218 static const char *pxa2x0_steppings[16] = { 219 "step A-0", "step A-1", "step B-0", "step B-1", 220 "rev 4", "rev 5", "rev 6", "rev 7", 221 "rev 8", "rev 9", "rev 10", "rev 11", 222 "rev 12", "rev 13", "rev 14", "rev 15", 223 }; 224 225 struct cpuidtab { 226 u_int32_t cpuid; 227 enum cpu_class cpu_class; 228 const char *cpu_name; 229 const char **cpu_steppings; 230 }; 231 232 const struct cpuidtab cpuids[] = { 233 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 234 generic_steppings }, 235 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 236 generic_steppings }, 237 238 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 239 generic_steppings }, 240 241 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 242 generic_steppings }, 243 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 244 generic_steppings }, 245 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 246 generic_steppings }, 247 248 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 249 generic_steppings }, 250 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 251 generic_steppings }, 252 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 253 generic_steppings }, 254 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 255 generic_steppings }, 256 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 257 generic_steppings }, 258 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 259 generic_steppings }, 260 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 261 generic_steppings }, 262 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 263 generic_steppings }, 264 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 265 generic_steppings }, 266 267 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 268 generic_steppings }, 269 270 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 271 generic_steppings }, 272 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 273 generic_steppings }, 274 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 275 generic_steppings }, 276 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 277 generic_steppings }, 278 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 279 generic_steppings }, 280 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 281 generic_steppings }, 282 283 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 284 sa110_steppings }, 285 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 286 sa1100_steppings }, 287 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 288 sa1110_steppings }, 289 290 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 291 ixp12x0_steppings }, 292 293 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 294 xscale_steppings }, 295 296 { CPU_ID_80321, CPU_CLASS_XSCALE, "i80321", 297 xscale_steppings }, 298 299 { CPU_ID_PXA250, CPU_CLASS_XSCALE, "PXA250", 300 pxa2x0_steppings }, 301 { CPU_ID_PXA210, CPU_CLASS_XSCALE, "PXA210", 302 pxa2x0_steppings }, /* XXX */ 303 304 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022ES", 305 generic_steppings }, 306 307 { 0, CPU_CLASS_NONE, NULL, NULL } 308 }; 309 310 struct cpu_classtab { 311 const char *class_name; 312 const char *class_option; 313 }; 314 315 const struct cpu_classtab cpu_classes[] = { 316 { "unknown", NULL }, /* CPU_CLASS_NONE */ 317 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 318 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 319 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 320 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 321 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 322 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 323 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 324 { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ 325 { "ARM9E-S", NULL }, /* CPU_CLASS_ARM9ES */ 326 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 327 { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 328 { "ARM10E", NULL }, /* CPU_CLASS_ARM10E */ 329 }; 330 331 /* 332 * Report the type of the specifed arm processor. This uses the generic and 333 * arm specific information in the cpu structure to identify the processor. 334 * The remaining fields in the cpu structure are filled in appropriately. 335 */ 336 337 static const char *wtnames[] = { 338 "write-through", 339 "write-back", 340 "write-back", 341 "**unknown 3**", 342 "**unknown 4**", 343 "write-back-locking", /* XXX XScale-specific? */ 344 "write-back-locking-A", 345 "write-back-locking-B", 346 "**unknown 8**", 347 "**unknown 9**", 348 "**unknown 10**", 349 "**unknown 11**", 350 "**unknown 12**", 351 "**unknown 13**", 352 "**unknown 14**", 353 "**unknown 15**", 354 }; 355 356 void 357 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 358 { 359 u_int cpuid; 360 enum cpu_class cpu_class; 361 int i; 362 363 cpuid = ci->ci_cpuid; 364 365 if (cpuid == 0) { 366 printf("Processor failed probe - no CPU ID\n"); 367 return; 368 } 369 370 for (i = 0; cpuids[i].cpuid != 0; i++) 371 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 372 cpu_class = cpuids[i].cpu_class; 373 sprintf(cpu_model, "%s %s (%s core)", 374 cpuids[i].cpu_name, 375 cpuids[i].cpu_steppings[cpuid & 376 CPU_ID_REVISION_MASK], 377 cpu_classes[cpu_class].class_name); 378 break; 379 } 380 381 if (cpuids[i].cpuid == 0) 382 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 383 384 printf(": %s\n", cpu_model); 385 386 printf("%s:", dv->dv_xname); 387 388 switch (cpu_class) { 389 case CPU_CLASS_ARM6: 390 case CPU_CLASS_ARM7: 391 case CPU_CLASS_ARM7TDMI: 392 case CPU_CLASS_ARM8: 393 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 394 printf(" IDC disabled"); 395 else 396 printf(" IDC enabled"); 397 break; 398 case CPU_CLASS_ARM9TDMI: 399 case CPU_CLASS_SA1: 400 case CPU_CLASS_XSCALE: 401 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 402 printf(" DC disabled"); 403 else 404 printf(" DC enabled"); 405 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 406 printf(" IC disabled"); 407 else 408 printf(" IC enabled"); 409 break; 410 default: 411 break; 412 } 413 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 414 printf(" WB disabled"); 415 else 416 printf(" WB enabled"); 417 418 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 419 printf(" LABT"); 420 else 421 printf(" EABT"); 422 423 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 424 printf(" branch prediction enabled"); 425 426 printf("\n"); 427 428 /* Print cache info. */ 429 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 430 goto skip_pcache; 431 432 if (arm_pcache_unified) { 433 printf("%s: %dKB/%dB %d-way %s unified cache\n", 434 dv->dv_xname, arm_pdcache_size / 1024, 435 arm_pdcache_line_size, arm_pdcache_ways, 436 wtnames[arm_pcache_type]); 437 } else { 438 printf("%s: %dKB/%dB %d-way Instruction cache\n", 439 dv->dv_xname, arm_picache_size / 1024, 440 arm_picache_line_size, arm_picache_ways); 441 printf("%s: %dKB/%dB %d-way %s Data cache\n", 442 dv->dv_xname, arm_pdcache_size / 1024, 443 arm_pdcache_line_size, arm_pdcache_ways, 444 wtnames[arm_pcache_type]); 445 } 446 447 skip_pcache: 448 449 switch (cpu_class) { 450 #ifdef CPU_ARM2 451 case CPU_CLASS_ARM2: 452 #endif 453 #ifdef CPU_ARM250 454 case CPU_CLASS_ARM2AS: 455 #endif 456 #ifdef CPU_ARM3 457 case CPU_CLASS_ARM3: 458 #endif 459 #ifdef CPU_ARM6 460 case CPU_CLASS_ARM6: 461 #endif 462 #ifdef CPU_ARM7 463 case CPU_CLASS_ARM7: 464 #endif 465 #ifdef CPU_ARM7TDMI 466 case CPU_CLASS_ARM7TDMI: 467 #endif 468 #ifdef CPU_ARM8 469 case CPU_CLASS_ARM8: 470 #endif 471 #ifdef CPU_ARM9 472 case CPU_CLASS_ARM9TDMI: 473 #endif 474 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 475 defined(CPU_SA1110) || defined(CPU_IXP12X0) 476 case CPU_CLASS_SA1: 477 #endif 478 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 479 defined(CPU_XSCALE_PXA2X0) 480 case CPU_CLASS_XSCALE: 481 #endif 482 break; 483 default: 484 if (cpu_classes[cpu_class].class_option != NULL) 485 printf("%s: %s does not fully support this CPU." 486 "\n", dv->dv_xname, ostype); 487 else { 488 printf("%s: This kernel does not fully support " 489 "this CPU.\n", dv->dv_xname); 490 printf("%s: Recompile with \"options %s\" to " 491 "correct this.\n", dv->dv_xname, 492 cpu_classes[cpu_class].class_option); 493 } 494 break; 495 } 496 497 } 498 499 /* End of cpu.c */ 500