1 /* $Id: at91emac.c,v 1.9 2010/04/05 07:19:29 joerg Exp $ */ 2 /* $NetBSD: at91emac.c,v 1.9 2010/04/05 07:19:29 joerg Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Embedtronics Oy 6 * All rights reserved. 7 * 8 * Based on arch/arm/ep93xx/epe.c 9 * 10 * Copyright (c) 2004 Jesse Off 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: at91emac.c,v 1.9 2010/04/05 07:19:29 joerg Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ioctl.h> 42 #include <sys/kernel.h> 43 #include <sys/proc.h> 44 #include <sys/malloc.h> 45 #include <sys/time.h> 46 #include <sys/device.h> 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 52 #include <arm/cpufunc.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_types.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #include <dev/mii/mii.h> 61 #include <dev/mii/miivar.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/if_inarp.h> 69 #endif 70 71 #ifdef NS 72 #include <netns/ns.h> 73 #include <netns/ns_if.h> 74 #endif 75 76 #include <net/bpf.h> 77 #include <net/bpfdesc.h> 78 79 #ifdef IPKDB_AT91 // @@@ 80 #include <ipkdb/ipkdb.h> 81 #endif 82 83 #include <arm/at91/at91var.h> 84 #include <arm/at91/at91emacreg.h> 85 #include <arm/at91/at91emacvar.h> 86 87 #define DEFAULT_MDCDIV 32 88 89 #ifndef EMAC_FAST 90 #define EMAC_FAST 91 #endif 92 93 #ifndef EMAC_FAST 94 #define EMAC_READ(x) \ 95 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 96 #define EMAC_WRITE(x, y) \ 97 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 98 #else 99 #define EMAC_READ(x) ETHREG(x) 100 #define EMAC_WRITE(x, y) ETHREG(x) = (y) 101 #endif /* ! EMAC_FAST */ 102 103 static int emac_match(device_t, cfdata_t, void *); 104 static void emac_attach(device_t, device_t, void *); 105 static void emac_init(struct emac_softc *); 106 static int emac_intr(void* arg); 107 static int emac_gctx(struct emac_softc *); 108 static int emac_mediachange(struct ifnet *); 109 static void emac_mediastatus(struct ifnet *, struct ifmediareq *); 110 int emac_mii_readreg (device_t, int, int); 111 void emac_mii_writereg (device_t, int, int, int); 112 void emac_statchg (device_t ); 113 void emac_tick (void *); 114 static int emac_ifioctl (struct ifnet *, u_long, void *); 115 static void emac_ifstart (struct ifnet *); 116 static void emac_ifwatchdog (struct ifnet *); 117 static int emac_ifinit (struct ifnet *); 118 static void emac_ifstop (struct ifnet *, int); 119 static void emac_setaddr (struct ifnet *); 120 121 CFATTACH_DECL(at91emac, sizeof(struct emac_softc), 122 emac_match, emac_attach, NULL, NULL); 123 124 #ifdef EMAC_DEBUG 125 int emac_debug = EMAC_DEBUG; 126 #define DPRINTFN(n,fmt) if (emac_debug >= (n)) printf fmt 127 #else 128 #define DPRINTFN(n,fmt) 129 #endif 130 131 static int 132 emac_match(device_t parent, cfdata_t match, void *aux) 133 { 134 if (strcmp(match->cf_name, "at91emac") == 0) 135 return 2; 136 return 0; 137 } 138 139 static void 140 emac_attach(device_t parent, device_t self, void *aux) 141 { 142 struct emac_softc *sc = device_private(self); 143 struct at91bus_attach_args *sa = aux; 144 prop_data_t enaddr; 145 uint32_t u; 146 147 printf("\n"); 148 sc->sc_dev = self; 149 sc->sc_iot = sa->sa_iot; 150 sc->sc_pid = sa->sa_pid; 151 sc->sc_dmat = sa->sa_dmat; 152 153 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &sc->sc_ioh)) 154 panic("%s: Cannot map registers", device_xname(self)); 155 156 /* enable peripheral clock */ 157 at91_peripheral_clock(sc->sc_pid, 1); 158 159 /* configure emac: */ 160 EMAC_WRITE(ETH_CTL, 0); // disable everything 161 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 162 EMAC_WRITE(ETH_RBQP, 0); // clear receive 163 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 164 EMAC_WRITE(ETH_TCR, 0); // send nothing 165 //(void)EMAC_READ(ETH_ISR); 166 u = EMAC_READ(ETH_TSR); 167 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 168 | ETH_TSR_IDLE | ETH_TSR_RLE 169 | ETH_TSR_COL|ETH_TSR_OVR))); 170 u = EMAC_READ(ETH_RSR); 171 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 172 173 /* Fetch the Ethernet address from property if set. */ 174 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 175 176 if (enaddr != NULL) { 177 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 178 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 179 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 180 ETHER_ADDR_LEN); 181 } else { 182 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 183 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 184 }; 185 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 186 } 187 188 at91_intr_establish(sc->sc_pid, IPL_NET, INTR_HIGH_LEVEL, emac_intr, sc); 189 emac_init(sc); 190 } 191 192 static int 193 emac_gctx(struct emac_softc *sc) 194 { 195 struct ifnet * ifp = &sc->sc_ec.ec_if; 196 u_int32_t tsr; 197 198 tsr = EMAC_READ(ETH_TSR); 199 if (!(tsr & ETH_TSR_BNQ)) { 200 // no space left 201 return 0; 202 } 203 204 // free sent frames 205 while (sc->txqc > (tsr & ETH_TSR_IDLE ? 0 : 1)) { 206 int i = sc->txqi % TX_QLEN; 207 bus_dmamap_sync(sc->sc_dmat, sc->txq[i].m_dmamap, 0, 208 sc->txq[i].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 209 bus_dmamap_unload(sc->sc_dmat, sc->txq[i].m_dmamap); 210 m_freem(sc->txq[i].m); 211 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", __FUNCTION__, i, sc->txq[i].m, sc->txqc)); 212 sc->txq[i].m = NULL; 213 sc->txqi = (i + 1) % TX_QLEN; 214 sc->txqc--; 215 } 216 217 // mark we're free 218 if (ifp->if_flags & IFF_OACTIVE) { 219 ifp->if_flags &= ~IFF_OACTIVE; 220 /* Disable transmit-buffer-free interrupt */ 221 /*EMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 222 } 223 224 return 1; 225 } 226 227 static int 228 emac_intr(void *arg) 229 { 230 struct emac_softc *sc = (struct emac_softc *)arg; 231 struct ifnet * ifp = &sc->sc_ec.ec_if; 232 u_int32_t imr, isr, rsr, ctl; 233 int bi; 234 235 imr = ~EMAC_READ(ETH_IMR); 236 if (!(imr & (ETH_ISR_RCOM|ETH_ISR_TBRE|ETH_ISR_TIDLE|ETH_ISR_RBNA|ETH_ISR_ROVR))) { 237 // interrupt not enabled, can't be us 238 return 0; 239 } 240 241 isr = EMAC_READ(ETH_ISR) & imr; 242 rsr = EMAC_READ(ETH_RSR); // get receive status register 243 244 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 245 246 if (isr & ETH_ISR_RBNA) { // out of receive buffers 247 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 248 ctl = EMAC_READ(ETH_CTL); // get current control register value 249 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 250 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 251 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 252 ifp->if_ierrors++; 253 ifp->if_ipackets++; 254 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 255 } 256 if (isr & ETH_ISR_ROVR) { 257 EMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 258 ifp->if_ierrors++; 259 ifp->if_ipackets++; 260 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 261 } 262 263 if (isr & ETH_ISR_RCOM) { // packet has been received! 264 uint32_t nfo; 265 // @@@ if memory is NOT coherent, then we're in trouble @@@@ 266 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 267 // printf("## RDSC[%i].ADDR=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Addr); 268 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 269 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 270 int fl; 271 struct mbuf *m; 272 273 nfo = sc->RDSC[bi].Info; 274 fl = (nfo & ETH_RDSC_I_LEN) - 4; 275 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 276 277 MGETHDR(m, M_DONTWAIT, MT_DATA); 278 if (m != NULL) MCLGET(m, M_DONTWAIT); 279 if (m != NULL && (m->m_flags & M_EXT)) { 280 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 281 MCLBYTES, BUS_DMASYNC_POSTREAD); 282 bus_dmamap_unload(sc->sc_dmat, 283 sc->rxq[bi].m_dmamap); 284 sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 285 sc->rxq[bi].m->m_pkthdr.len = 286 sc->rxq[bi].m->m_len = fl; 287 bpf_mtap(ifp, sc->rxq[bi].m); 288 DPRINTFN(2,("received %u bytes packet\n", fl)); 289 (*ifp->if_input)(ifp, sc->rxq[bi].m); 290 if (mtod(m, intptr_t) & 3) { 291 m_adj(m, mtod(m, intptr_t) & 3); 292 } 293 sc->rxq[bi].m = m; 294 bus_dmamap_load(sc->sc_dmat, 295 sc->rxq[bi].m_dmamap, 296 m->m_ext.ext_buf, MCLBYTES, 297 NULL, BUS_DMA_NOWAIT); 298 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 299 MCLBYTES, BUS_DMASYNC_PREREAD); 300 sc->RDSC[bi].Info = 0; 301 sc->RDSC[bi].Addr = 302 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 303 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 304 } else { 305 /* Drop packets until we can get replacement 306 * empty mbufs for the RXDQ. 307 */ 308 if (m != NULL) { 309 m_freem(m); 310 } 311 ifp->if_ierrors++; 312 } 313 sc->rxqi++; 314 } 315 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 316 } 317 318 if (emac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 319 emac_ifstart(ifp); 320 } 321 #if 0 // reloop 322 irq = EMAC_READ(IntStsC); 323 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 324 goto begin; 325 #endif 326 327 return (1); 328 } 329 330 331 static void 332 emac_init(struct emac_softc *sc) 333 { 334 bus_dma_segment_t segs; 335 void *addr; 336 int rsegs, err, i; 337 struct ifnet * ifp = &sc->sc_ec.ec_if; 338 uint32_t u; 339 #if 0 340 int mdcdiv = DEFAULT_MDCDIV; 341 #endif 342 343 callout_init(&sc->emac_tick_ch, 0); 344 345 // ok... 346 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 347 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 348 EMAC_WRITE(ETH_RBQP, 0); // clear receive 349 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 350 EMAC_WRITE(ETH_TCR, 0); // send nothing 351 // (void)EMAC_READ(ETH_ISR); 352 u = EMAC_READ(ETH_TSR); 353 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 354 | ETH_TSR_IDLE | ETH_TSR_RLE 355 | ETH_TSR_COL|ETH_TSR_OVR))); 356 u = EMAC_READ(ETH_RSR); 357 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 358 359 /* configure EMAC */ 360 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 361 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); 362 #if 0 363 if (device_cfdata(&sc->sc_dev)->cf_flags) 364 mdcdiv = device_cfdata(&sc->sc_dev)->cf_flags; 365 #endif 366 /* set ethernet address */ 367 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 368 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 369 | (sc->sc_enaddr[0])); 370 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 371 | (sc->sc_enaddr[4])); 372 EMAC_WRITE(ETH_SA2L, 0); 373 EMAC_WRITE(ETH_SA2H, 0); 374 EMAC_WRITE(ETH_SA3L, 0); 375 EMAC_WRITE(ETH_SA3H, 0); 376 EMAC_WRITE(ETH_SA4L, 0); 377 EMAC_WRITE(ETH_SA4H, 0); 378 379 /* Allocate a page of memory for receive queue descriptors */ 380 sc->rbqlen = (ETH_RDSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 381 sc->rbqlen *= PAGE_SIZE; 382 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 383 384 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 385 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 386 &segs, 1, &rsegs, BUS_DMA_WAITOK); 387 if (err == 0) { 388 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 389 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 390 &sc->rbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 391 } 392 if (err == 0) { 393 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 394 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 395 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 396 &sc->rbqpage_dmamap); 397 } 398 if (err == 0) { 399 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 400 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 401 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 402 } 403 if (err != 0) { 404 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 405 } 406 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 407 408 memset(sc->rbqpage, 0, sc->rbqlen); 409 410 /* Set up pointers to start of each queue in kernel addr space. 411 * Each descriptor queue or status queue entry uses 2 words 412 */ 413 sc->RDSC = (void*)sc->rbqpage; 414 415 /* Populate the RXQ with mbufs */ 416 sc->rxqi = 0; 417 for(i = 0; i < RX_QLEN; i++) { 418 struct mbuf *m; 419 420 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 421 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 422 if (err) { 423 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 424 } 425 MGETHDR(m, M_WAIT, MT_DATA); 426 MCLGET(m, M_WAIT); 427 sc->rxq[i].m = m; 428 if (mtod(m, intptr_t) & 3) { 429 m_adj(m, mtod(m, intptr_t) & 3); 430 } 431 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 432 m->m_ext.ext_buf, MCLBYTES, NULL, 433 BUS_DMA_WAITOK); 434 if (err) { 435 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 436 } 437 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 438 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 439 sc->RDSC[i].Info = 0; 440 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 441 MCLBYTES, BUS_DMASYNC_PREREAD); 442 } 443 444 /* prepare transmit queue */ 445 for (i = 0; i < TX_QLEN; i++) { 446 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 447 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 448 &sc->txq[i].m_dmamap); 449 if (err) 450 panic("ARGH #1"); 451 sc->txq[i].m = NULL; 452 } 453 454 /* Program each queue's start addr, cur addr, and len registers 455 * with the physical addresses. 456 */ 457 bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, 458 BUS_DMASYNC_PREREAD); 459 addr = (void *)sc->rbqpage_dmamap->dm_segs[0].ds_addr; 460 EMAC_WRITE(ETH_RBQP, (u_int32_t)addr); 461 462 /* Divide HCLK by 32 for MDC clock */ 463 sc->sc_mii.mii_ifp = ifp; 464 sc->sc_mii.mii_readreg = emac_mii_readreg; 465 sc->sc_mii.mii_writereg = emac_mii_writereg; 466 sc->sc_mii.mii_statchg = emac_statchg; 467 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, emac_mediachange, 468 emac_mediastatus); 469 mii_attach((device_t )sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 470 MII_OFFSET_ANY, 0); 471 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 472 473 // enable / disable interrupts 474 475 #if 0 476 // enable / disable interrupts 477 EMAC_WRITE(ETH_IDR, -1); 478 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 479 | ETH_ISR_RBNA | ETH_ISR_ROVR); 480 // (void)EMAC_READ(ETH_ISR); // why 481 482 // enable transmitter / receiver 483 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 484 | ETH_CTL_CSR | ETH_CTL_MPE); 485 #endif 486 /* 487 * We can support 802.1Q VLAN-sized frames. 488 */ 489 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 490 491 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 492 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 493 ifp->if_ioctl = emac_ifioctl; 494 ifp->if_start = emac_ifstart; 495 ifp->if_watchdog = emac_ifwatchdog; 496 ifp->if_init = emac_ifinit; 497 ifp->if_stop = emac_ifstop; 498 ifp->if_timer = 0; 499 ifp->if_softc = sc; 500 IFQ_SET_READY(&ifp->if_snd); 501 if_attach(ifp); 502 ether_ifattach(ifp, (sc)->sc_enaddr); 503 } 504 505 static int 506 emac_mediachange(struct ifnet *ifp) 507 { 508 if (ifp->if_flags & IFF_UP) 509 emac_ifinit(ifp); 510 return (0); 511 } 512 513 static void 514 emac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 515 { 516 struct emac_softc *sc = ifp->if_softc; 517 518 mii_pollstat(&sc->sc_mii); 519 ifmr->ifm_active = sc->sc_mii.mii_media_active; 520 ifmr->ifm_status = sc->sc_mii.mii_media_status; 521 } 522 523 524 int 525 emac_mii_readreg(device_t self, int phy, int reg) 526 { 527 struct emac_softc *sc; 528 529 sc = (struct emac_softc *)self; 530 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 531 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 532 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 533 | ETH_MAN_CODE_IEEE802_3)); 534 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 535 return (EMAC_READ(ETH_MAN) & ETH_MAN_DATA); 536 } 537 538 void 539 emac_mii_writereg(device_t self, int phy, int reg, int val) 540 { 541 struct emac_softc *sc; 542 sc = (struct emac_softc *)self; 543 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 544 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 545 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 546 | ETH_MAN_CODE_IEEE802_3 547 | (val & ETH_MAN_DATA))); 548 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 549 } 550 551 552 void 553 emac_statchg(device_t self) 554 { 555 struct emac_softc *sc = (struct emac_softc *)self; 556 u_int32_t reg; 557 558 /* 559 * We must keep the MAC and the PHY in sync as 560 * to the status of full-duplex! 561 */ 562 reg = EMAC_READ(ETH_CFG); 563 if (sc->sc_mii.mii_media_active & IFM_FDX) 564 reg |= ETH_CFG_FD; 565 else 566 reg &= ~ETH_CFG_FD; 567 EMAC_WRITE(ETH_CFG, reg); 568 } 569 570 void 571 emac_tick(void *arg) 572 { 573 struct emac_softc* sc = (struct emac_softc *)arg; 574 struct ifnet * ifp = &sc->sc_ec.ec_if; 575 int s; 576 u_int32_t misses; 577 578 ifp->if_collisions += EMAC_READ(ETH_SCOL) + EMAC_READ(ETH_MCOL); 579 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 580 misses = EMAC_READ(ETH_DRFC); 581 if (misses > 0) 582 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses); 583 584 s = splnet(); 585 if (emac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 586 emac_ifstart(ifp); 587 } 588 splx(s); 589 590 mii_tick(&sc->sc_mii); 591 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 592 } 593 594 595 static int 596 emac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 597 { 598 struct emac_softc *sc = ifp->if_softc; 599 struct ifreq *ifr = (struct ifreq *)data; 600 int s, error; 601 602 s = splnet(); 603 switch(cmd) { 604 case SIOCSIFMEDIA: 605 case SIOCGIFMEDIA: 606 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 607 break; 608 default: 609 error = ether_ioctl(ifp, cmd, data); 610 if (error == ENETRESET) { 611 if (ifp->if_flags & IFF_RUNNING) 612 emac_setaddr(ifp); 613 error = 0; 614 } 615 } 616 splx(s); 617 return error; 618 } 619 620 static void 621 emac_ifstart(struct ifnet *ifp) 622 { 623 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 624 struct mbuf *m; 625 bus_dma_segment_t *segs; 626 int s, bi, err, nsegs; 627 628 s = splnet(); 629 start: 630 if (emac_gctx(sc) == 0) { 631 /* Enable transmit-buffer-free interrupt */ 632 EMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 633 ifp->if_flags |= IFF_OACTIVE; 634 ifp->if_timer = 10; 635 splx(s); 636 return; 637 } 638 639 ifp->if_timer = 0; 640 641 IFQ_POLL(&ifp->if_snd, m); 642 if (m == NULL) { 643 splx(s); 644 return; 645 } 646 //more: 647 bi = (sc->txqi + sc->txqc) % TX_QLEN; 648 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 649 BUS_DMA_NOWAIT)) || 650 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 651 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 652 /* Copy entire mbuf chain to new single */ 653 struct mbuf *mn; 654 655 if (err == 0) 656 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 657 658 MGETHDR(mn, M_DONTWAIT, MT_DATA); 659 if (mn == NULL) goto stop; 660 if (m->m_pkthdr.len > MHLEN) { 661 MCLGET(mn, M_DONTWAIT); 662 if ((mn->m_flags & M_EXT) == 0) { 663 m_freem(mn); 664 goto stop; 665 } 666 } 667 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 668 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 669 IFQ_DEQUEUE(&ifp->if_snd, m); 670 m_freem(m); 671 m = mn; 672 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 673 BUS_DMA_NOWAIT); 674 } else { 675 IFQ_DEQUEUE(&ifp->if_snd, m); 676 } 677 678 bpf_mtap(ifp, m); 679 680 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 681 segs = sc->txq[bi].m_dmamap->dm_segs; 682 if (nsegs > 1) { 683 panic("#### ARGH #2"); 684 } 685 686 sc->txq[bi].m = m; 687 sc->txqc++; 688 689 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 690 (unsigned)m->m_pkthdr.len)); 691 #ifdef DIAGNOSTIC 692 if (sc->txqc > TX_QLEN) { 693 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 694 } 695 #endif 696 697 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 698 sc->txq[bi].m_dmamap->dm_mapsize, 699 BUS_DMASYNC_PREWRITE); 700 701 EMAC_WRITE(ETH_TAR, segs->ds_addr); 702 EMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 703 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 704 goto start; 705 stop: 706 707 splx(s); 708 return; 709 } 710 711 static void 712 emac_ifwatchdog(struct ifnet *ifp) 713 { 714 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 715 716 if ((ifp->if_flags & IFF_RUNNING) == 0) 717 return; 718 printf("%s: device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 719 device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG)); 720 } 721 722 static int 723 emac_ifinit(struct ifnet *ifp) 724 { 725 struct emac_softc *sc = ifp->if_softc; 726 int s = splnet(); 727 728 callout_stop(&sc->emac_tick_ch); 729 730 // enable interrupts 731 EMAC_WRITE(ETH_IDR, -1); 732 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 733 | ETH_ISR_RBNA | ETH_ISR_ROVR); 734 735 // enable transmitter / receiver 736 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 737 | ETH_CTL_CSR | ETH_CTL_MPE); 738 739 mii_mediachg(&sc->sc_mii); 740 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 741 ifp->if_flags |= IFF_RUNNING; 742 splx(s); 743 return 0; 744 } 745 746 static void 747 emac_ifstop(struct ifnet *ifp, int disable) 748 { 749 // u_int32_t u; 750 struct emac_softc *sc = ifp->if_softc; 751 752 #if 0 753 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 754 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 755 // EMAC_WRITE(ETH_RBQP, 0); // clear receive 756 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 757 EMAC_WRITE(ETH_TCR, 0); // send nothing 758 // (void)EMAC_READ(ETH_ISR); 759 u = EMAC_READ(ETH_TSR); 760 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 761 | ETH_TSR_IDLE | ETH_TSR_RLE 762 | ETH_TSR_COL|ETH_TSR_OVR))); 763 u = EMAC_READ(ETH_RSR); 764 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 765 #endif 766 callout_stop(&sc->emac_tick_ch); 767 768 /* Down the MII. */ 769 mii_down(&sc->sc_mii); 770 771 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 772 ifp->if_timer = 0; 773 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 774 } 775 776 static void 777 emac_setaddr(struct ifnet *ifp) 778 { 779 struct emac_softc *sc = ifp->if_softc; 780 struct ethercom *ac = &sc->sc_ec; 781 struct ether_multi *enm; 782 struct ether_multistep step; 783 u_int8_t ias[3][ETHER_ADDR_LEN]; 784 u_int32_t h, nma = 0, hashes[2] = { 0, 0 }; 785 u_int32_t ctl = EMAC_READ(ETH_CTL); 786 u_int32_t cfg = EMAC_READ(ETH_CFG); 787 788 /* disable receiver temporarily */ 789 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 790 791 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 792 793 if (ifp->if_flags & IFF_PROMISC) { 794 cfg |= ETH_CFG_CAF; 795 } else { 796 cfg &= ~ETH_CFG_CAF; 797 } 798 799 // ETH_CFG_BIG? 800 801 ifp->if_flags &= ~IFF_ALLMULTI; 802 803 ETHER_FIRST_MULTI(step, ac, enm); 804 while (enm != NULL) { 805 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 806 /* 807 * We must listen to a range of multicast addresses. 808 * For now, just accept all multicasts, rather than 809 * trying to set only those filter bits needed to match 810 * the range. (At this time, the only use of address 811 * ranges is for IP multicast routing, for which the 812 * range is big enough to require all bits set.) 813 */ 814 cfg |= ETH_CFG_CAF; 815 hashes[0] = 0xffffffffUL; 816 hashes[1] = 0xffffffffUL; 817 ifp->if_flags |= IFF_ALLMULTI; 818 nma = 0; 819 break; 820 } 821 822 if (nma < 3) { 823 /* We can program 3 perfect address filters for mcast */ 824 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 825 } else { 826 /* 827 * XXX: Datasheet is not very clear here, I'm not sure 828 * if I'm doing this right. --joff 829 */ 830 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 831 832 /* Just want the 6 most-significant bits. */ 833 h = h >> 26; 834 835 hashes[ h / 32 ] |= (1 << (h % 32)); 836 cfg |= ETH_CFG_MTI; 837 } 838 ETHER_NEXT_MULTI(step, enm); 839 nma++; 840 } 841 842 // program... 843 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 844 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 845 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 846 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 847 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 848 | (sc->sc_enaddr[0])); 849 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 850 | (sc->sc_enaddr[4])); 851 if (nma > 1) { 852 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 853 ias[0][0], ias[0][1], ias[0][2], 854 ias[0][3], ias[0][4], ias[0][5])); 855 EMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 856 | (ias[0][2] << 16) | (ias[0][1] << 8) 857 | (ias[0][0])); 858 EMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 859 | (ias[0][5])); 860 } 861 if (nma > 2) { 862 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 863 ias[1][0], ias[1][1], ias[1][2], 864 ias[1][3], ias[1][4], ias[1][5])); 865 EMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 866 | (ias[1][2] << 16) | (ias[1][1] << 8) 867 | (ias[1][0])); 868 EMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 869 | (ias[1][5])); 870 } 871 if (nma > 3) { 872 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 873 ias[2][0], ias[2][1], ias[2][2], 874 ias[2][3], ias[2][4], ias[2][5])); 875 EMAC_WRITE(ETH_SA3L, (ias[2][3] << 24) 876 | (ias[2][2] << 16) | (ias[2][1] << 8) 877 | (ias[2][0])); 878 EMAC_WRITE(ETH_SA3H, (ias[2][4] << 8) 879 | (ias[2][5])); 880 } 881 EMAC_WRITE(ETH_HSH, hashes[0]); 882 EMAC_WRITE(ETH_HSL, hashes[1]); 883 EMAC_WRITE(ETH_CFG, cfg); 884 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 885 } 886