1*30dc3feeSskrll /* $NetBSD: epcomreg.h,v 1.4 2021/11/21 08:25:26 skrll Exp $ */ 24e771f5dSjoff 34e771f5dSjoff /* 44e771f5dSjoff * Copyright (c) 2004 Jesse Off 54e771f5dSjoff * 64e771f5dSjoff * Redistribution and use in source and binary forms, with or without 74e771f5dSjoff * modification, are permitted provided that the following conditions 84e771f5dSjoff * are met: 94e771f5dSjoff * 1. Redistributions of source code must retain the above copyright 104e771f5dSjoff * notice, this list of conditions and the following disclaimer. 114e771f5dSjoff * 2. Redistributions in binary form must reproduce the above copyright 124e771f5dSjoff * notice, this list of conditions and the following disclaimer in the 134e771f5dSjoff * documentation and/or other materials provided with the distribution. 144e771f5dSjoff * 154e771f5dSjoff * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS'' 164e771f5dSjoff * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 174e771f5dSjoff * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 184e771f5dSjoff * ARE DISCLAIMED. IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS 194e771f5dSjoff * HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 204e771f5dSjoff * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 214e771f5dSjoff * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 224e771f5dSjoff * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 234e771f5dSjoff * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 244e771f5dSjoff * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 254e771f5dSjoff * THE POSSIBILITY OF SUCH DAMAGE. 264e771f5dSjoff */ 274e771f5dSjoff 284e771f5dSjoff #ifndef _EPCOMREG_H_ 294e771f5dSjoff #define _EPCOMREG_H_ 304e771f5dSjoff 314e771f5dSjoff #define EPCOM_FREQ 7372800 324e771f5dSjoff #define EPCOMSPEED2BRD(b) ((EPCOM_FREQ / (16 * (b))) - 1) 334e771f5dSjoff 344e771f5dSjoff 354e771f5dSjoff /* UART Data Register */ 364e771f5dSjoff #define EPCOM_Data 0x00000000UL 374e771f5dSjoff 384e771f5dSjoff /* UART Receive Status/Error Clear Register */ 394e771f5dSjoff #define EPCOM_RXSts 0x00000004UL 404e771f5dSjoff #define RXSts_FE 0x01 414e771f5dSjoff #define RXSts_PE 0x02 424e771f5dSjoff #define RXSts_BE 0x04 434e771f5dSjoff #define RXSts_OE 0x08 444e771f5dSjoff 454e771f5dSjoff /* UART Line Control Register High */ 464e771f5dSjoff #define EPCOM_LinCtrlHigh 0x00000008UL 474e771f5dSjoff #define LinCtrlHigh_BRK 0x01 484e771f5dSjoff #define LinCtrlHigh_PEN 0x02 494e771f5dSjoff #define LinCtrlHigh_EPS 0x04 504e771f5dSjoff #define LinCtrlHigh_STP2 0x08 514e771f5dSjoff #define LinCtrlHigh_FEN 0x10 524e771f5dSjoff #define LinCtrlHigh_WLEN 0x60 534e771f5dSjoff 544e771f5dSjoff /* UART Line Control Register Middle */ 554e771f5dSjoff #define EPCOM_LinCtrlMid 0x0000000cUL 564e771f5dSjoff 574e771f5dSjoff /* UART Line Control Register Low */ 584e771f5dSjoff #define EPCOM_LinCtrlLow 0x00000010UL 594e771f5dSjoff 604e771f5dSjoff /* UART control register */ 614e771f5dSjoff #define EPCOM_Ctrl 0x00000014UL 624e771f5dSjoff #define Ctrl_UARTE 0x01 /* UART Enable */ 634e771f5dSjoff #define Ctrl_MSIE 0x08 /* Modem Status Interrupt Enable */ 644e771f5dSjoff #define Ctrl_RIE 0x10 /* Receive Interrupt Enable */ 654e771f5dSjoff #define Ctrl_TIE 0x20 /* Transmit Interrupt Enable */ 664e771f5dSjoff #define Ctrl_RTIE 0x40 /* Receive Timeout Enable */ 674e771f5dSjoff #define Ctrl_LBE 0x80 /* Loopback Enable */ 684e771f5dSjoff 694e771f5dSjoff /* UART Flag register */ 704e771f5dSjoff #define EPCOM_Flag 0x00000018UL 714e771f5dSjoff #define Flag_CTS 0x01 /* Clear To Send status */ 724e771f5dSjoff #define Flag_DSR 0x02 /* Data Set Ready status */ 734e771f5dSjoff #define Flag_DCD 0x04 /* Data Carrier Detect status */ 744e771f5dSjoff #define Flag_BUSY 0x08 /* UART Busy */ 754e771f5dSjoff #define Flag_RXFE 0x10 /* Receive FIFO Empty */ 764e771f5dSjoff #define Flag_TXFF 0x20 /* Transmit FIFO Full */ 774e771f5dSjoff #define Flag_RXFF 0x40 /* Receive FIFO Full */ 784e771f5dSjoff #define Flag_TXFE 0x80 /* Transmit FIFO Empty */ 794e771f5dSjoff 804e771f5dSjoff /* UART Interrupt Identification and Interrupt Clear Register */ 814e771f5dSjoff #define EPCOM_IntIDIntClr 0x0000001cUL 824e771f5dSjoff #define IntIDIntClr_MIS 0x01 /* Modem Interrupt Status */ 834e771f5dSjoff #define IntIDIntClr_RIS 0x01 /* Receive Interrupt Status */ 844e771f5dSjoff #define IntIDIntClr_TIS 0x01 /* Transmit Interrupt Status */ 854e771f5dSjoff #define IntIDIntClr_RTIS 0x01 /* Receive Timeout Interrupt Status */ 864e771f5dSjoff 874e771f5dSjoff /* UART Modem Control Register */ 884e771f5dSjoff #define EPCOM_ModemCtrl 0x00000100UL 894e771f5dSjoff #define ModemCtrl_DTR 0x01 /* DTR output signal */ 904e771f5dSjoff #define ModemCtrl_RTS 0x02 /* RTS output signal */ 914e771f5dSjoff 924e771f5dSjoff /* UART Modem Status Register */ 934e771f5dSjoff #define EPCOM_ModemSts 0x00000104UL 944e771f5dSjoff #define ModemSts_DCTS 0x01 /* Delta CTS */ 954e771f5dSjoff #define ModemSts_DDSR 0x02 /* Delta DSR */ 964e771f5dSjoff #define ModemSts_TERI 0x04 /* Trailing Edge Ring Indicator */ 974e771f5dSjoff #define ModemSts_DDCD 0x08 /* Delta DCD */ 984e771f5dSjoff #define ModemSts_CTS 0x10 /* Inverse CTSn input pin */ 994e771f5dSjoff #define ModemSts_DSR 0x20 /* Inverse of the DSRn pin */ 1004e771f5dSjoff #define ModemSts_RI 0x40 /* Inverse of RI input pin */ 1014e771f5dSjoff #define ModemSts_DCD 0x80 /* Inverse of DCDn input pin */ 1024e771f5dSjoff 1034e771f5dSjoff #endif /* _EPCOMREG_H_ */ 104