1*0ae57f90Smbalmer /* $NetBSD: gemini_reg.h,v 1.9 2009/11/22 19:09:15 mbalmer Exp $ */
2f5d7ce3dSmatt
3f5d7ce3dSmatt #ifndef _ARM_GEMINI_REG_H_
4f5d7ce3dSmatt #define _ARM_GEMINI_REG_H_
5f5d7ce3dSmatt
6f5d7ce3dSmatt /*
7f5d7ce3dSmatt * Register definitions for Gemini SOC
8f5d7ce3dSmatt */
9f5d7ce3dSmatt
10f5d7ce3dSmatt #include "opt_gemini.h"
11f5d7ce3dSmatt #include <machine/endian.h>
12f5d7ce3dSmatt #include <sys/cdefs.h>
13f5d7ce3dSmatt
14f5d7ce3dSmatt #if defined(SL3516)
15f5d7ce3dSmatt /*
16f5d7ce3dSmatt * Gemini SL3516 memory map
17f5d7ce3dSmatt */
18f5d7ce3dSmatt #define GEMINI_SRAM_BASE 0x00000000 /* Internal SRAM */
194a7f1217Scliff /* NOTE: use the SHADOW to avoid conflict w/ DRAM */
20f5d7ce3dSmatt #define GEMINI_SRAM_SIZE 0x10000000 /* 128 MB */
214a7f1217Scliff #define GEMINI_DRAM_BASE 0x00000000 /* DRAM (via DDR Control Module) */
224a7f1217Scliff /* NOTE: this is a shadow of 0x10000000 */
23f5d7ce3dSmatt #define GEMINI_DRAM_SIZE 0x20000000 /* 512 MB */
244a7f1217Scliff /* NOTE: size of addr space, not necessarily populated */
25f5d7ce3dSmatt #define GEMINI_FLASH_BASE 0x30000000 /* DRAM (via DDR Control Module) */
26f5d7ce3dSmatt #define GEMINI_FLASH_SIZE 0x10000000 /* 128 MB */
27f5d7ce3dSmatt
28f5d7ce3dSmatt /*
29f5d7ce3dSmatt * Gemini SL3516 device map
30f5d7ce3dSmatt */
31f5d7ce3dSmatt #define GEMINI_GLOBAL_BASE 0x40000000 /* Global registers */
32f5d7ce3dSmatt #define GEMINI_WATCHDOG_BASE 0x41000000 /* Watch dog timer module */
33f5d7ce3dSmatt #define GEMINI_UART_BASE 0x42000000 /* UART control module */
34f5d7ce3dSmatt #define GEMINI_UART_SIZE 0x20
35f5d7ce3dSmatt #define GEMINI_TIMER_BASE 0x43000000 /* Timer module */
36f5d7ce3dSmatt #define GEMINI_LCD_BASE 0x44000000 /* LCD Interface module */
37f5d7ce3dSmatt #define GEMINI_RTC_BASE 0x45000000 /* Real Time Clock module */
38f5d7ce3dSmatt #define GEMINI_SATA_BASE 0x46000000 /* Serial ATA module */
39f5d7ce3dSmatt #define GEMINI_LPCHC_BASE 0x47000000 /* LPC Hosr Controller module */
407a2b04a9Scliff #define GEMINI_LPCIO_BASE 0x47800000 /* LPC Peripherals IO space */
41f5d7ce3dSmatt #define GEMINI_IC0_BASE 0x48000000 /* Interrupt Control module #0 */
42f5d7ce3dSmatt #define GEMINI_IC1_BASE 0x49000000 /* Interrupt Control module #1 */
43f5d7ce3dSmatt #define GEMINI_SSPC_BASE 0x4a000000 /* Synchronous Serial Port Control module */
44f5d7ce3dSmatt #define GEMINI_PWRC_BASE 0x4b000000 /* Power Control module */
45f5d7ce3dSmatt #define GEMINI_CIR_BASE 0x4c000000 /* CIR Control module */
46f5d7ce3dSmatt #define GEMINI_GPIO0_BASE 0x4d000000 /* GPIO module #0 */
47f5d7ce3dSmatt #define GEMINI_GPIO1_BASE 0x4e000000 /* GPIO module #1 */
48f5d7ce3dSmatt #define GEMINI_GPIO2_BASE 0x4f000000 /* GPIO module #2 */
49f5d7ce3dSmatt #define GEMINI_PCICFG_BASE 0x50000000 /* PCI IO, configuration and control space */
50f5d7ce3dSmatt #define GEMINI_PCIIO_BASE 0x50001000 /* PCI IO space */
51f5d7ce3dSmatt #define GEMINI_PCIIO_SIZE 0x0007f000 /* PCI IO space size */
52f5d7ce3dSmatt #define GEMINI_PCIMEM_BASE 0x58000000 /* PCI Memory space */
53f5d7ce3dSmatt #define GEMINI_PCIMEM_SIZE 0x08000000 /* PCI Memory space size */
54145d2756Smatt #define GEMINI_GMAC_BASE 0x60000000 /* NetEngine & GMAC Configuration registers */
55145d2756Smatt #define GEMINI_GMAC_SIZE 0x00010000 /* NetEngine & GMAC Configuration size */
56f5d7ce3dSmatt #define GEMINI_SDC_BASE 0x62000000 /* Security DMA and Configure registers */
57f5d7ce3dSmatt #define GEMINI_MIDE_BASE 0x63000000 /* Multi IDE registers */
58f5d7ce3dSmatt #define GEMINI_RXDC_BASE 0x64000000 /* RAID XOR DMA Configuration registers */
59f5d7ce3dSmatt #define GEMINI_FLASHC_BASE 0x65000000 /* Flash Controller registers */
60f5d7ce3dSmatt #define GEMINI_DRAMC_BASE 0x66000000 /* DRAM (DDR/SDR) Controller registers */
61f5d7ce3dSmatt #define GEMINI_GDMA_BASE 0x67000000 /* General DMA registers */
62f5d7ce3dSmatt #define GEMINI_USB0_BASE 0x68000000 /* USB #0 registers */
63f5d7ce3dSmatt #define GEMINI_USB1_BASE 0x69000000 /* USB #1 registers */
64f5d7ce3dSmatt #define GEMINI_TVE_BASE 0x6a000000 /* TVE registers */
65f5d7ce3dSmatt #define GEMINI_SRAM_SHADOW_BASE 0x70000000 /* Shadow of internal SRAM */
66f5d7ce3dSmatt
67f5d7ce3dSmatt /*
6884dc474cScliff * Gemini SL3516 Global register offsets and bits
6984dc474cScliff */
7084dc474cScliff #define GEMINI_GLOBAL_WORD_ID 0x0 /* Global Word ID */ /* ro */
7184dc474cScliff #define GLOBAL_ID_CHIP_ID __BITS(31,8)
7284dc474cScliff #define GLOBAL_ID_CHIP_REV __BITS(7,0)
7384dc474cScliff #define GEMINI_GLOBAL_RESET_CTL 0xc /* Global Soft Reset Control */ /* rw */
747a2b04a9Scliff #define GLOBAL_RESET_GLOBAL __BIT(31) /* Global Soft Reset */
757a2b04a9Scliff #define GLOBAL_RESET_CPU1 __BIT(30) /* CPU#1 reset hold */
76313f8b79Smatt #define GLOBAL_RESET_GMAC1 __BIT(6) /* GMAC1 reset hold */
77313f8b79Smatt #define GLOBAL_RESET_GMAC0 __BIT(5) /* CGMAC reset hold */
787a2b04a9Scliff #define GEMINI_GLOBAL_MISC_CTL 0x30 /* Miscellaneous Control */ /* rw */
79b3224e5fScliff #define GEMINI_GLOBAL_CPU0 0x38 /* CPU #0 Status and Control */ /* rw */
80b3224e5fScliff #define GLOBAL_CPU0_IPICPU1 __BIT(31) /* IPI to CPU#1 */
81b3224e5fScliff #define GEMINI_GLOBAL_CPU1 0x3c /* CPU #1 Status and Control */ /* rw */
82b3224e5fScliff #define GLOBAL_CPU1_IPICPU0 __BIT(31) /* IPI to CPU#0 */
8384dc474cScliff
8484dc474cScliff /*
85f5d7ce3dSmatt * Gemini SL3516 Watchdog device register offsets and bits
86f5d7ce3dSmatt */
87f5d7ce3dSmatt #define GEMINI_WDT_WDCOUNTER 0x0 /* Watchdog Timer Counter */ /* ro */
88f5d7ce3dSmatt #define GEMINI_WDT_WDLOAD 0x4 /* Watchdog Timer Load */ /* rw */
89f5d7ce3dSmatt #define WDT_WDLOAD_DFLT 0x3EF1480 /* default Load reg val */
90f5d7ce3dSmatt #define GEMINI_WDT_WDRESTART 0x8 /* Watchdog Timer Restart */ /* wo */
91f5d7ce3dSmatt #define WDT_WDRESTART_Resv __BITS(31,16)
92f5d7ce3dSmatt #define WDT_WDRESTART_RST __BITS(15,0)
93f5d7ce3dSmatt #define WDT_WDRESTART_MAGIC 0x5ab9
94f5d7ce3dSmatt #define GEMINI_WDT_WDCR 0xc /* Watchdog Timer Control */ /* rw */
95f5d7ce3dSmatt #define WDT_WDCR_Resv __BITS(31,5)
96f5d7ce3dSmatt #define WDT_WDCR_CLKSRC __BIT(4) /* Timer Clock Source: 5 MHz clock */
97f5d7ce3dSmatt #define WDCR_CLKSRC_PCLK (0 << 4) /* Timer Clock Source: PCLK (APB CLK) */
98f5d7ce3dSmatt #define WDCR_CLKSRC_5MHZ (1 << 4) /* Timer Clock Source: 5 MHz clock */
99f5d7ce3dSmatt #define WDT_WDCR_EXTSIG_ENB __BIT(3) /* Timer External Signal Enable */
100f5d7ce3dSmatt #define WDT_WDCR_INTR_ENB __BIT(2) /* Timer System Interrupt Enable */
101f5d7ce3dSmatt #define WDT_WDCR_RESET_ENB __BIT(1) /* Timer System Reset Enable */
102f5d7ce3dSmatt #define WDT_WDCR_ENB __BIT(0) /* Timer Enable */
103f5d7ce3dSmatt #define GEMINI_WDT_WDSTATUS 0x10 /* Watchdog Timer Status */ /* ro */
104f5d7ce3dSmatt #define WDT_WDSTATUS_Resv __BITS(31,1)
105f5d7ce3dSmatt #define WDT_WDSTATUS_ZERO __BIT(0) /* non-zero if timer counted down to zero! */
106f5d7ce3dSmatt #define GEMINI_WDT_WDCLEAR 0x14 /* Watchdog Timer Clear */ /* wo */
107f5d7ce3dSmatt #define WDT_WDCLEAR_Resv __BITS(31,1)
108f5d7ce3dSmatt #define WDT_WDCLEAR_CLEAR __BIT(0) /* write this bit to clear Status */
109f5d7ce3dSmatt #define GEMINI_WDT_WDINTERLEN 0x18 /* Watchdog Timer Interrupt Length */ /* rw */
110f5d7ce3dSmatt /* duration of signal assertion, */
111f5d7ce3dSmatt /* in units of clock cycles */
112f5d7ce3dSmatt #define WDT_WDINTERLEN_DFLT 0xff /* default is 256 cycles */
113f5d7ce3dSmatt
114f5d7ce3dSmatt
115f5d7ce3dSmatt /*
116f5d7ce3dSmatt * Gemini SL3516 Timer device register offsets and bits
117f5d7ce3dSmatt *
118f5d7ce3dSmatt * have 3 timers, here indexed 1<=(n)<=3 as in the doc
119f5d7ce3dSmatt * each has 4 sequential 32bit rw regs
120f5d7ce3dSmatt */
121f5d7ce3dSmatt #define GEMINI_NTIMERS 3
122f5d7ce3dSmatt #define GEMINI_TIMERn_REG(n, o) ((((n) - 1) * 0x10) + (o))
123f5d7ce3dSmatt #define GEMINI_TIMERn_COUNTER(n) GEMINI_TIMERn_REG((n), 0x0) /* rw */
124f5d7ce3dSmatt #define GEMINI_TIMERn_LOAD(n) GEMINI_TIMERn_REG((n), 0x4) /* rw */
125f5d7ce3dSmatt #define GEMINI_TIMERn_MATCH1(n) GEMINI_TIMERn_REG((n), 0x08) /* rw */
126f5d7ce3dSmatt #define GEMINI_TIMERn_MATCH2(n) GEMINI_TIMERn_REG((n), 0x0C) /* rw */
127f5d7ce3dSmatt #define GEMINI_TIMER_TMCR 0x30 /* rw */
128f5d7ce3dSmatt #define TIMER_TMCR_Resv __BITS(31,12)
129f5d7ce3dSmatt #define TIMER_TMCR_TMnUPDOWN(n) __BIT(9 + (n) - 1)
130f5d7ce3dSmatt #define TIMER_TMCR_TMnOFENABLE(n) __BIT((((n) - 1) * 3) + 2)
131f5d7ce3dSmatt #define TIMER_TMCR_TMnCLOCK(n) __BIT((((n) - 1) * 3) + 1)
132f5d7ce3dSmatt #define TIMER_TMCR_TMnENABLE(n) __BIT((((n) - 1) * 3) + 0)
133f5d7ce3dSmatt #define GEMINI_TIMER_TMnCR_MASK(n) \
134f5d7ce3dSmatt ( TIMER_TMCR_TMnUPDOWN(n) \
135f5d7ce3dSmatt | TIMER_TMCR_TMnOFENABLE(n) \
136f5d7ce3dSmatt | TIMER_TMCR_TMnCLOCK(n) \
137f5d7ce3dSmatt | TIMER_TMCR_TMnENABLE(n) )
138f5d7ce3dSmatt #define GEMINI_TIMER_INTRSTATE 0x34 /* rw */
139f5d7ce3dSmatt #define TIMER_INTRSTATE_Resv __BITS(31,9)
140f5d7ce3dSmatt #define TIMER_INTRSTATE_TMnOVFLOW(n) __BIT((((n) -1) * 3) + 2)
141f5d7ce3dSmatt #define TIMER_INTRSTATE_TMnMATCH2(n) __BIT((((n) -1) * 3) + 1)
142f5d7ce3dSmatt #define TIMER_INTRSTATE_TMnMATCH1(n) __BIT((((n) -1) * 3) + 0)
143f5d7ce3dSmatt #define GEMINI_TIMER_INTRMASK 0x38 /* rw */
144f5d7ce3dSmatt #define TIMER_INTRMASK_Resv __BITS(31,9)
145f5d7ce3dSmatt #define TIMER_INTRMASK_TMnOVFLOW(n) __BIT((((n) -1) * 3) + 2)
146f5d7ce3dSmatt #define TIMER_INTRMASK_TMnMATCH2(n) __BIT((((n) -1) * 3) + 1)
147f5d7ce3dSmatt #define TIMER_INTRMASK_TMnMATCH1(n) __BIT((((n) -1) * 3) + 0)
148f5d7ce3dSmatt #define GEMINI_TIMERn_INTRMASK(n) \
149f5d7ce3dSmatt ( TIMER_INTRMASK_TMnOVFLOW(n) \
150f5d7ce3dSmatt | TIMER_INTRMASK_TMnMATCH2(n) \
151f5d7ce3dSmatt | TIMER_INTRMASK_TMnMATCH1(n) )
152f5d7ce3dSmatt
153f5d7ce3dSmatt /*
154f5d7ce3dSmatt * Gemini SL3516 Interrupt Controller device register offsets and bits
155f5d7ce3dSmatt */
156f5d7ce3dSmatt #define GEMINI_ICU_IRQ_SOURCE 0x0 /* ro */
157f5d7ce3dSmatt #define GEMINI_ICU_IRQ_ENABLE 0x4 /* rw */
158f5d7ce3dSmatt #define GEMINI_ICU_IRQ_CLEAR 0x8 /* wo */
159f5d7ce3dSmatt #define GEMINI_ICU_IRQ_TRIGMODE 0xc /* rw */
160f5d7ce3dSmatt #define ICU_IRQ_TRIGMODE_EDGE 1 /* edge triggered */
161f5d7ce3dSmatt #define ICU_IRQ_TRIGMODE_LEVEL 0 /* level triggered */
162f5d7ce3dSmatt #define GEMINI_ICU_IRQ_TRIGLEVEL 0x10 /* rw */
163f5d7ce3dSmatt #define ICU_IRQ_TRIGLEVEL_LO 1 /* active low or falling edge */
164f5d7ce3dSmatt #define ICU_IRQ_TRIGLEVEL_HI 0 /* active high or rising edge */
165f5d7ce3dSmatt #define GEMINI_ICU_IRQ_STATUS 0x14 /* ro */
166f5d7ce3dSmatt
167f5d7ce3dSmatt #define GEMINI_ICU_FIQ_SOURCE 0x20 /* ro */
168f5d7ce3dSmatt #define GEMINI_ICU_FIQ_ENABLE 0x24 /* rw */
169f5d7ce3dSmatt #define GEMINI_ICU_FIQ_CLEAR 0x28 /* wo */
170f5d7ce3dSmatt #define GEMINI_ICU_FIQ_TRIGMODE 0x2c /* rw */
171f5d7ce3dSmatt #define GEMINI_ICU_FIQ_TRIGLEVEL 0x30 /* rw */
172f5d7ce3dSmatt #define GEMINI_ICU_FIQ_STATUS 0x34 /* ro */
173f5d7ce3dSmatt
174f5d7ce3dSmatt #define GEMINI_ICU_REVISION 0x50 /* ro */
175f5d7ce3dSmatt #define GEMINI_ICU_INPUT_NUM 0x54 /* ro */
176f5d7ce3dSmatt #define ICU_INPUT_NUM_RESV __BITS(31,16)
177f5d7ce3dSmatt #define ICU_INPUT_NUM_IRQ __BITS(15,8)
178f5d7ce3dSmatt #define ICU_INPUT_NUM_FIQ __BITS(7,0)
179f5d7ce3dSmatt #define GEMINI_ICU_IRQ_DEBOUNCE 0x58 /* ro */
180f5d7ce3dSmatt #define GEMINI_ICU_FIQ_DEBOUNCE 0x5c /* ro */
181f5d7ce3dSmatt
182f5d7ce3dSmatt
183f5d7ce3dSmatt /*
1847a2b04a9Scliff * Gemini LPC controller register offsets and bits
1857a2b04a9Scliff */
1867a2b04a9Scliff #define GEMINI_LPCHC_ID 0x00 /* ro */
1877a2b04a9Scliff # define LPCHC_ID_DEVICE __BITS(31,8) /* Device ID */
1887a2b04a9Scliff # define LPCHC_ID_REV __BITS(7,0) /* Revision */
1897a2b04a9Scliff # define _LPCHC_ID_DEVICE(r) ((typeof(r))(((r) & LPCHC_ID_DEVICE) >> 8))
1907a2b04a9Scliff # define _LPCHC_ID_REV(r) ((typeof(r))(((r) & LPCHC_ID_REV) >> 0))
1917a2b04a9Scliff #define GEMINI_LPCHC_CSR 0x04 /* rw */
1927a2b04a9Scliff # define LPCHC_CSR_RESa __BITS(31,24)
1937a2b04a9Scliff # define LPCHC_CSR_STO __BIT(23) /* Sync Time Out */
1947a2b04a9Scliff # define LPCHC_CSR_SERR __BIT(22) /* Sync Error */
1957a2b04a9Scliff # define LPCHC_CSR_RESb __BITS(21,8)
1967a2b04a9Scliff # define LPCHC_CSR_STOE __BIT(7) /* Sync Time Out Enable */
1977a2b04a9Scliff # define LPCHC_CSR_SERRE __BIT(6) /* Sync Error Enable */
1987a2b04a9Scliff # define LPCHC_CSR_RESc __BITS(5,1)
1997a2b04a9Scliff # define LPCHC_CSR_BEN __BIT(0) /* Bridge Enable */
2007a2b04a9Scliff #define GEMINI_LPCHC_IRQCTL 0x08 /* rw */
2017a2b04a9Scliff # define LPCHC_IRQCTL_RESV __BITS(31,8)
2027a2b04a9Scliff # define LPCHC_IRQCTL_SIRQEN __BIT(7) /* Serial IRQ Enable */
2037a2b04a9Scliff # define LPCHC_IRQCTL_SIRQMS __BIT(6) /* Serial IRQ Mode Select */
2047a2b04a9Scliff # define LPCHC_IRQCTL_SIRQFN __BITS(5,2) /* Serial IRQ Frame Number */
2057a2b04a9Scliff # define LPCHC_IRQCTL_SIRQFW __BITS(1,0) /* Serial IRQ Frame Width */
2067a2b04a9Scliff # define IRQCTL_SIRQFW_4 0
2077a2b04a9Scliff # define IRQCTL_SIRQFW_6 1
2087a2b04a9Scliff # define IRQCTL_SIRQFW_8 2
2097a2b04a9Scliff # define IRQCTL_SIRQFW_RESV 3
2107a2b04a9Scliff #define GEMINI_LPCHC_SERIRQSTS 0x0c /* rwc */
2117a2b04a9Scliff # define LPCHC_SERIRQSTS_RESV __BITS(31,17)
2127a2b04a9Scliff #define GEMINI_LPCHC_SERIRQTYP 0x10 /* rw */
2137a2b04a9Scliff # define LPCHC_SERIRQTYP_RESV __BITS(31,17)
2147a2b04a9Scliff # define SERIRQTYP_EDGE 1
2157a2b04a9Scliff # define SERIRQTYP_LEVEL 0
2167a2b04a9Scliff #define GEMINI_LPCHC_SERIRQPOLARITY 0x14 /* rw */
2177a2b04a9Scliff # define LPCHC_SERIRQPOLARITY_RESV __BITS(31,17)
2187a2b04a9Scliff # define SERIRQPOLARITY_HI 1
2197a2b04a9Scliff # define SERIRQPOLARITY_LO 0
2207a2b04a9Scliff #define GEMINI_LPCHC_SIZE (GEMINI_LPCHC_SERIRQPOLARITY + 4)
2217a2b04a9Scliff #define GEMINI_LPCHC_NSERIRQ 17
2227a2b04a9Scliff
2237a2b04a9Scliff /*
2245aec566fScliff * Gemini GPIO controller register offsets and bits
2255aec566fScliff */
2265aec566fScliff #define GEMINI_GPIO_DATAOUT 0x00 /* Data Out */ /* rw */
2275aec566fScliff #define GEMINI_GPIO_DATAIN 0x04 /* Data Out */ /* ro */
2285aec566fScliff #define GEMINI_GPIO_PINDIR 0x08 /* Pin Direction */ /* rw */
2295aec566fScliff #define GPIO_PINDIR_INPUT 0
2305aec566fScliff #define GPIO_PINDIR_OUTPUT 1
2315aec566fScliff #define GEMINI_GPIO_PINBYPASS 0x0c /* Pin Bypass */ /* rw */
2325aec566fScliff #define GEMINI_GPIO_DATASET 0x10 /* Data Set */ /* wo */
2335aec566fScliff #define GEMINI_GPIO_DATACLR 0x14 /* Data Clear */ /* wo */
2345aec566fScliff #define GEMINI_GPIO_PULLENB 0x18 /* Pullup Enable */ /* rw */
2355aec566fScliff #define GEMINI_GPIO_PULLTYPE 0x1c /* Pullup Type */ /* rw */
2365aec566fScliff #define GPIO_PULLTYPE_LOW 0
2375aec566fScliff #define GPIO_PULLTYPE_HIGH 1
2385aec566fScliff #define GEMINI_GPIO_INTRENB 0x20 /* Interrupt Enable */ /* rw */
2395aec566fScliff #define GEMINI_GPIO_INTRRAWSTATE 0x24 /* Interrupt Raw State */ /* ro */
2405aec566fScliff #define GEMINI_GPIO_INTRMSKSTATE 0x28 /* Interrupt Masked State */ /* ro */
2415aec566fScliff #define GEMINI_GPIO_INTRMASK 0x2c /* Interrupt Mask */ /* rw */
2425aec566fScliff #define GEMINI_GPIO_INTRCLR 0x30 /* Interrupt Clear */ /* wo */
2435aec566fScliff #define GEMINI_GPIO_INTRTRIG 0x34 /* Interrupt Trigger Method */ /* rw */
2445aec566fScliff #define GPIO_INTRTRIG_EDGE 0
2455aec566fScliff #define GPIO_INTRTRIG_LEVEL 1
2465aec566fScliff #define GEMINI_GPIO_INTREDGEBOTH 0x38 /* Both edges trigger Intr. */ /* rw */
2475aec566fScliff #define GEMINI_GPIO_INTRDIR 0x3c /* edge/level direction */ /* rw */
2485aec566fScliff #define GPIO_INTRDIR_EDGE_RISING 0
2495aec566fScliff #define GPIO_INTRDIR_EDGE_FALLING 1
2505aec566fScliff #define GPIO_INTRDIR_LEVEL_HIGH 0
2515aec566fScliff #define GPIO_INTRDIR_LEVEL_LOW 1
2525aec566fScliff #define GEMINI_GPIO_BOUNCEENB 0x40 /* Bounce Enable */ /* rw */
2535aec566fScliff #define GEMINI_GPIO_BOUNCESCALE 0x44 /* Bounce Pre-Scale */ /* rw */
2545aec566fScliff #define GPIO_BOUNCESCALE_RESV __BITS(31,16)
2555aec566fScliff #define GPIO_BOUNCESCALE_VAL __BITS(15,0) /* NOTE:
2565aec566fScliff * if bounce is enabled, and bounce pre-scale == 0
257*0ae57f90Smbalmer * then the pin will not detect any interrupt
2585aec566fScliff */
2595aec566fScliff #define GEMINI_GPIO_SIZE (GEMINI_GPIO_BOUNCESCALE + 4)
2605aec566fScliff
2615aec566fScliff /*
262f5d7ce3dSmatt * Gemini PCI controller register offsets and bits
263f5d7ce3dSmatt */
264f5d7ce3dSmatt #define GEMINI_PCI_IOSIZE 0x00 /* I/O Space Size */ /* rw */
265f5d7ce3dSmatt #define GEMINI_PCI_PROT 0x04 /* AHB Protection */ /* rw */
266f5d7ce3dSmatt #define GEMINI_PCI_PCICTRL 0x08 /* PCI Control Signal */ /* rw */
267f5d7ce3dSmatt #define GEMINI_PCI_ERREN 0x0c /* Soft Reset Counter and
268f5d7ce3dSmatt * Response Error Enable */ /* rw */
269f5d7ce3dSmatt #define GEMINI_PCI_SOFTRST 0x10 /* Soft Reset */
270f5d7ce3dSmatt #define GEMINI_PCI_CFG_CMD 0x28 /* PCI Configuration Command */ /* rw */
271f5d7ce3dSmatt #define PCI_CFG_CMD_ENB __BIT(31) /* Enable */
272f5d7ce3dSmatt #define PCI_CFG_CMD_RESa __BITS(30,24)
273f5d7ce3dSmatt #define PCI_CFG_CMD_BUSNO __BITS(23,16) /* Bus Number */
274f5d7ce3dSmatt #define PCI_CFG_CMD_BUSn(n) (((n) << 16) & PCI_CFG_CMD_BUSNO)
275f5d7ce3dSmatt #define PCI_CFG_CMD_DEVNO __BITS(15,11) /* Device Number */
276f5d7ce3dSmatt #define PCI_CFG_CMD_DEVn(n) (((n) << 11) & PCI_CFG_CMD_DEVNO)
277f5d7ce3dSmatt #define PCI_CFG_CMD_FUNCNO __BITS(10,8) /* Function Number */
278f5d7ce3dSmatt #define PCI_CFG_CMD_FUNCn(n) (((n) << 8) & PCI_CFG_CMD_FUNCNO)
279f5d7ce3dSmatt #define PCI_CFG_CMD_REGNO __BITS(7,2) /* Register Number */
280f5d7ce3dSmatt #define PCI_CFG_CMD_REGn(n) (((n) << 0) & PCI_CFG_CMD_REGNO)
281f5d7ce3dSmatt #define PCI_CFG_CMD_RESb __BITS(1,0)
282f5d7ce3dSmatt #define PCI_CFG_CMD_RESV \
283f5d7ce3dSmatt (PCI_CFG_CMD_RESa | PCI_CFG_CMD_RESb)
284f5d7ce3dSmatt #define GEMINI_PCI_CFG_DATA 0x2c /* PCI Configuration Data */ /* rw */
285f5d7ce3dSmatt
286f5d7ce3dSmatt /*
287f5d7ce3dSmatt * Gemini machine dependent PCI config registers
288f5d7ce3dSmatt */
289f5d7ce3dSmatt #define GEMINI_PCI_CFG_REG_PMR1 0x40 /* Power Management 1 */ /* rw */
290f5d7ce3dSmatt #define GEMINI_PCI_CFG_REG_PMR2 0x44 /* Power Management 2 */ /* rw */
291f5d7ce3dSmatt #define GEMINI_PCI_CFG_REG_CTL1 0x48 /* Control 1 */ /* rw */
292f5d7ce3dSmatt #define GEMINI_PCI_CFG_REG_CTL2 0x4c /* Control 2 */ /* rw */
293f5d7ce3dSmatt #define PCI_CFG_REG_CTL2_INTSTS __BITS(31,28)
294f5d7ce3dSmatt #define CFG_REG_CTL2_INTSTS_INTD __BIT(28 + 3)
295f5d7ce3dSmatt #define CFG_REG_CTL2_INTSTS_INTC __BIT(28 + 2)
296f5d7ce3dSmatt #define CFG_REG_CTL2_INTSTS_INTB __BIT(28 + 1)
297f5d7ce3dSmatt #define CFG_REG_CTL2_INTSTS_INTA __BIT(28 + 0)
298f5d7ce3dSmatt #define PCI_CFG_REG_CTL2_INTMASK __BITS(27,16)
299f5d7ce3dSmatt #define CFG_REG_CTL2_INTMASK_CMDERR __BIT(16 + 11)
300f5d7ce3dSmatt #define CFG_REG_CTL2_INTMASK_PARERR __BIT(16 + 10)
301f5d7ce3dSmatt #define CFG_REG_CTL2_INTMASK_INTD __BIT(16 + 9)
302f5d7ce3dSmatt #define CFG_REG_CTL2_INTMASK_INTC __BIT(16 + 8)
303f5d7ce3dSmatt #define CFG_REG_CTL2_INTMASK_INTB __BIT(16 + 7)
304f5d7ce3dSmatt #define CFG_REG_CTL2_INTMASK_INTA __BIT(16 + 6)
305f5d7ce3dSmatt #define CFG_REG_CTL2_INTMASK_INT_ABCD __BITS(16+9,16+6)
306f5d7ce3dSmatt #define CFG_REG_CTL2_INTMASK_MABRT_RX __BIT(16 + 5)
307f5d7ce3dSmatt #define CFG_REG_CTL2_INTMASK_TABRT_RX __BIT(16 + 4)
308f5d7ce3dSmatt #define CFG_REG_CTL2_INTMASK_TABRT_TX __BIT(16 + 3)
309f5d7ce3dSmatt #define CFG_REG_CTL2_INTMASK_RETRY4 __BIT(16 + 2)
310f5d7ce3dSmatt #define CFG_REG_CTL2_INTMASK_SERR_RX __BIT(16 + 1)
311f5d7ce3dSmatt #define CFG_REG_CTL2_INTMASK_PERR_RX __BIT(16 + 0)
312f5d7ce3dSmatt #define PCI_CFG_REG_CTL2_RESa __BIT(15)
313f5d7ce3dSmatt #define PCI_CFG_REG_CTL2_MSTPRI __BITS(14,8)
314f5d7ce3dSmatt #define CFG_REG_CTL2_MSTPRI_REQn(n) __BIT(8 + (n))
315f5d7ce3dSmatt #define PCI_CFG_REG_CTL2_RESb __BITS(7,4)
316f5d7ce3dSmatt #define PCI_CFG_REG_CTL2_TRDYW __BITS(3,0)
317f5d7ce3dSmatt #define PCI_CFG_REG_CTL2_RESV \
318f5d7ce3dSmatt (PCI_CFG_REG_CTL2_RESa | PCI_CFG_REG_CTL2_RESb)
319f5d7ce3dSmatt #define GEMINI_PCI_CFG_REG_MEM1 0x50 /* Memory 1 Base */ /* rw */
320f5d7ce3dSmatt #define GEMINI_PCI_CFG_REG_MEM2 0x54 /* Memory 2 Base */ /* rw */
321f5d7ce3dSmatt #define GEMINI_PCI_CFG_REG_MEM3 0x58 /* Memory 3 Base */ /* rw */
322f5d7ce3dSmatt #define PCI_CFG_REG_MEM_BASE_MASK __BITS(31,20)
323f5d7ce3dSmatt #define PCI_CFG_REG_MEM_BASE(base) ((base) & PCI_CFG_REG_MEM_BASE_MASK)
324f5d7ce3dSmatt #define PCI_CFG_REG_MEM_SIZE_MASK __BITS(19,16)
325f5d7ce3dSmatt #define PCI_CFG_REG_MEM_SIZE_1MB (0x0 << 16)
326f5d7ce3dSmatt #define PCI_CFG_REG_MEM_SIZE_2MB (0x1 << 16)
327f5d7ce3dSmatt #define PCI_CFG_REG_MEM_SIZE_4MB (0x2 << 16)
328f5d7ce3dSmatt #define PCI_CFG_REG_MEM_SIZE_8MB (0x3 << 16)
329f5d7ce3dSmatt #define PCI_CFG_REG_MEM_SIZE_16MB (0x4 << 16)
330f5d7ce3dSmatt #define PCI_CFG_REG_MEM_SIZE_32MB (0x5 << 16)
331f5d7ce3dSmatt #define PCI_CFG_REG_MEM_SIZE_64MB (0x6 << 16)
332f5d7ce3dSmatt #define PCI_CFG_REG_MEM_SIZE_128MB (0x7 << 16)
333f5d7ce3dSmatt #define PCI_CFG_REG_MEM_SIZE_256MB (0x8 << 16)
334f5d7ce3dSmatt #define PCI_CFG_REG_MEM_SIZE_512MB (0x9 << 16)
335f5d7ce3dSmatt #define PCI_CFG_REG_MEM_SIZE_1GB (0xa << 16)
336f5d7ce3dSmatt #define PCI_CFG_REG_MEM_SIZE_2GB (0xb << 16)
337f5d7ce3dSmatt #define PCI_CFG_REG_MEM_RESV __BITS(19,16)
338f5d7ce3dSmatt
339f5d7ce3dSmatt #ifndef _LOCORE
340f5d7ce3dSmatt static inline unsigned int
gemini_pci_cfg_reg_mem_size(size_t sz)341f5d7ce3dSmatt gemini_pci_cfg_reg_mem_size(size_t sz)
342f5d7ce3dSmatt {
343f5d7ce3dSmatt switch (sz) {
344f5d7ce3dSmatt case (1 << 20):
345f5d7ce3dSmatt return PCI_CFG_REG_MEM_SIZE_1MB;
346f5d7ce3dSmatt case (2 << 20):
347f5d7ce3dSmatt return PCI_CFG_REG_MEM_SIZE_2MB;
348f5d7ce3dSmatt case (4 << 20):
349f5d7ce3dSmatt return PCI_CFG_REG_MEM_SIZE_4MB;
350f5d7ce3dSmatt case (8 << 20):
351f5d7ce3dSmatt return PCI_CFG_REG_MEM_SIZE_8MB;
352f5d7ce3dSmatt case (16 << 20):
353f5d7ce3dSmatt return PCI_CFG_REG_MEM_SIZE_16MB;
354f5d7ce3dSmatt case (32 << 20):
355f5d7ce3dSmatt return PCI_CFG_REG_MEM_SIZE_32MB;
356f5d7ce3dSmatt case (64 << 20):
357f5d7ce3dSmatt return PCI_CFG_REG_MEM_SIZE_64MB;
358f5d7ce3dSmatt case (128 << 20):
359f5d7ce3dSmatt return PCI_CFG_REG_MEM_SIZE_128MB;
360f5d7ce3dSmatt case (256 << 20):
361f5d7ce3dSmatt return PCI_CFG_REG_MEM_SIZE_256MB;
362f5d7ce3dSmatt case (512 << 20):
363f5d7ce3dSmatt return PCI_CFG_REG_MEM_SIZE_512MB;
364f5d7ce3dSmatt case (1024 << 20):
365f5d7ce3dSmatt return PCI_CFG_REG_MEM_SIZE_1GB;
366f5d7ce3dSmatt case (2048 << 20):
367f5d7ce3dSmatt return PCI_CFG_REG_MEM_SIZE_2GB;
368f5d7ce3dSmatt default:
369f5d7ce3dSmatt panic("gemini_pci_cfg_reg_mem_size: bad size %#lx\n", sz);
370f5d7ce3dSmatt }
371f5d7ce3dSmatt /* NOTREACHED */
372f5d7ce3dSmatt }
373f5d7ce3dSmatt #endif /* _LOCORE */
374f5d7ce3dSmatt
3757a2b04a9Scliff /*
3767a2b04a9Scliff * Gemini SL3516 IDE device register offsets, &etc.
3777a2b04a9Scliff */
3787a2b04a9Scliff #define GEMINI_MIDE_NCHAN 2
3797a2b04a9Scliff #define GEMINI_MIDE_OFFSET(chan) ((chan == 0) ? 0x0 : 0x400000)
3807a2b04a9Scliff #define GEMINI_MIDE_BASEn(chan) (GEMINI_MIDE_BASE + GEMINI_MIDE_OFFSET(chan))
3817a2b04a9Scliff #define GEMINI_MIDE_CMDBLK 0x20
3827a2b04a9Scliff #define GEMINI_MIDE_CTLBLK 0x36
3837a2b04a9Scliff #define GEMINI_MIDE_SIZE 0x40
3847a2b04a9Scliff
3857a2b04a9Scliff
386b3224e5fScliff /*
387b3224e5fScliff * Gemini DRAM Controller register offsets, &etc.
388b3224e5fScliff */
389b3224e5fScliff #define GEMINI_DRAMC_RMCR 0x40 /* CPU Remap Control */ /* rw */
390b3224e5fScliff #define DRAMC_RMCR_RESa __BITS(31,29)
391b3224e5fScliff #define DRAMC_RMCR_RMBAR __BITS(28,20) /* Remap Base Address */
392b3224e5fScliff #define DRAMC_RMCR_RMBAR_SHFT 20
393b3224e5fScliff #define DRAMC_RMCR_RESb __BITS(19,9)
394b3224e5fScliff #define DRAMC_RMCR_RMSZR __BITS(8,0) /* Remap Size Address */
395b3224e5fScliff #define DRAMC_RMCR_RMSZR_SHFT 0
396b3224e5fScliff
397f5d7ce3dSmatt #else
398f5d7ce3dSmatt # error unknown gemini cpu type
399f5d7ce3dSmatt #endif
400f5d7ce3dSmatt
401f5d7ce3dSmatt #endif /* _ARM_GEMINI_REG_H_ */
402