1 /* $NetBSD: pte.h,v 1.5 2002/04/05 16:58:06 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_PTE_H_ 39 #define _ARM_PTE_H_ 40 41 /* 42 * The ARM MMU architecture was introduced with ARM v3 (previous ARM 43 * architecture versions used an optional off-CPU memory controller 44 * to perform address translation). 45 * 46 * The ARM MMU consists of a TLB and translation table walking logic. 47 * There is typically one TLB per memory interface (or, put another 48 * way, one TLB per software-visible cache). 49 * 50 * The ARM MMU is capable of mapping memory in the following chunks: 51 * 52 * 1M Sections (L1 table) 53 * 54 * 64K Large Pages (L2 table) 55 * 56 * 4K Small Pages (L2 table) 57 * 58 * 1K Tiny Pages (L2 table) 59 * 60 * There are two types of L2 tables: Coarse Tables and Fine Tables. 61 * Coarse Tables can map Large and Small Pages. Fine Tables can 62 * map Tiny Pages. 63 * 64 * Coarse Tables can define 4 Subpages within Large and Small pages. 65 * Subpages define different permissions for each Subpage within 66 * a Page. 67 * 68 * Coarse Tables are 1K in length. Fine tables are 4K in length. 69 * 70 * The Translation Table Base register holds the pointer to the 71 * L1 Table. The L1 Table is a 16K contiguous chunk of memory 72 * aligned to a 16K boundary. Each entry in the L1 Table maps 73 * 1M of virtual address space, either via a Section mapping or 74 * via an L2 Table. 75 * 76 * In addition, the Fast Context Switching Extension (FCSE) is available 77 * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating 78 * TLB/cache flushes on context switch by use of a smaller address space 79 * and a "process ID" that modifies the virtual address before being 80 * presented to the translation logic. 81 */ 82 83 #ifndef _LOCORE 84 typedef uint32_t pd_entry_t; /* L1 table entry */ 85 typedef uint32_t pt_entry_t; /* L2 table entry */ 86 #endif /* _LOCORE */ 87 88 #define L1_S_SIZE 0x00100000 /* 1M */ 89 #define L1_S_OFFSET (L1_S_SIZE - 1) 90 #define L1_S_FRAME (~L1_S_OFFSET) 91 #define L1_S_SHIFT 20 92 93 #define L2_L_SIZE 0x00010000 /* 64K */ 94 #define L2_L_OFFSET (L2_L_SIZE - 1) 95 #define L2_L_FRAME (~L2_L_OFFSET) 96 #define L2_L_SHIFT 16 97 98 #define L2_S_SIZE 0x00001000 /* 4K */ 99 #define L2_S_OFFSET (L2_S_SIZE - 1) 100 #define L2_S_FRAME (~L2_S_OFFSET) 101 #define L2_S_SHIFT 12 102 103 #define L2_T_SIZE 0x00000400 /* 1K */ 104 #define L2_T_OFFSET (L2_T_SIZE - 1) 105 #define L2_T_FRAME (~L2_T_OFFSET) 106 #define L2_T_SHIFT 10 107 108 /* 109 * The NetBSD VM implementation only works on whole pages (4K), 110 * whereas the ARM MMU's Coarse tables are sized in terms of 1K 111 * (16K L1 table, 1K L2 table). 112 * 113 * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2 114 * table. 115 */ 116 #define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */ 117 #define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */ 118 119 #define L1_TABLE_SIZE 0x4000 /* 16K */ 120 #define L2_TABLE_SIZE 0x1000 /* 4K */ 121 122 /* 123 * ARM L1 Descriptors 124 */ 125 126 #define L1_TYPE_INV 0x00 /* Invalid (fault) */ 127 #define L1_TYPE_C 0x01 /* Coarse L2 */ 128 #define L1_TYPE_S 0x02 /* Section */ 129 #define L1_TYPE_F 0x03 /* Fine L2 */ 130 #define L1_TYPE_MASK 0x03 /* mask of type bits */ 131 132 /* L1 Section Descriptor */ 133 #define L1_S_B 0x00000004 /* bufferable Section */ 134 #define L1_S_C 0x00000008 /* cacheable Section */ 135 #define L1_S_IMP 0x00000010 /* implementation defined */ 136 #define L1_S_DOM(x) ((x) << 5) /* domain */ 137 #define L1_S_DOM_MASK L1_S_DOM(0xf) 138 #define L1_S_AP(x) ((x) << 10) /* access permissions */ 139 #define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ 140 141 #define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */ 142 #define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */ 143 144 /* L1 Coarse Descriptor */ 145 #define L1_C_IMP0 0x00000004 /* implementation defined */ 146 #define L1_C_IMP1 0x00000008 /* implementation defined */ 147 #define L1_C_IMP2 0x00000010 /* implementation defined */ 148 #define L1_C_DOM(x) ((x) << 5) /* domain */ 149 #define L1_C_DOM_MASK L1_C_DOM(0xf) 150 #define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ 151 152 #define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */ 153 154 /* L1 Fine Descriptor */ 155 #define L1_F_IMP0 0x00000004 /* implementation defined */ 156 #define L1_F_IMP1 0x00000008 /* implementation defined */ 157 #define L1_F_IMP2 0x00000010 /* implementation defined */ 158 #define L1_F_DOM(x) ((x) << 5) /* domain */ 159 #define L1_F_DOM_MASK L1_F_DOM(0xf) 160 #define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */ 161 162 #define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */ 163 164 /* 165 * ARM L2 Descriptors 166 */ 167 168 #define L2_TYPE_INV 0x00 /* Invalid (fault) */ 169 #define L2_TYPE_L 0x01 /* Large Page */ 170 #define L2_TYPE_S 0x02 /* Small Page */ 171 #define L2_TYPE_T 0x03 /* Tiny Page */ 172 #define L2_TYPE_MASK 0x03 /* mask of type bits */ 173 174 /* 175 * This L2 Descriptor type is available on XScale processors 176 * when using a Coarse L1 Descriptor. The Extended Small 177 * Descriptor has the same format as the XScale Tiny Descriptor, 178 * but describes a 4K page, rather than a 1K page. 179 */ 180 #define L2_TYPE_XSCALE_XS 0x03 /* XScale Extended Small Page */ 181 182 #define L2_B 0x00000004 /* Bufferable page */ 183 #define L2_C 0x00000008 /* Cacheable page */ 184 #define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */ 185 #define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */ 186 #define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */ 187 #define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */ 188 #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 189 190 #define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */ 191 #define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */ 192 193 /* 194 * Access Permissions for L1 and L2 Descriptors. 195 */ 196 #define AP_W 0x01 /* writable */ 197 #define AP_U 0x02 /* user */ 198 199 /* 200 * Short-hand for common AP_* constants. 201 * 202 * Note: These values assume the S (System) bit is set and 203 * the R (ROM) bit is clear in CP15 register 1. 204 */ 205 #define AP_KR 0x00 /* kernel read */ 206 #define AP_KRW 0x01 /* kernel read/write */ 207 #define AP_KRWUR 0x02 /* kernel read/write usr read */ 208 #define AP_KRWURW 0x03 /* kernel read/write usr read/write */ 209 210 /* 211 * Domain Types for the Domain Access Control Register. 212 */ 213 #define DOMAIN_FAULT 0x00 /* no access */ 214 #define DOMAIN_CLIENT 0x01 /* client */ 215 #define DOMAIN_RESERVED 0x02 /* reserved */ 216 #define DOMAIN_MANAGER 0x03 /* manager */ 217 218 /* 219 * Type Extension bits for XScale processors. 220 * 221 * Behavior of C and B when X == 0: 222 * 223 * C B Cacheable Bufferable Write Policy Line Allocate Policy 224 * 0 0 N N - - 225 * 0 1 N Y - - 226 * 1 0 Y Y Write-through Read Allocate 227 * 1 1 Y Y Write-back Read Allocate 228 * 229 * Behavior of C and B when X == 1: 230 * C B Cacheable Bufferable Write Policy Line Allocate Policy 231 * 0 0 - - - - DO NOT USE 232 * 0 1 N Y - - 233 * 1 0 Mini-Data - - - 234 * 1 1 Y Y Write-back R/W Allocate 235 */ 236 #define TEX_XSCALE_X 0x01 /* X modifies C and B */ 237 238 #endif /* _ARM_PTE_H_ */ 239