1*162a5c00Ssimonb /* $NetBSD: cputypes.h,v 1.16 2021/11/13 01:09:51 simonb Exp $ */ 2d3cd5314Sryo 3d3cd5314Sryo /* 4d3cd5314Sryo * Copyright (c) 1998, 2001 Ben Harris 5d3cd5314Sryo * Copyright (c) 1994-1996 Mark Brinicombe. 6d3cd5314Sryo * Copyright (c) 1994 Brini. 7d3cd5314Sryo * All rights reserved. 8d3cd5314Sryo * 9d3cd5314Sryo * This code is derived from software written for Brini by Mark Brinicombe 10d3cd5314Sryo * 11d3cd5314Sryo * Redistribution and use in source and binary forms, with or without 12d3cd5314Sryo * modification, are permitted provided that the following conditions 13d3cd5314Sryo * are met: 14d3cd5314Sryo * 1. Redistributions of source code must retain the above copyright 15d3cd5314Sryo * notice, this list of conditions and the following disclaimer. 16d3cd5314Sryo * 2. Redistributions in binary form must reproduce the above copyright 17d3cd5314Sryo * notice, this list of conditions and the following disclaimer in the 18d3cd5314Sryo * documentation and/or other materials provided with the distribution. 19d3cd5314Sryo * 3. All advertising materials mentioning features or use of this software 20d3cd5314Sryo * must display the following acknowledgement: 21d3cd5314Sryo * This product includes software developed by Brini. 22d3cd5314Sryo * 4. The name of the company nor the name of the author may be used to 23d3cd5314Sryo * endorse or promote products derived from this software without specific 24d3cd5314Sryo * prior written permission. 25d3cd5314Sryo * 26d3cd5314Sryo * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27d3cd5314Sryo * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28d3cd5314Sryo * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29d3cd5314Sryo * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30d3cd5314Sryo * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31d3cd5314Sryo * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32d3cd5314Sryo * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33d3cd5314Sryo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34d3cd5314Sryo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35d3cd5314Sryo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36d3cd5314Sryo * SUCH DAMAGE. 37d3cd5314Sryo */ 38d3cd5314Sryo 39d3cd5314Sryo #ifndef _ARM_CPUTYPES_H_ 40d3cd5314Sryo #define _ARM_CPUTYPES_H_ 41d3cd5314Sryo 42d3cd5314Sryo /* 43d3cd5314Sryo * The CPU ID register is theoretically structured, but the definitions of 44d3cd5314Sryo * the fields keep changing. 45d3cd5314Sryo */ 46d3cd5314Sryo 47d3cd5314Sryo /* The high-order byte is always the implementor */ 48d3cd5314Sryo #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 49d3cd5314Sryo #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 5040488029Sryo #define CPU_ID_BROADCOM 0x42000000 /* 'B' */ 51d3cd5314Sryo #define CPU_ID_CAVIUM 0x43000000 /* 'C' */ 52d3cd5314Sryo #define CPU_ID_DEC 0x44000000 /* 'D' */ 53d3cd5314Sryo #define CPU_ID_INFINEON 0x49000000 /* 'I' */ 54d3cd5314Sryo #define CPU_ID_MOTOROLA 0x4d000000 /* 'M' */ 55d3cd5314Sryo #define CPU_ID_NVIDIA 0x4e000000 /* 'N' */ 5640488029Sryo #define CPU_ID_APM 0x50000000 /* 'P' */ 57d3cd5314Sryo #define CPU_ID_QUALCOMM 0x51000000 /* 'Q' */ 5840488029Sryo #define CPU_ID_SAMSUNG 0x53000000 /* 'S' */ 59d3cd5314Sryo #define CPU_ID_TI 0x54000000 /* 'T' */ 60d3cd5314Sryo #define CPU_ID_MARVELL 0x56000000 /* 'V' */ 6140488029Sryo #define CPU_ID_APPLE 0x61000000 /* 'a' */ 62d3cd5314Sryo #define CPU_ID_FARADAY 0x66000000 /* 'f' */ 63d3cd5314Sryo #define CPU_ID_INTEL 0x69000000 /* 'i' */ 64d3cd5314Sryo 65d3cd5314Sryo /* How to decide what format the CPUID is in. */ 66d3cd5314Sryo #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 67d3cd5314Sryo #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 68d3cd5314Sryo #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 69d3cd5314Sryo 70d3cd5314Sryo /* On ARM3 and ARM6, this byte holds the foundry ID. */ 71d3cd5314Sryo #define CPU_ID_FOUNDRY_MASK 0x00ff0000 72d3cd5314Sryo #define CPU_ID_FOUNDRY_VLSI 0x00560000 73d3cd5314Sryo 74d3cd5314Sryo /* On ARM7 it holds the architecture and variant (sub-model) */ 75d3cd5314Sryo #define CPU_ID_7ARCH_MASK 0x00800000 76d3cd5314Sryo #define CPU_ID_7ARCH_V3 0x00000000 77d3cd5314Sryo #define CPU_ID_7ARCH_V4T 0x00800000 78d3cd5314Sryo #define CPU_ID_7VARIANT_MASK 0x007f0000 79d3cd5314Sryo 80d3cd5314Sryo /* On more recent ARMs, it does the same, but in a different format */ 81d3cd5314Sryo #define CPU_ID_ARCH_MASK 0x000f0000 82d3cd5314Sryo #define CPU_ID_ARCH_V3 0x00000000 83d3cd5314Sryo #define CPU_ID_ARCH_V4 0x00010000 84d3cd5314Sryo #define CPU_ID_ARCH_V4T 0x00020000 85d3cd5314Sryo #define CPU_ID_ARCH_V5 0x00030000 86d3cd5314Sryo #define CPU_ID_ARCH_V5T 0x00040000 87d3cd5314Sryo #define CPU_ID_ARCH_V5TE 0x00050000 88d3cd5314Sryo #define CPU_ID_ARCH_V5TEJ 0x00060000 89d3cd5314Sryo #define CPU_ID_ARCH_V6 0x00070000 90d3cd5314Sryo #define CPU_ID_VARIANT_MASK 0x00f00000 91d3cd5314Sryo 92d3cd5314Sryo /* Next three nybbles are part number */ 93d3cd5314Sryo #define CPU_ID_PARTNO_MASK 0x0000fff0 94d3cd5314Sryo 95d3cd5314Sryo /* Intel XScale has sub fields in part number */ 96d3cd5314Sryo #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 97d3cd5314Sryo #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 98d3cd5314Sryo #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 99d3cd5314Sryo 100d3cd5314Sryo /* And finally, the revision number. */ 101d3cd5314Sryo #define CPU_ID_REVISION_MASK 0x0000000f 102d3cd5314Sryo 103d3cd5314Sryo /* Individual CPUs are probably best IDed by everything but the revision. */ 104d3cd5314Sryo #define CPU_ID_CPU_MASK 0xfffffff0 105d3cd5314Sryo 106d3cd5314Sryo /* Fake CPU IDs for ARMs without CP15 */ 107d3cd5314Sryo #define CPU_ID_ARM2 0x41560200 108d3cd5314Sryo #define CPU_ID_ARM250 0x41560250 109d3cd5314Sryo 110d3cd5314Sryo /* Pre-ARM7 CPUs -- [15:12] == 0 */ 111d3cd5314Sryo #define CPU_ID_ARM3 0x41560300 112d3cd5314Sryo #define CPU_ID_ARM600 0x41560600 113d3cd5314Sryo #define CPU_ID_ARM610 0x41560610 114d3cd5314Sryo #define CPU_ID_ARM620 0x41560620 115d3cd5314Sryo 116d3cd5314Sryo /* ARM7 CPUs -- [15:12] == 7 */ 117d3cd5314Sryo #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 118d3cd5314Sryo #define CPU_ID_ARM710 0x41007100 119d3cd5314Sryo #define CPU_ID_ARM7500 0x41027100 120d3cd5314Sryo #define CPU_ID_ARM710A 0x41067100 121d3cd5314Sryo #define CPU_ID_ARM7500FE 0x41077100 122d3cd5314Sryo #define CPU_ID_ARM710T 0x41807100 123d3cd5314Sryo #define CPU_ID_ARM720T 0x41807200 124d3cd5314Sryo #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 125d3cd5314Sryo #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 126d3cd5314Sryo 127d3cd5314Sryo /* Post-ARM7 CPUs */ 128d3cd5314Sryo #define CPU_ID_ARM810 0x41018100 129d3cd5314Sryo #define CPU_ID_ARM920T 0x41129200 130d3cd5314Sryo #define CPU_ID_ARM922T 0x41029220 131d3cd5314Sryo #define CPU_ID_ARM926EJS 0x41069260 132d3cd5314Sryo #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 133d3cd5314Sryo #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 134d3cd5314Sryo #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 135d3cd5314Sryo #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 136d3cd5314Sryo #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 137d3cd5314Sryo #define CPU_ID_ARM1022ES 0x4105a220 138d3cd5314Sryo #define CPU_ID_ARM1026EJS 0x4106a260 139d3cd5314Sryo #define CPU_ID_ARM11MPCORE 0x410fb020 140d3cd5314Sryo #define CPU_ID_ARM1136JS 0x4107b360 141d3cd5314Sryo #define CPU_ID_ARM1136JSR1 0x4117b360 142d3cd5314Sryo #define CPU_ID_ARM1156T2S 0x4107b560 /* MPU only */ 143d3cd5314Sryo #define CPU_ID_ARM1176JZS 0x410fb760 144d3cd5314Sryo #define CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000) 145ac4b8db0Smrg 146ac4b8db0Smrg /* ARMv7 CPUs */ 147d3cd5314Sryo #define CPU_ID_CORTEXA5R0 0x410fc050 148d3cd5314Sryo #define CPU_ID_CORTEXA7R0 0x410fc070 149d3cd5314Sryo #define CPU_ID_CORTEXA8R1 0x411fc080 150d3cd5314Sryo #define CPU_ID_CORTEXA8R2 0x412fc080 151d3cd5314Sryo #define CPU_ID_CORTEXA8R3 0x413fc080 152d3cd5314Sryo #define CPU_ID_CORTEXA9R1 0x411fc090 153d3cd5314Sryo #define CPU_ID_CORTEXA9R2 0x412fc090 154d3cd5314Sryo #define CPU_ID_CORTEXA9R3 0x413fc090 155d3cd5314Sryo #define CPU_ID_CORTEXA9R4 0x414fc090 156e8726373Stnn #define CPU_ID_CORTEXA12R0 0x410fc0d0 157d3cd5314Sryo #define CPU_ID_CORTEXA15R2 0x412fc0f0 158d3cd5314Sryo #define CPU_ID_CORTEXA15R3 0x413fc0f0 1593a88a279Sjmcneill #define CPU_ID_CORTEXA15R4 0x414fc0f0 160d3cd5314Sryo #define CPU_ID_CORTEXA17R1 0x411fc0e0 161ac4b8db0Smrg 162ac4b8db0Smrg /* ARMv8 CPUS */ 163ac4b8db0Smrg #define CPU_ID_CORTEXA32R1 0x411fd010 164d3cd5314Sryo #define CPU_ID_CORTEXA35R0 0x410fd040 165ac4b8db0Smrg #define CPU_ID_CORTEXA35R1 0x411fd040 166d3cd5314Sryo #define CPU_ID_CORTEXA53R0 0x410fd030 167d3cd5314Sryo #define CPU_ID_CORTEXA55R1 0x411fd050 168d3cd5314Sryo #define CPU_ID_CORTEXA57R0 0x410fd070 169d3cd5314Sryo #define CPU_ID_CORTEXA57R1 0x411fd070 170ac4b8db0Smrg #define CPU_ID_CORTEXA65R0 0x410fd060 171d3cd5314Sryo #define CPU_ID_CORTEXA72R0 0x410fd080 172d3cd5314Sryo #define CPU_ID_CORTEXA73R0 0x410fd090 173d3cd5314Sryo #define CPU_ID_CORTEXA75R2 0x412fd0a0 174ac4b8db0Smrg #define CPU_ID_CORTEXA76AER1 0x411fd0e0 175a5f54d8dSmrg #define CPU_ID_CORTEXA76R3 0x413fd0b0 176f489bc0eSjmcneill #define CPU_ID_NEOVERSEN1R3 0x413fd0c0 177f489bc0eSjmcneill #define CPU_ID_NEOVERSEE1R1 0x411fd4a0 178ac4b8db0Smrg #define CPU_ID_CORTEXA77R0 0x410fd0d0 179d3cd5314Sryo 180d3cd5314Sryo #define CPU_ID_CORTEX_P(n) ((n & 0xff0fe000) == 0x410fc000) 181d3cd5314Sryo #define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050) 182d3cd5314Sryo #define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070) 183d3cd5314Sryo #define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080) 184d3cd5314Sryo #define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090) 185f05c8035Stnn #define CPU_ID_CORTEX_A12_P(n) ((n & 0xff0ff0f0) == 0x410fc0d0) 186d3cd5314Sryo #define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0) 187f05c8035Stnn #define CPU_ID_CORTEX_A17_P(n) ((n & 0xff0ff0f0) == 0x410fc0e0) 188ac4b8db0Smrg #define CPU_ID_CORTEX_A32_P(n) ((n & 0xff0ff0f0) == 0x410fd010) 189d3cd5314Sryo #define CPU_ID_CORTEX_A35_P(n) ((n & 0xff0ff0f0) == 0x410fd040) 190d3cd5314Sryo #define CPU_ID_CORTEX_A53_P(n) ((n & 0xff0ff0f0) == 0x410fd030) 191d3cd5314Sryo #define CPU_ID_CORTEX_A55_P(n) ((n & 0xff0ff0f0) == 0x410fd050) 192d3cd5314Sryo #define CPU_ID_CORTEX_A57_P(n) ((n & 0xff0ff0f0) == 0x410fd070) 193ac4b8db0Smrg #define CPU_ID_CORTEX_A65_P(n) ((n & 0xff0ff0f0) == 0x410fd060) 194d3cd5314Sryo #define CPU_ID_CORTEX_A72_P(n) ((n & 0xff0ff0f0) == 0x410fd080) 195d3cd5314Sryo #define CPU_ID_CORTEX_A73_P(n) ((n & 0xff0ff0f0) == 0x410fd090) 196d3cd5314Sryo #define CPU_ID_CORTEX_A75_P(n) ((n & 0xff0ff0f0) == 0x410fd0a0) 197a5f54d8dSmrg #define CPU_ID_CORTEX_A76_P(n) ((n & 0xff0ff0f0) == 0x410fd0b0) 198ac4b8db0Smrg #define CPU_ID_CORTEX_A76AE_P(n) ((n & 0xff0ff0f0) == 0x410fd0e0) 199ac4b8db0Smrg #define CPU_ID_CORTEX_A77_P(n) ((n & 0xff0ff0f0) == 0x410fd0f0) 2005d769522Sskrll 20124c2e3e6Sryo #define CPU_ID_NEOVERSEN1_P(n) ((n & 0xff0ffff0) == 0x410fd0c0) 20224c2e3e6Sryo 2035d769522Sskrll #define CPU_ID_THUNDERXRX 0x43000a10 2041900cbfaSskrll #define CPU_ID_THUNDERXP1d0 0x43000a10 2051900cbfaSskrll #define CPU_ID_THUNDERXP1d1 0x43000a11 2061900cbfaSskrll #define CPU_ID_THUNDERXP2d1 0x431f0a11 2075d769522Sskrll #define CPU_ID_THUNDERX81XXRX 0x43000a20 2085d769522Sskrll #define CPU_ID_THUNDERX83XXRX 0x43000a30 2095d769522Sskrll #define CPU_ID_THUNDERX2RX 0x43000af0 2101900cbfaSskrll 211b5b17782Sskrll /* 212*162a5c00Ssimonb * Chip-specific errata. These defines are intended to be 213b5b17782Sskrll * booleans used within if statements. When an appropriate 214b5b17782Sskrll * kernel option is disabled, these defines must be defined 215b5b17782Sskrll * as 0 to allow the compiler to remove a dead code thus 216b5b17782Sskrll * produce better optimized kernel image. 217b5b17782Sskrll */ 218b5b17782Sskrll /* 219b5b17782Sskrll * Vendor: Cavium 220b5b17782Sskrll * Chip: ThunderX 221b5b17782Sskrll * Revision(s): Pass 1.0, Pass 1.1 222b5b17782Sskrll */ 223b5b17782Sskrll #define CPU_ID_ERRATA_CAVIUM_THUNDERX_1_1_P(n) \ 224b5b17782Sskrll (((n) & 0xfff0ffff) == CPU_ID_THUNDERXP1d0 || \ 225b5b17782Sskrll ((n) & 0xfff0ffff) == CPU_ID_THUNDERXP1d1) 226b5b17782Sskrll 227f09a00feSjmcneill #define CPU_ID_APPLE_M1_ICESTORM 0x61000220 228f09a00feSjmcneill #define CPU_ID_APPLE_M1_FIRESTORM 0x61000230 229f09a00feSjmcneill 230d3cd5314Sryo #define CPU_ID_SA110 0x4401a100 231d3cd5314Sryo #define CPU_ID_SA1100 0x4401a110 232ce852336Sskrll #define CPU_ID_NVIDIADENVER2 0x4e0f0030 233a2ce741cSjmcneill #define CPU_ID_EMAG8180 0x503f0002 234d3cd5314Sryo #define CPU_ID_TI925T 0x54029250 235d3cd5314Sryo #define CPU_ID_MV88FR571_VD 0x56155710 236d3cd5314Sryo #define CPU_ID_MV88SV131 0x56251310 237d3cd5314Sryo #define CPU_ID_FA526 0x66015260 238d3cd5314Sryo #define CPU_ID_SA1110 0x6901b110 239d3cd5314Sryo #define CPU_ID_IXP1200 0x6901c120 240d3cd5314Sryo #define CPU_ID_80200 0x69052000 241d3cd5314Sryo #define CPU_ID_PXA250 0x69052100 /* sans core revision */ 242d3cd5314Sryo #define CPU_ID_PXA210 0x69052120 243d3cd5314Sryo #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 244d3cd5314Sryo #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 245d3cd5314Sryo #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 246d3cd5314Sryo #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 247d3cd5314Sryo #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 248d3cd5314Sryo #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 249d3cd5314Sryo #define CPU_ID_PXA27X 0x69054110 250d3cd5314Sryo #define CPU_ID_80321_400 0x69052420 251d3cd5314Sryo #define CPU_ID_80321_600 0x69052430 252d3cd5314Sryo #define CPU_ID_80321_400_B0 0x69052c20 253d3cd5314Sryo #define CPU_ID_80321_600_B0 0x69052c30 254d3cd5314Sryo #define CPU_ID_80219_400 0x69052e20 255d3cd5314Sryo #define CPU_ID_80219_600 0x69052e30 256d3cd5314Sryo #define CPU_ID_IXP425_533 0x690541c0 257d3cd5314Sryo #define CPU_ID_IXP425_400 0x690541d0 258d3cd5314Sryo #define CPU_ID_IXP425_266 0x690541f0 259d3cd5314Sryo #define CPU_ID_MV88SV58XX_P(n) ((n & 0xff0fff00) == 0x560f5800) 260d3cd5314Sryo #define CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */ 261d3cd5314Sryo #define CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */ 262d3cd5314Sryo #define CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */ 263d3cd5314Sryo #define CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */ 264d3cd5314Sryo /* Marvell's CPUIDs with ARM ID in implementor field */ 265d3cd5314Sryo #define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ 266d3cd5314Sryo #define CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */ 267d3cd5314Sryo #define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */ 268d3cd5314Sryo 269d3cd5314Sryo #endif /* _ARM_CPUTYPES_H_ */ 270