1/* $NetBSD: iomd_irq.S,v 1.3 2002/10/14 22:32:51 bjh21 Exp $ */ 2 3/* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Mark Brinicombe 21 * for the NetBSD Project. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 28 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Low level irq and fiq handlers 38 * 39 * Created : 27/09/94 40 */ 41 42#include "opt_irqstats.h" 43 44#include "assym.h" 45#include <machine/asm.h> 46#include <machine/cpu.h> 47#include <machine/frame.h> 48#include <arm/iomd/iomdreg.h> 49 50 .text 51 .align 0 52/* 53 * ffs table used for servicing irq's quickly must be here otherwise adr can't 54 * reach it 55 * The algorithm for ffs was devised by D. Seal and posted to 56 * comp.sys.arm on 16 Feb 1994. 57 */ 58.type Lirq_ffs_table, _ASM_TYPE_OBJECT; 59Lirq_ffs_table: 60/* same as ffs table but all nums are -1 from that */ 61/* 0 1 2 3 4 5 6 7 */ 62 .byte 0, 0, 1, 12, 2, 6, 0, 13 /* 0- 7 */ 63 .byte 3, 0, 7, 0, 0, 0, 0, 14 /* 8-15 */ 64 .byte 10, 4, 0, 0, 8, 0, 0, 25 /* 16-23 */ 65 .byte 0, 0, 0, 0, 0, 21, 27, 15 /* 24-31 */ 66 .byte 31, 11, 5, 0, 0, 0, 0, 0 /* 32-39 */ 67 .byte 9, 0, 0, 24, 0, 0, 20, 26 /* 40-47 */ 68 .byte 30, 0, 0, 0, 0, 23, 0, 19 /* 48-55 */ 69 .byte 29, 0, 22, 18, 28, 17, 16, 0 /* 56-63 */ 70 71/* 72 * 73 * irq_entry 74 * 75 * Main entry point for the IRQ vector 76 * 77 * This function reads the irq request bits in the IOMD registers 78 * IRQRQA, IRQRQB and DMARQ 79 * It then calls an installed handler for each bit that is set. 80 * The function stray_irqhandler is called if a handler is not defined 81 * for a particular interrupt. 82 * If a interrupt handler is found then it is called with r0 containing 83 * the argument defined in the handler structure. If the field ih_arg 84 * is zero then a pointer to the IRQ frame on the stack is passed instead. 85 */ 86 87Ldisabled_mask: 88 .word _C_LABEL(disabled_mask) 89 90Lcurrent_spl_level: 91 .word _C_LABEL(current_spl_level) 92 93Lcurrent_intr_depth: 94 .word _C_LABEL(current_intr_depth) 95 96Lspl_masks: 97 .word _C_LABEL(spl_masks) 98 99/* 100 * Register usage 101 * 102 * r5 - Address of ffs table 103 * r6 - Address of current handler 104 * r7 - Pointer to handler pointer list 105 * r8 - Current IRQ requests. 106 * r10 - Base address of IOMD 107 * r11 - IRQ requests still to service. 108 */ 109 110Liomd_base: 111 .word _C_LABEL(iomd_base) 112 113Larm7500_ioc_found: 114 .word _C_LABEL(arm7500_ioc_found) 115 116ASENTRY_NP(irq_entry) 117 sub lr, lr, #0x00000004 /* Adjust the lr */ 118 119 PUSHFRAMEINSVC /* Push an interrupt frame */ 120 121 /* Load r8 with the IOMD interrupt requests */ 122 123 ldr r10, Liomd_base 124 ldr r10, [r10] /* Point to the IOMD */ 125 ldrb r8, [r10, #(IOMD_IRQRQA << 2)] /* Get IRQ request A */ 126 ldrb r9, [r10, #(IOMD_IRQRQB << 2)] /* Get IRQ request B */ 127 orr r8, r8, r9, lsl #8 128 129 ldr r9, Larm7500_ioc_found 130 ldr r9, [r9] /* get the flag */ 131 cmp r9, #0 132 beq skip_extended_IRQs_reading 133 134 /* ARM 7500 only */ 135 ldrb r9, [r10, #(IOMD_IRQRQC << 2)] /* Get IRQ request C */ 136 orr r8, r8, r9, lsl #16 137 ldrb r9, [r10, #(IOMD_IRQRQD << 2)] /* Get IRQ request D */ 138 orr r8, r8, r9, lsl #24 139 ldrb r9, [r10, #(IOMD_DMARQ << 2)] /* Get DMA Request */ 140 tst r9, #0x10 141 orrne r8, r8, r9, lsl #27 142 b irq_entry_continue 143 144skip_extended_IRQs_reading: 145 /* non ARM7500 machines */ 146 ldrb r9, [r10, #(IOMD_DMARQ << 2)] /* Get DMA Request */ 147 orr r8, r8, r9, lsl #16 148irq_entry_continue: 149 150 and r0, r8, #0x7d /* Clear IOMD IRQA bits */ 151 strb r0, [r10, #(IOMD_IRQRQA << 2)] 152 153 /* 154 * Note that we have entered the IRQ handler. 155 * We are in SVC mode so we cannot use the processor mode 156 * to determine if we are in an IRQ. Instead we will count the 157 * each time the interrupt handler is nested. 158 */ 159 160 ldr r0, Lcurrent_intr_depth 161 ldr r1, [r0] 162 add r1, r1, #1 163 str r1, [r0] 164 165 /* Block the current requested interrupts */ 166 ldr r1, Ldisabled_mask 167 ldr r0, [r1] 168 stmfd sp!, {r0} 169 orr r0, r0, r8 170 171 /* 172 * Need to block all interrupts at the IPL or lower for 173 * all asserted interrupts. 174 * This basically emulates hardware interrupt priority levels. 175 * Means we need to go through the interrupt mask and for 176 * every asserted interrupt we need to mask out all other 177 * interrupts at the same or lower IPL. 178 * If only we could wait until the main loop but we need to sort 179 * this out first so interrupts can be re-enabled. 180 * 181 * This would benefit from a special ffs type routine 182 */ 183 184 mov r9, #(_SPL_LEVELS - 1) 185 ldr r7, Lspl_masks 186 187Lfind_highest_ipl: 188 ldr r2, [r7, r9, lsl #2] 189 tst r8, r2 190 subeq r9, r9, #1 191 beq Lfind_highest_ipl 192 193 /* r9 = SPL level of highest priority interrupt */ 194 add r9, r9, #1 195 ldr r2, [r7, r9, lsl #2] 196 mvn r2, r2 197 orr r0, r0, r2 198 199 str r0, [r1] 200 201 ldr r0, Lcurrent_spl_level 202 ldr r1, [r0] 203 str r9, [r0] 204 stmfd sp!, {r1} 205 206 /* Update the IOMD irq masks */ 207 bl _C_LABEL(irq_setmasks) 208 209 mrs r0, cpsr_all /* Enable IRQ's */ 210 bic r0, r0, #I32_bit 211 msr cpsr_all, r0 212 213 ldr r7, Lirqhandlers 214 215 /* 216 * take a copy of the IRQ request so that we can strip bits out of it 217 * note that we only use 24 bits with iomd2 chips 218 */ 219 ldr r4, Larm7500_ioc_found 220 ldr r4, [r4] /* get the flag */ 221 cmp r4, #0 222 movne r11, r8 /* ARM7500 -> copy all bits */ 223 biceq r11, r8, #0xff000000 /* !ARM7500 -> only use 24 bit */ 224 225 /* ffs routine to find first irq to service */ 226 /* standard trick to isolate bottom bit in a0 or 0 if a0 = 0 on entry */ 227 rsb r4, r11, #0 228 ands r10, r11, r4 229 230 /* 231 * now r10 has at most 1 set bit, call this X 232 * if X = 0, branch to exit code 233 */ 234 beq exitirq 235 adr r5, Lirq_ffs_table 236irqloop: 237 /* 238 * at this point: 239 * r5 = address of ffs table 240 * r7 = address of irq handlers table 241 * r8 = irq request 242 * r10 = bit of irq to be serviced 243 * r11 = bitmask of IRQ's to service 244 */ 245 246 /* find the set bit */ 247 orr r9, r10, r10, lsl #4 /* X * 0x11 */ 248 orr r9, r9, r9, lsl #6 /* X * 0x451 */ 249 rsb r9, r9, r9, lsl #16 /* X * 0x0450fbaf */ 250 /* fetch the bit number */ 251 ldrb r9, [r5, r9, lsr #26 ] 252 253 /* 254 * r9 = irq to service 255 */ 256 257 /* apologies for the dogs dinner of code here, but it's in an attempt 258 * to minimise stalling on SA's, hence lots of things happen here: 259 * - getting address of handler, if it doesn't exist we call 260 * stray_irqhandler this is assumed to be rare so we don't 261 * care about performance for it 262 * - statinfo is updated 263 * - unsetting of the irq bit in r11 264 * - irq stats (if enabled) also get put in the mix 265 */ 266 ldr r4, Lcnt /* Stat info A */ 267 ldr r6, [r7, r9, lsl #2] /* Get address of first handler structure */ 268 269 ldr r1, [r4, #(V_INTR)] /* Stat info B */ 270 271 teq r6, #0x00000000 /* Do we have a handler */ 272 moveq r0, r8 /* IRQ requests as arg 0 */ 273 adreq lr, nextirq /* return Address */ 274 beq _C_LABEL(stray_irqhandler) /* call special handler */ 275 276#ifdef IRQSTATS 277 ldr r2, Lintrcnt 278 ldr r3, [r6, #(IH_NUM)] 279#endif 280 /* stat info C */ 281 add r1, r1, #0x00000001 282 str r1, [r4, #(V_INTR)] 283 284#ifdef IRQSTATS 285 ldr r3, [r2, r3, lsl #2]! 286#endif 287 bic r11, r11, r10 /* clear the IRQ bit */ 288 289#ifdef IRQSTATS 290 add r3, r3, #0x00000001 291 str r3, [r2] 292#endif /* IRQSTATS */ 293 294irqchainloop: 295 ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */ 296 teq r0, #0x00000000 /* If arg is zero pass stack frame */ 297 addeq r0, sp, #8 /* ... stack frame [XXX needs care] */ 298 mov lr, pc /* return address */ 299 ldr pc, [r6, #(IH_FUNC)] /* Call handler */ 300 301 ldr r6, [r6, #(IH_NEXT)] /* fetch next handler */ 302 303 teq r0, #0x00000001 /* Was the irq serviced ? */ 304 305 /* if it was it'll just fall through this: */ 306 teqne r6, #0x00000000 307 bne irqchainloop 308nextirq: 309 /* Check for next irq */ 310 rsb r4, r11, #0 311 ands r10, r11, r4 312 /* check if there are anymore irq's to service */ 313 bne irqloop 314 315exitirq: 316 ldmfd sp!, {r2, r3} 317 ldr r9, Lcurrent_spl_level 318 ldr r1, Ldisabled_mask 319 str r2, [r9] 320 str r3, [r1] 321 322 bl _C_LABEL(irq_setmasks) 323 324 bl _C_LABEL(dosoftints) /* Handle the soft interrupts */ 325 326 /* Manage AST's. Maybe this should be done as a soft interrupt ? */ 327 ldr r0, [sp] /* Get the SPSR from stack */ 328 329 and r0, r0, #(PSR_MODE) /* Test for USR32 mode before the IRQ */ 330 teq r0, #(PSR_USR32_MODE) 331 ldreq r0, Lastpending /* Do we have an AST pending ? */ 332 ldreq r1, [r0] 333 teqeq r1, #0x00000001 334 335 beq irqast /* call the AST handler */ 336 337 /* Kill IRQ's in preparation for exit */ 338 mrs r0, cpsr_all 339 orr r0, r0, #(I32_bit) 340 msr cpsr_all, r0 341 342 /* Decrement the nest count */ 343 ldr r0, Lcurrent_intr_depth 344 ldr r1, [r0] 345 sub r1, r1, #1 346 str r1, [r0] 347 348 PULLFRAMEFROMSVCANDEXIT 349 350 /* NOT REACHED */ 351 b . - 8 352 353 /* 354 * Ok, snag with current intr depth ... 355 * If ast() calls mi_sleep() the current_intr_depth will not be 356 * decremented until the process is woken up. This can result 357 * in the system believing it is still in the interrupt handler. 358 * If we are calling ast() then correct the current_intr_depth 359 * before the call. 360 */ 361irqast: 362 mov r1, #0x00000000 /* Clear ast_pending */ 363 str r1, [r0] 364 365 /* Kill IRQ's so we atomically decrement current_intr_depth */ 366 mrs r2, cpsr_all 367 orr r3, r2, #(I32_bit) 368 msr cpsr_all, r3 369 370 /* Decrement the interrupt nesting count */ 371 ldr r0, Lcurrent_intr_depth 372 ldr r1, [r0] 373 sub r1, r1, #1 374 str r1, [r0] 375 376 /* Restore IRQ's */ 377 msr cpsr_all, r2 378 379 mov r0, sp 380 bl _C_LABEL(ast) 381 382 /* Kill IRQ's in preparation for exit */ 383 mrs r0, cpsr_all 384 orr r0, r0, #(I32_bit) 385 msr cpsr_all, r0 386 387 PULLFRAMEFROMSVCANDEXIT 388 389 /* NOT REACHED */ 390 b . - 8 391 392 393Lspl_mask: 394 .word _C_LABEL(spl_mask) /* irq's allowed at current spl level */ 395 396Lcurrent_mask: 397 .word _C_LABEL(current_mask) /* irq's that are usable */ 398 399ENTRY(irq_setmasks) 400 /* Disable interrupts */ 401 mrs r3, cpsr_all 402 orr r1, r3, #(I32_bit) 403 msr cpsr_all, r1 404 405 /* Calculate IOMD interrupt mask */ 406 ldr r1, Lcurrent_mask /* All the enabled interrupts */ 407 ldr r2, Lspl_mask /* Block due to current spl level */ 408 ldr r1, [r1] 409 ldr r2, [r2] 410 and r1, r1, r2 411 ldr r2, Ldisabled_mask /* Block due to active interrupts */ 412 ldr r2, [r2] 413 bic r1, r1, r2 414 415 ldr r0, Liomd_base 416 ldr r0, [r0] /* Point to the IOMD */ 417 strb r1, [r0, #(IOMD_IRQMSKA << 2)] /* Set IRQ mask A */ 418 mov r1, r1, lsr #8 419 strb r1, [r0, #(IOMD_IRQMSKB << 2)] /* Set IRQ mask B */ 420 mov r1, r1, lsr #8 421 422 ldr r2, Larm7500_ioc_found 423 ldr r2, [r2] 424 cmp r2, #0 425 beq skip_setting_extended_DMA_mask 426 427 /* only for ARM7500's */ 428 strb r1, [r0, #(IOMD_IRQMSKC << 2)] 429 mov r1, r1, lsr #8 430 and r2, r1, #0xef 431 strb r2, [r0, #(IOMD_IRQMSKD << 2)] 432 mov r1, r1, lsr #3 433 and r2, r1, #0x10 434 strb r2, [r0, #(IOMD_DMAMSK << 2)] /* Set DMA mask */ 435 b continue_setting_masks 436 437skip_setting_extended_DMA_mask: 438 /* non ARM7500's */ 439 strb r1, [r0, #(IOMD_DMAMSK << 2)] /* Set DMA mask */ 440 441continue_setting_masks: 442 443 /* Restore old cpsr and exit */ 444 msr cpsr_all, r3 445 mov pc, lr 446 447Lcnt: 448 .word _C_LABEL(uvmexp) 449 450Lintrcnt: 451 .word _C_LABEL(intrcnt) 452 453 454Lirqhandlers: 455 .word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */ 456 457Lastpending: 458 .word _C_LABEL(astpending) 459 460#ifdef IRQSTATS 461/* These symbols are used by vmstat */ 462 463 .text 464 .global _C_LABEL(_intrnames) 465_C_LABEL(_intrnames): 466 .word _C_LABEL(intrnames) 467 468 .data 469 470 .globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(sintrcnt), _C_LABEL(eintrcnt) 471_C_LABEL(intrnames): 472 .asciz "interrupt 0 " 473 .asciz "interrupt 1 " /* reserved0 */ 474 .asciz "interrupt 2 " 475 .asciz "interrupt 3 " 476 .asciz "interrupt 4 " 477 .asciz "interrupt 5 " 478 .asciz "interrupt 6 " 479 .asciz "interrupt 7 " /* reserved1 */ 480 .asciz "interrupt 8 " /* reserved2 */ 481 .asciz "interrupt 9 " 482 .asciz "interrupt 10 " 483 .asciz "interrupt 11 " 484 .asciz "interrupt 12 " 485 .asciz "interrupt 13 " 486 .asciz "interrupt 14 " 487 .asciz "interrupt 15 " 488 .asciz "dma channel 0" 489 .asciz "dma channel 1" 490 .asciz "dma channel 2" 491 .asciz "dma channel 3" 492 .asciz "interrupt 20 " 493 .asciz "interrupt 21 " 494 .asciz "reserved 3 " 495 .asciz "reserved 4 " 496 .asciz "exp card 0 " 497 .asciz "exp card 1 " 498 .asciz "exp card 2 " 499 .asciz "exp card 3 " 500 .asciz "exp card 4 " 501 .asciz "exp card 5 " 502 .asciz "exp card 6 " 503 .asciz "exp card 7 " 504 505_C_LABEL(sintrnames): 506 .asciz "softclock " 507 .asciz "softnet " 508 .asciz "softserial " 509 .asciz "softintr 3 " 510 .asciz "softintr 4 " 511 .asciz "softintr 5 " 512 .asciz "softintr 6 " 513 .asciz "softintr 7 " 514 .asciz "softintr 8 " 515 .asciz "softintr 9 " 516 .asciz "softintr 10 " 517 .asciz "softintr 11 " 518 .asciz "softintr 12 " 519 .asciz "softintr 13 " 520 .asciz "softintr 14 " 521 .asciz "softintr 15 " 522 .asciz "softintr 16 " 523 .asciz "softintr 17 " 524 .asciz "softintr 18 " 525 .asciz "softintr 19 " 526 .asciz "softintr 20 " 527 .asciz "softintr 21 " 528 .asciz "softintr 22 " 529 .asciz "softintr 23 " 530 .asciz "softintr 24 " 531 .asciz "softintr 25 " 532 .asciz "softintr 26 " 533 .asciz "softintr 27 " 534 .asciz "softintr 28 " 535 .asciz "softintr 29 " 536 .asciz "softintr 30 " 537 .asciz "softintr 31 " 538_C_LABEL(eintrnames): 539 540 .bss 541 .align 0 542_C_LABEL(intrcnt): 543 .space 32*4 /* XXX Should be linked to number of interrupts */ 544 545_C_LABEL(sintrcnt): 546 .space 32*4 /* XXX Should be linked to number of interrupts */ 547_C_LABEL(eintrcnt): 548 549#else /* IRQSTATS */ 550 /* Dummy entries to keep vmstat happy */ 551 552 .text 553 .globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(eintrcnt) 554_C_LABEL(intrnames): 555 .long 0 556_C_LABEL(eintrnames): 557 558_C_LABEL(intrcnt): 559 .long 0 560_C_LABEL(eintrcnt): 561#endif /* IRQSTATS */ 562