1 /* $NetBSD: ixp12x0_comreg.h,v 1.4 2002/12/03 09:28:28 ichiro Exp $ */ 2 3 /* 4 * Copyright (c) 2002 5 * Ichiro FUKUHARA <ichiro@ichiro.org>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ichiro FUKUHARA. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS'' 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS 26 * HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 27 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * IXP12X0 UART register 37 * UART_SR 0x90003400 38 * UART_CR 0x90003800 39 * UART_DR 0x90003C00 40 */ 41 42 #define IXPCOM_FREQ (3686400 / 16) 43 #define IXPCOMSPEED(b) (IXPCOM_FREQ / (b) - 1) 44 #define IXPCOMSPEED2BRD(b) (IXPCOMSPEED(b) << 16) 45 46 /* size of I/O space */ 47 #define IXPCOM_UART_HWBASE 0x90000000UL 48 #define IXPCOM_UART_SIZE 0x00004000UL 49 50 /* Register base virtual addresses mapped by initarm() */ 51 #define IXPCOM_UART_BASE 0xf0000000UL 52 53 /* UART control register */ 54 #define IXPCOM_CR 0x00003800UL 55 #define CR_BRK 0x01 /* Break */ 56 #define CR_PE 0x02 /* Parity enable */ 57 #define CR_OES 0x04 /* Odd/even parity select */ 58 #define CR_SBS 0x08 /* Stop bit select */ 59 #define SBS_1STOP (0 << 3) /* 1 Stop Bit */ 60 #define SBS_2STOP (1 << 3) /* 2 Stop Bit */ 61 #define CR_RIE 0x10 /* Receive FIFO interrupt enable */ 62 #define CR_DSS 0x60 /* Data size select */ 63 #define DSS_5BIT (0 << 5) /* 5Bits */ 64 #define DSS_6BIT (1 << 5) /* 6Bits */ 65 #define DSS_7BIT (2 << 5) /* 7Bits */ 66 #define DSS_8BIT (3 << 5) /* 8Bits */ 67 #define CR_UE 0x80 /* UART Enable */ 68 #define UE_DISABLE (0 << 7) /* UART Disabled */ 69 #define UE_ENABLE (1 << 7) /* UART Enabled */ 70 #define CR_XIE 0x100 /* Transmit FIFO interrupt enable */ 71 #define CR_UIS 0x200 /* UART Interrupt Select */ 72 #define CR_BRD 0x03ff0000 /* Baud rate divisor */ 73 74 75 /* UART Status register */ 76 #define IXPCOM_SR 0x00003400UL 77 #define SR_PRE 0x01 /* Parity error */ 78 #define SR_FRE 0x02 /* Framing error */ 79 #define SR_TXR 0x04 /* Transmit FIFO Ready */ 80 #define SR_ROR 0x08 /* Receiver overrun */ 81 #define SR_RXR 0x10 /* Receiver FIFO Ready */ 82 #define SR_TXE 0x20 /* Transmit FIFO Empty */ 83 #define SR_RXF 0x40 /* Receiver FIFO Full */ 84 #define SR_TXF 0x80 /* Transmit FIFO Full */ 85 86 87 /* UART data register */ 88 #define IXPCOM_DR 0x00003C00UL 89 #define DR_PRE 0x100 /* Parity error */ 90 #define DR_FRE 0x200 /* Framing error */ 91 #define DR_ROR 0x400 /* Receiver overrun */ 92 93 #define IXPCOMSPLRAISED (~(CR_RIE | CR_XIE)) 94 #define IXPCOMSPLLOWERD (~0UL); 95