1 /* $NetBSD: ixp12x0_io.c,v 1.3 2002/12/08 13:21:44 ichiro Exp $ */ 2 3 /* 4 * Copyright (c) 2002 5 * Ichiro FUKUHARA <ichiro@ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 /* 37 * bus_space I/O functions for ixp12x0 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/queue.h> 43 44 #include <uvm/uvm.h> 45 46 #include <machine/bus.h> 47 48 #include <arm/ixp12x0/ixp12x0reg.h> 49 #include <arm/ixp12x0/ixp12x0var.h> 50 51 /* Proto types for all the bus_space structure functions */ 52 bs_protos(ixp12x0); 53 bs_protos(ixp12x0_io); 54 bs_protos(ixp12x0_mem); 55 bs_protos(generic); 56 bs_protos(generic_armv4); 57 bs_protos(bs_notimpl); 58 59 struct bus_space ixp12x0_bs_tag = { 60 /* cookie */ 61 (void *) 0, 62 63 /* mapping/unmapping */ 64 NULL, 65 NULL, 66 ixp12x0_bs_subregion, 67 68 /* allocation/deallocation */ 69 NULL, 70 NULL, 71 72 /* get kernel virtual address */ 73 ixp12x0_bs_vaddr, 74 75 /* mmap bus space for userland */ 76 ixp12x0_bs_mmap, 77 78 /* barrier */ 79 ixp12x0_bs_barrier, 80 81 /* read (single) */ 82 generic_bs_r_1, 83 generic_armv4_bs_r_2, 84 generic_bs_r_4, 85 bs_notimpl_bs_r_8, 86 87 /* read multiple */ 88 generic_bs_rm_1, 89 generic_armv4_bs_rm_2, 90 generic_bs_rm_4, 91 bs_notimpl_bs_rm_8, 92 93 /* read region */ 94 bs_notimpl_bs_rr_1, 95 generic_armv4_bs_rr_2, 96 generic_bs_rr_4, 97 bs_notimpl_bs_rr_8, 98 99 /* write (single) */ 100 generic_bs_w_1, 101 generic_armv4_bs_w_2, 102 generic_bs_w_4, 103 bs_notimpl_bs_w_8, 104 105 /* write multiple */ 106 generic_bs_wm_1, 107 generic_armv4_bs_wm_2, 108 generic_bs_wm_4, 109 bs_notimpl_bs_wm_8, 110 111 /* write region */ 112 bs_notimpl_bs_wr_1, 113 generic_armv4_bs_wr_2, 114 bs_notimpl_bs_wr_4, 115 bs_notimpl_bs_wr_8, 116 117 /* set multiple */ 118 bs_notimpl_bs_sm_1, 119 bs_notimpl_bs_sm_2, 120 bs_notimpl_bs_sm_4, 121 bs_notimpl_bs_sm_8, 122 123 /* set region */ 124 bs_notimpl_bs_sr_1, 125 generic_armv4_bs_sr_2, 126 bs_notimpl_bs_sr_4, 127 bs_notimpl_bs_sr_8, 128 129 /* copy */ 130 bs_notimpl_bs_c_1, 131 generic_armv4_bs_c_2, 132 bs_notimpl_bs_c_4, 133 bs_notimpl_bs_c_8, 134 }; 135 136 void 137 ixp12x0_bs_init(bs, cookie) 138 bus_space_tag_t bs; 139 void *cookie; 140 { 141 *bs = ixp12x0_bs_tag; 142 bs->bs_cookie = cookie; 143 } 144 145 void 146 ixp12x0_io_bs_init(bs, cookie) 147 bus_space_tag_t bs; 148 void *cookie; 149 { 150 *bs = ixp12x0_bs_tag; 151 bs->bs_cookie = cookie; 152 153 bs->bs_map = ixp12x0_io_bs_map; 154 bs->bs_unmap = ixp12x0_io_bs_unmap; 155 bs->bs_alloc = ixp12x0_io_bs_alloc; 156 bs->bs_free = ixp12x0_io_bs_free; 157 158 bs->bs_vaddr = ixp12x0_io_bs_vaddr; 159 } 160 void 161 ixp12x0_mem_bs_init(bs, cookie) 162 bus_space_tag_t bs; 163 void *cookie; 164 { 165 *bs = ixp12x0_bs_tag; 166 bs->bs_cookie = cookie; 167 168 bs->bs_map = ixp12x0_mem_bs_map; 169 bs->bs_unmap = ixp12x0_mem_bs_unmap; 170 bs->bs_alloc = ixp12x0_mem_bs_alloc; 171 bs->bs_free = ixp12x0_mem_bs_free; 172 173 bs->bs_mmap = ixp12x0_mem_bs_mmap; 174 } 175 176 /* mem bus space functions */ 177 178 int 179 ixp12x0_mem_bs_map(t, bpa, size, cacheable, bshp) 180 void *t; 181 bus_addr_t bpa; 182 bus_size_t size; 183 int cacheable; 184 bus_space_handle_t *bshp; 185 { 186 #if 0 187 struct ixp12x0_softc *sc = t; 188 #endif 189 paddr_t pa, endpa; 190 vaddr_t va; 191 192 if ((bpa + size) >= IXP12X0_PCI_MEM_VBASE + IXP12X0_PCI_MEM_SIZE) 193 return (EINVAL); 194 /* 195 * PCI MEM space is mapped same address as real memory 196 */ 197 198 pa = trunc_page(bpa); 199 endpa = round_page(bpa + size); 200 201 /* XXX use extent manager to check duplicate mapping */ 202 203 va = uvm_km_valloc(kernel_map, endpa - pa); 204 if (va == 0) 205 return(ENOMEM); 206 207 /* Store the bus space handle */ 208 *bshp = va + (bpa & PAGE_MASK); 209 210 for(; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) { 211 pmap_enter(pmap_kernel(), va, pa, 212 VM_PROT_READ | VM_PROT_WRITE, 213 VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED); 214 } 215 pmap_update(pmap_kernel()); 216 217 return(0); 218 } 219 220 void 221 ixp12x0_mem_bs_unmap(t, bsh, size) 222 void *t; 223 bus_space_handle_t bsh; 224 bus_size_t size; 225 { 226 vaddr_t startva, endva; 227 228 startva = trunc_page(bsh); 229 endva = round_page(bsh + size); 230 231 uvm_km_free(kernel_map, startva, endva - startva); 232 } 233 234 int 235 ixp12x0_mem_bs_alloc(t, rstart, rend, size, alignment, boundary, cacheable, 236 bpap, bshp) 237 void *t; 238 bus_addr_t rstart, rend; 239 bus_size_t size, alignment, boundary; 240 int cacheable; 241 bus_addr_t *bpap; 242 bus_space_handle_t *bshp; 243 { 244 panic("ixp12x0_mem_bs_alloc(): Help!"); 245 } 246 247 void 248 ixp12x0_mem_bs_free(t, bsh, size) 249 void *t; 250 bus_space_handle_t bsh; 251 bus_size_t size; 252 { 253 panic("ixp12x0_mem_bs_free(): Help!"); 254 } 255 256 paddr_t 257 ixp12x0_mem_bs_mmap(t, addr, off, prot, flags) 258 void *t; 259 bus_addr_t addr; 260 off_t off; 261 int prot; 262 int flags; 263 { 264 /* Not supported. */ 265 return (-1); 266 } 267 268 /* I/O bus space functions */ 269 270 int 271 ixp12x0_io_bs_map(t, bpa, size, cacheable, bshp) 272 void *t; 273 bus_addr_t bpa; 274 bus_size_t size; 275 int cacheable; 276 bus_space_handle_t *bshp; 277 { 278 #if 0 279 struct ixp12x0_softc *sc = t; 280 #endif 281 #if 0 282 if ((bpa + size) >= IXP12X0_PCI_IO_SIZE) 283 return (EINVAL); 284 #endif 285 /* 286 * PCI I/O space is mapped at virtual address of each evaluation board. 287 * Translate the bus address to the virtual address. 288 */ 289 *bshp = bpa + IXP12X0_PCI_IO_VBASE; 290 291 return(0); 292 } 293 294 void 295 ixp12x0_io_bs_unmap(t, bsh, size) 296 void *t; 297 bus_space_handle_t bsh; 298 bus_size_t size; 299 { 300 /* 301 * Temporary implementation 302 */ 303 } 304 305 int 306 ixp12x0_io_bs_alloc(t, rstart, rend, size, alignment, boundary, cacheable, 307 bpap, bshp) 308 void *t; 309 bus_addr_t rstart, rend; 310 bus_size_t size, alignment, boundary; 311 int cacheable; 312 bus_addr_t *bpap; 313 bus_space_handle_t *bshp; 314 { 315 panic("ixp12x0_io_bs_alloc(): Help!"); 316 } 317 318 void 319 ixp12x0_io_bs_free(t, bsh, size) 320 void *t; 321 bus_space_handle_t bsh; 322 bus_size_t size; 323 { 324 panic("ixp12x0_io_bs_free(): Help!"); 325 } 326 327 void * 328 ixp12x0_io_bs_vaddr(t, bsh) 329 void *t; 330 bus_space_handle_t bsh; 331 { 332 /* Not supported. */ 333 return (NULL); 334 } 335 336 337 /* Common routines */ 338 339 int 340 ixp12x0_bs_subregion(t, bsh, offset, size, nbshp) 341 void *t; 342 bus_space_handle_t bsh; 343 bus_size_t offset, size; 344 bus_space_handle_t *nbshp; 345 { 346 347 *nbshp = bsh + offset; 348 return (0); 349 } 350 351 void * 352 ixp12x0_bs_vaddr(t, bsh) 353 void *t; 354 bus_space_handle_t bsh; 355 { 356 return ((void *)bsh); 357 } 358 359 paddr_t 360 ixp12x0_bs_mmap(t, addr, off, prot, flags) 361 void *t; 362 bus_addr_t addr; 363 off_t off; 364 int prot; 365 int flags; 366 { 367 /* Not supported. */ 368 return (-1); 369 } 370 371 void 372 ixp12x0_bs_barrier(t, bsh, offset, len, flags) 373 void *t; 374 bus_space_handle_t bsh; 375 bus_size_t offset, len; 376 int flags; 377 { 378 /* NULL */ 379 } 380 381 382 383 /* End of ixp12x0_io.c */ 384