1 /* $NetBSD: ixp12x0reg.h,v 1.2 2002/12/02 14:08:58 ichiro Exp $ */ 2 3 /* 4 * Copyright (c) 2002 5 * Ichiro FUKUHARA <ichiro@ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #ifndef _IXP12X0REG_H_ 37 #define _IXP12X0REG_H_ 38 39 /* 40 * Physical memory map for the Intel IXP12X0 41 */ 42 43 /* 44 * FFFF FFFF --------------------------- 45 * Device 6 46 * SDRAM 47 * FF00 0000 - FF00 0014 48 * SDRAM Control Register 49 * D000 0000 - DFFF FFFF 50 * Prefetch 256MB 51 * C000 0000 - CFFF FFFF 52 * non-Prefetch 256MB 53 * C000 0000 --------------------------- 54 * Device 5 55 * AMBA Translation (ATU) 56 * B000 0000 --------------------------- 57 * Device 4 58 * Reserved 59 * A000 0000 --------------------------- 60 * Device 3 61 * StrongARM Core System 62 * 9000 0000 --------------------------- 63 * Device 2 64 * Reserved 65 * 8000 0000 --------------------------- 66 * Device 1 67 * PCI UNIT 68 * 6000 0000 - 7FFF FFFF 69 * PCI Memory Cycle Access 70 * 5400 0000 - 5400 FFFF 71 * PCI I/O Cycle Access 72 * 5300 0000 - 53FF FFFF 73 * PCI Type0 Configuration Cycle Access 74 * 5200 0000 - 52FF FFFF 75 * PCI Type1 Configuration Cycle Access 76 * 4200 0000 - 4200 03FF 77 * Local PCI Configuration Space 78 * 4000 0000 --------------------------- 79 * Device 0 80 * SRAM UNIT 81 * 0000 0000 --------------------------- 82 */ 83 84 85 /* 86 * Virtual memory map for the Intel IXP12X0 integrated devices 87 */ 88 89 /* 90 * FFFF FFFF --------------------------- 91 * 92 * F002 1000 --------------------------- 93 * PCI Registers Accessible Through I/O 94 * VA F001 1000 == PA 5400 0000 (64kbyte) 95 * F001 1000 --------------------------- 96 * PCI Registers Accessible Through StrongARM Core 97 * VA F001 0000 == PA 4200 0000 (4kbyte) 98 * F001 0300 - F001 036F TIMER 99 * F001 0000 --------------------------- 100 * StrongARM System and Peripheral Registers 101 * VA F001 0000 == PA 9000 0000 (64kbyte) 102 * F000 3400 - F000 3C03 UART 103 * F000 3400 - F000 3C03 UART 104 * F000 2000 - F000 3003 RTC 105 * F000 1C00 - F000 1C03 GPIO_DATA 106 * F000 1800 - F000 1C03 GPIO 107 * F000 1400 - F000 1403 IRQ 108 * F000 1000 - F000 1003 FIQ 109 * F000 0C00 - F000 0C03 PLL_CFG 110 * F000 0000 --------------------------- 111 * Kernel text and data 112 * C000 0000 --------------------------- 113 * L2 tables for user process (XXX should be fixed) 114 * 6000 0000 --------------------------- 115 * PCI Registers Accessible Through Memory 116 * 5400 0000 --------------------------- 117 * PCI Type 0 Configuration Cycle Access 118 * VA 5400 0000 == PA 5400 0000 119 * 5300 0000 --------------------------- 120 * PCI Type 1 Configuration Cycle Access 121 * VA 5300 0000 == PA 5300 0000 122 * 5200 0000 --------------------------- 123 * 124 * 0000 0000 --------------------------- 125 * 126 */ 127 128 129 /* Virtual address for I/O space */ 130 #define IXP12X0_IO_VBASE 0xf0000000UL 131 132 /* StrongARM System and Peripheral Registers */ 133 #define IXP12X0_SYS_VBASE IXP12X0_IO_VBASE 134 /* va=0xf0000000 */ 135 #define IXP12X0_SYS_HWBASE 0x90000000UL 136 #define IXP12X0_SYS_SIZE 0x00010000UL /* 64Kbyte */ 137 138 #define IXP12X0_PLL_CFG (IXP12X0_IO_VBASE + 0x0c00) 139 #define IXP12X0_PLL_CFG_CCF 0x1f 140 141 /* PCI Registers Accessible Through StrongARM Core */ 142 #define IXP12X0_PCI_VBASE (IXP12X0_IO_VBASE + IXP12X0_SYS_SIZE) 143 /* va=0xf0010000 */ 144 #define IXP12X0_PCI_HWBASE 0x42000000UL 145 #define IXP12X0_PCI_SIZE 0x00001000UL /* 4Kbyte */ 146 147 /* PCI I/O Space */ 148 #define IXP12X0_PCI_IO_VBASE (IXP12X0_PCI_VBASE + IXP12X0_PCI_SIZE) 149 /* va=0xf0011000 */ 150 #define IXP12X0_PCI_IO_HWBASE 0x54000000UL 151 #define IXP12X0_PCI_IO_SIZE 0x00010000UL /* 64Kbyte */ 152 153 /* PCI Memory Space */ 154 #define IXP12X0_PCI_MEM_HWBASE 0x60000000UL /* VA == PA */ 155 #define IXP12X0_PCI_MEM_VBASE IXP12X0_PCI_MEM_HWBASE 156 #define IXP12X0_PCI_MEM_SIZE 0x20000000UL 157 158 /* PCI Type0/1 Configuration address */ 159 #define IXP12X0_PCI_TYPE0_HWBASE 0x53000000UL /* VA == PA */ 160 #define IXP12X0_PCI_TYPE0_VBASE IXP12X0_PCI_TYPE0_HWBASE 161 162 #define IXP12X0_PCI_TYPE1_HWBASE 0x52000000UL /* VA == PA */ 163 #define IXP12X0_PCI_TYPE1_VBASE IXP12X0_PCI_TYPE1_HWBASE 164 165 #define IXP12X0_PCI_TYPEX_SIZE 0x01000000UL /* 16MB */ 166 167 /* 168 * SlowPort I/O Register 169 */ 170 /* see. arch/evbarm/ixm1200/ixm1200reg.h */ 171 172 /* Physical register base addresses */ 173 /* #define IXP12X0_GPIO_VBASE */ 174 #define IXP12X0_GPIO_HWBASE 0x90001800UL 175 #define IXP12X0_GPIO_SIZE 0x00000800UL 176 177 /* Interrupts */ 178 #define IXP12X0_FIQ_VBASE (IXP12X0_IO_VBASE + 0x1000) 179 #define IXP12X0_FIQ_HWBASE 0x90001000UL 180 #define IXP12X0_FIQ_SIZE 0x00000004UL 181 #define IXP12X0_IRQ_VBASE (IXP12X0_IO_VBASE + 0x1400) 182 #define IXP12X0_IRQ_HWBASE 0x90001400UL 183 #define IXP12X0_IRQ_SIZE 0x00000004UL 184 185 /* 186 * Interrupt index assignment 187 * 188 * 189 * FIQ/IRQ bitmap in "StrongARM System and Peripheral Registers" 190 * 191 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 192 * bit 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 193 * +-+-------------------------------------------+-+-+-+-+-+-+-+---+ 194 * |M| |U|S|R|S|U|C|P| | 195 * |B| |A|D|T|R|E|I|C| | 196 * |Z| RES |R|R|C|A|N|N|I|RES| 197 * | | |T|A| |M|G|T| | | 198 * | | | |M| | | | | | | 199 * +-+-------------------------------------------+-+-+-+-+-+-+-+---+ 200 * 3 201 * index 1 8 7 6 5 4 3 2 202 * 203 * 204 * We Map a software interrupt queue index to the unused bits in the 205 * IRQ/FIQ registers. (in "StrongARM System and Peripheral Registers") 206 * 207 * XXX will need to revisit this if those bits are ever used in future 208 * steppings). 209 * 210 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 211 * bit 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 212 * +-+-+-+-+-+-----------------------------------+-+-+-+-+-+-+-+---+ 213 * |M|S|C|N|S| |U|S|R|S|U|C|P| | 214 * |B|O|L|E|E| |A|D|T|R|E|I|C| | 215 * |Z|F|O|T|R| RES |R|R|C|A|N|N|I|RES| 216 * | |T|C| |I| |T|A| |M|G|T| | | 217 * | | |K| |A| | |M| | | | | | | 218 * | | | | |L| | | | | | | | | | 219 * +-+-+-+-+-+-----------------------------------+-+-+-+-+-+-+-+---+ 220 * 3 3 2 2 2 221 * index 1 0 9 8 7 8 7 6 5 4 3 2 222 * 223 */ 224 225 #define NIRQ 64 226 #define SYS_NIRQ 32 227 228 #define IXP12X0_INTR_MBZ 31 229 #define IXP12X0_INTR_bit30 30 230 #define IXP12X0_INTR_bit29 29 231 #define IXP12X0_INTR_bit28 28 232 #define IXP12X0_INTR_bit27 27 233 #define IXP12X0_INTR_bit26 26 234 #define IXP12X0_INTR_bit25 25 235 #define IXP12X0_INTR_bit24 24 236 #define IXP12X0_INTR_bit23 23 237 #define IXP12X0_INTR_bit22 22 238 #define IXP12X0_INTR_bit21 21 239 #define IXP12X0_INTR_bit20 20 240 #define IXP12X0_INTR_bit19 19 241 #define IXP12X0_INTR_bit18 18 242 #define IXP12X0_INTR_bit17 17 243 #define IXP12X0_INTR_bit16 16 244 #define IXP12X0_INTR_bit15 15 245 #define IXP12X0_INTR_bit14 14 246 #define IXP12X0_INTR_bit13 13 247 #define IXP12X0_INTR_bit12 12 248 #define IXP12X0_INTR_bit11 11 249 #define IXP12X0_INTR_bit10 10 250 #define IXP12X0_INTR_bit9 9 251 #define IXP12X0_INTR_UART 8 252 #define IXP12X0_INTR_SDRAM 7 253 #define IXP12X0_INTR_RTC 6 254 #define IXP12X0_INTR_SRAM 5 255 #define IXP12X0_INTR_UENG 4 256 #define IXP12X0_INTR_CINT 3 257 #define IXP12X0_INTR_PCI 2 258 #define IXP12X0_INTR_bit1 1 259 #define IXP12X0_INTR_bit0 0 260 261 #define IXP12X0_INTR_MASK \ 262 ((1U << IXP12X0_INTR_MBZ) \ 263 | (1U << IXP12X0_INTR_UART) \ 264 | (1U << IXP12X0_INTR_SDRAM) \ 265 | (1U << IXP12X0_INTR_RTC) \ 266 | (1U << IXP12X0_INTR_SRAM) \ 267 | (1U << IXP12X0_INTR_UENG) \ 268 | (1U << IXP12X0_INTR_CINT)) 269 270 #endif /* _IXP12X0REG_H_ */ 271