1 /* $NetBSD: mvsocreg.h,v 1.2 2011/02/01 22:54:24 jakllsch Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _MVSOCREG_H_ 29 #define _MVSOCREG_H_ 30 31 #define MVSOC_UNITID_MASK 0xf 32 #define MVSOC_UNITID_DDR 0x0 /* DDR registers */ 33 #define MVSOC_UNITID_DEVBUS 0x1 /* Device Bus registers */ 34 #define MVSOC_UNITID_MLMB 0x2 /* Mbus-L to Mbus Bridge reg */ 35 #define MVSOC_UNITID_PEX 0x4 /* PCI Express Interface reg */ 36 37 38 /* 39 * Physical address of integrated peripherals 40 */ 41 42 #define UNITID2PHYS(uid) ((MVSOC_UNITID_ ## uid) << 16) 43 44 /* 45 * DDR SDRAM Controller Registers 46 */ 47 #define MVSOC_DDR_BASE (UNITID2PHYS(DDR)) /* 0x00000 */ 48 49 /* DDR SDRAM Contriller Address Decode Registers */ 50 #define MVSOC_DSC_BASE 0x01500 /* DDR SDRAM Ctrl Addr Reg */ 51 #define MVSOC_DSC_NCS 4 52 #define MVSOC_DSC_CSBAR(x) ((x) * 8) 53 #define MVSOC_DSC_CSBAR_BASE_MASK 0xff000000 54 #define MVSOC_DSC_CSSR(x) ((x) * 8 + 4) 55 #define MVSOC_DSC_CSSR_WINEN 0x00000001 56 #define MVSOC_DSC_CSSR_SIZE_MASK 0xff000000 57 58 59 /* 60 * Device Bus 61 */ 62 #define MVSOC_DEVBUS_BASE (UNITID2PHYS(DEVBUS)) /* 0x10000 */ 63 64 /* 65 * General Purpose Port Registers 66 */ 67 #define MVSOC_GPP_BASE (MVSOC_DEVBUS_BASE + 0x0100) 68 69 /* 70 * Two-Wire Serial Interface Registers 71 */ 72 #define MVSOC_TWSI_BASE (MVSOC_DEVBUS_BASE + 0x1000) 73 74 /* 75 * UART Interface Registers 76 */ 77 /* NS16550 compatible */ 78 #define MVSOC_COM0_BASE (MVSOC_DEVBUS_BASE + 0x2000) 79 #define MVSOC_COM1_BASE (MVSOC_DEVBUS_BASE + 0x2100) 80 81 /* 82 * Mbus-L to Mbus Bridge Registers 83 */ 84 #define MVSOC_MLMB_BASE (UNITID2PHYS(MLMB)) /* 0x20000 */ 85 86 /* CPU Address Map Registers */ 87 #define MVSOC_MLMB_WCR(w) (((w) << 4) + 0x0) 88 #define MVSOC_MLMB_WCR_WINEN (1 << 0) 89 #define MVSOC_MLMB_WCR_TARGET(t) (((t) & 0xf) << 4) 90 #define MVSOC_MLMB_WCR_ATTR(a) (((a) & 0xff) << 8) 91 #define MVSOC_MLMB_WCR_SIZE_MASK 0xffff0000 92 #define MVSOC_MLMB_WCR_SIZE(s) (((s) - 1) & MVSOC_MLMB_WCR_SIZE_MASK) 93 #define MVSOC_MLMB_WBR(w) (((w) << 4) + 0x4) 94 #define MVSOC_MLMB_WBR_BASE_MASK 0xffff0000 95 #define MVSOC_MLMB_WRLR(w) (((w) << 4) + 0x8) 96 #define MVSOC_MLMB_WRLR_REMAP_MASK 0xffff0000 97 #define MVSOC_MLMB_WRHR(w) (((w) << 4) + 0xc) 98 #define MVSOC_MLMB_IRBAR 0x080 /* Internal regs Base Address */ 99 #define MVSOC_MLMB_IRBAR_BASE_MASK 0xfff00000 100 101 /* CPU Control and Status Registers */ 102 #define MVSOC_MLMB_CPUCR 0x100 /* CPU Configuration Register */ 103 #define MVSOC_MLMB_CPUCSR 0x104 /* CPU Control/Status Register*/ 104 #define MVSOC_MLMB_RSTOUTNMASKR 0x108 /* RSTOUTn Mask Register */ 105 #define MVSOC_MLMB_RSTOUTNMASKR_PEXRSTOUTEN (1 << 0) 106 #define MVSOC_MLMB_RSTOUTNMASKR_WDRSTOUTEN (1 << 1) 107 #define MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN (1 << 2) 108 #define MVSOC_MLMB_SSRR 0x10c /* System Soft Reset Register */ 109 #define MVSOC_MLMB_SSRR_SYSTEMSOFTRST (1 << 0) 110 #define MVSOC_MLMB_MLMBICR 0x110 /*Mb-L to Mb Bridge Intr Cause*/ 111 #define MVSOC_MLMB_MLMBIMR 0x114 /*Mb-L to Mb Bridge Intr Mask */ 112 113 #define MVSOC_MLMB_L2CFG 0x128 /* L2 Cache Config */ 114 115 #define MVSOC_TMR_BASE (MVSOC_MLMB_BASE + 0x0300) 116 117 /* CPU Doorbell Registers */ 118 #define MVSOC_MLMB_H2CDR 0x400 /* Host-to-CPU Doorbell */ 119 #define MVSOC_MLMB_H2CDMR 0x404 /* Host-to-CPU Doorbell Mask */ 120 #define MVSOC_MLMB_C2HDR 0x408 /* CPU-to-Host Doorbell */ 121 #define MVSOC_MLMB_C2HDMR 0x40c /* CPU-to-Host Doorbell Mask */ 122 123 /* Local to System Bridge Interrupt {Cause,Mask} Register bits */ 124 #define MVSOC_MLMB_MLMBI_CPUSELFINT 0 125 #define MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ 1 126 #define MVSOC_MLMB_MLMBI_CPUTIMER1INTREQ 2 127 #define MVSOC_MLMB_MLMBI_CPUWDTIMERINTREQ 3 128 #define MVSOC_MLMB_MLMBI_ACCESSERR 4 129 #define MVSOC_MLMB_MLMBI_BIT64ERR 5 130 131 #define MVSOC_MLMB_MLMBI_NIRQ 6 132 133 /* 134 * PCI-Express Interface Registers 135 */ 136 #define MVSOC_PEX_BASE (UNITID2PHYS(PEX)) /* 0x40000 */ 137 138 #endif /* _MVSOCREG_H_ */ 139