1*799005bcSriastradh /* $NetBSD: tegra124_car.c,v 1.24 2022/03/19 11:37:17 riastradh Exp $ */
2cfee7739Sjmcneill
3cfee7739Sjmcneill /*-
4cfee7739Sjmcneill * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5cfee7739Sjmcneill * All rights reserved.
6cfee7739Sjmcneill *
7cfee7739Sjmcneill * Redistribution and use in source and binary forms, with or without
8cfee7739Sjmcneill * modification, are permitted provided that the following conditions
9cfee7739Sjmcneill * are met:
10cfee7739Sjmcneill * 1. Redistributions of source code must retain the above copyright
11cfee7739Sjmcneill * notice, this list of conditions and the following disclaimer.
12cfee7739Sjmcneill * 2. Redistributions in binary form must reproduce the above copyright
13cfee7739Sjmcneill * notice, this list of conditions and the following disclaimer in the
14cfee7739Sjmcneill * documentation and/or other materials provided with the distribution.
15cfee7739Sjmcneill *
16cfee7739Sjmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17cfee7739Sjmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18cfee7739Sjmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19cfee7739Sjmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20cfee7739Sjmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21cfee7739Sjmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22cfee7739Sjmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23cfee7739Sjmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24cfee7739Sjmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25cfee7739Sjmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26cfee7739Sjmcneill * SUCH DAMAGE.
27cfee7739Sjmcneill */
28cfee7739Sjmcneill
29cfee7739Sjmcneill #include <sys/cdefs.h>
30*799005bcSriastradh __KERNEL_RCSID(0, "$NetBSD: tegra124_car.c,v 1.24 2022/03/19 11:37:17 riastradh Exp $");
31cfee7739Sjmcneill
32cfee7739Sjmcneill #include <sys/param.h>
33cfee7739Sjmcneill #include <sys/bus.h>
34cfee7739Sjmcneill #include <sys/device.h>
35cfee7739Sjmcneill #include <sys/intr.h>
36cfee7739Sjmcneill #include <sys/systm.h>
37cfee7739Sjmcneill #include <sys/kernel.h>
38cfee7739Sjmcneill #include <sys/rndsource.h>
39cfee7739Sjmcneill #include <sys/atomic.h>
40cfee7739Sjmcneill #include <sys/kmem.h>
41cfee7739Sjmcneill
42cfee7739Sjmcneill #include <dev/clk/clk_backend.h>
43cfee7739Sjmcneill
44cfee7739Sjmcneill #include <arm/nvidia/tegra_reg.h>
45cfee7739Sjmcneill #include <arm/nvidia/tegra124_carreg.h>
46cfee7739Sjmcneill #include <arm/nvidia/tegra_clock.h>
47cfee7739Sjmcneill #include <arm/nvidia/tegra_pmcreg.h>
48cfee7739Sjmcneill #include <arm/nvidia/tegra_var.h>
49cfee7739Sjmcneill
50cfee7739Sjmcneill #include <dev/fdt/fdtvar.h>
51cfee7739Sjmcneill
52cfee7739Sjmcneill static int tegra124_car_match(device_t, cfdata_t, void *);
53cfee7739Sjmcneill static void tegra124_car_attach(device_t, device_t, void *);
54cfee7739Sjmcneill
55cdeb425bSaymeric static struct clk *tegra124_car_clock_decode(device_t, int, const void *,
56cdeb425bSaymeric size_t);
57cfee7739Sjmcneill
58cfee7739Sjmcneill static const struct fdtbus_clock_controller_func tegra124_car_fdtclock_funcs = {
59cfee7739Sjmcneill .decode = tegra124_car_clock_decode
60cfee7739Sjmcneill };
61cfee7739Sjmcneill
62cfee7739Sjmcneill /* DT clock ID to clock name mappings */
63cfee7739Sjmcneill static struct tegra124_car_clock_id {
64cfee7739Sjmcneill u_int id;
65cfee7739Sjmcneill const char *name;
66cfee7739Sjmcneill } tegra124_car_clock_ids[] = {
67cfee7739Sjmcneill { 3, "ispb" },
68cfee7739Sjmcneill { 4, "rtc" },
69cfee7739Sjmcneill { 5, "timer" },
70cfee7739Sjmcneill { 6, "uarta" },
71cfee7739Sjmcneill { 9, "sdmmc2" },
72cfee7739Sjmcneill { 11, "i2s1" },
73cfee7739Sjmcneill { 12, "i2c1" },
74cfee7739Sjmcneill { 14, "sdmmc1" },
75cfee7739Sjmcneill { 15, "sdmmc4" },
76cfee7739Sjmcneill { 17, "pwm" },
77cfee7739Sjmcneill { 18, "i2s2" },
78cfee7739Sjmcneill { 22, "usbd" },
79cfee7739Sjmcneill { 23, "isp" },
80cfee7739Sjmcneill { 26, "disp2" },
81cfee7739Sjmcneill { 27, "disp1" },
82cfee7739Sjmcneill { 28, "host1x" },
83cfee7739Sjmcneill { 29, "vcp" },
84cfee7739Sjmcneill { 30, "i2s0" },
85cfee7739Sjmcneill { 32, "mc" },
86cfee7739Sjmcneill { 34, "apbdma" },
87cfee7739Sjmcneill { 36, "kbc" },
88cfee7739Sjmcneill { 40, "kfuse" },
894e889696Sjakllsch { 41, "spi1" },
90cfee7739Sjmcneill { 42, "nor" },
914e889696Sjakllsch { 44, "spi2" },
924e889696Sjakllsch { 46, "spi3" },
93cfee7739Sjmcneill { 47, "i2c5" },
94cfee7739Sjmcneill { 48, "dsia" },
95cfee7739Sjmcneill { 50, "mipi" },
96cfee7739Sjmcneill { 51, "hdmi" },
97cfee7739Sjmcneill { 52, "csi" },
98cfee7739Sjmcneill { 54, "i2c2" },
99cfee7739Sjmcneill { 55, "uartc" },
100cfee7739Sjmcneill { 56, "mipi_cal" },
101cfee7739Sjmcneill { 57, "emc" },
102cfee7739Sjmcneill { 58, "usb2" },
103cfee7739Sjmcneill { 59, "usb3" },
104cfee7739Sjmcneill { 61, "vde" },
105cfee7739Sjmcneill { 62, "bsea" },
106cfee7739Sjmcneill { 63, "bsev" },
107cfee7739Sjmcneill { 65, "uartd" },
108cfee7739Sjmcneill { 67, "i2c3" },
1094e889696Sjakllsch { 68, "spi4" },
110cfee7739Sjmcneill { 69, "sdmmc3" },
111cfee7739Sjmcneill { 70, "pcie" },
112cfee7739Sjmcneill { 71, "owr" },
113cfee7739Sjmcneill { 72, "afi" },
114cfee7739Sjmcneill { 73, "csite" },
115cfee7739Sjmcneill { 76, "la" },
116cfee7739Sjmcneill { 77, "trace" },
117cfee7739Sjmcneill { 78, "soc_therm" },
118cfee7739Sjmcneill { 79, "dtv" },
119cfee7739Sjmcneill { 81, "i2cslow" },
120cfee7739Sjmcneill { 82, "dsib" },
121cfee7739Sjmcneill { 83, "tsec" },
122cfee7739Sjmcneill { 89, "xusb_host" },
123cfee7739Sjmcneill { 91, "msenc" },
124cfee7739Sjmcneill { 92, "csus" },
125cfee7739Sjmcneill { 99, "mselect" },
126cfee7739Sjmcneill { 100, "tsensor" },
127cfee7739Sjmcneill { 101, "i2s3" },
128cfee7739Sjmcneill { 102, "i2s4" },
129cfee7739Sjmcneill { 103, "i2c4" },
1304e889696Sjakllsch { 104, "spi5" },
1314e889696Sjakllsch { 105, "spi6" },
132cfee7739Sjmcneill { 106, "d_audio" },
133cfee7739Sjmcneill { 107, "apbif" },
134cfee7739Sjmcneill { 108, "dam0" },
135cfee7739Sjmcneill { 109, "dam1" },
136cfee7739Sjmcneill { 110, "dam2" },
137cfee7739Sjmcneill { 111, "hda2codec_2x" },
138cfee7739Sjmcneill { 113, "audio0_2x" },
139cfee7739Sjmcneill { 114, "audio1_2x" },
140cfee7739Sjmcneill { 115, "audio2_2x" },
141cfee7739Sjmcneill { 116, "audio3_2x" },
142cfee7739Sjmcneill { 117, "audio4_2x" },
143cfee7739Sjmcneill { 118, "spdif_2x" },
144cfee7739Sjmcneill { 119, "actmon" },
145cfee7739Sjmcneill { 120, "extern1" },
146cfee7739Sjmcneill { 121, "extern2" },
147cfee7739Sjmcneill { 122, "extern3" },
148cfee7739Sjmcneill { 123, "sata_oob" },
149cfee7739Sjmcneill { 124, "sata" },
150cfee7739Sjmcneill { 125, "hda" },
151cfee7739Sjmcneill { 127, "se" },
152cfee7739Sjmcneill { 128, "hda2hdmi" },
153cfee7739Sjmcneill { 129, "sata_cold" },
1549ad6de64Sjmcneill { 136, "cec" },
155cfee7739Sjmcneill { 144, "cilab" },
156cfee7739Sjmcneill { 145, "cilcd" },
157cfee7739Sjmcneill { 146, "cile" },
158cfee7739Sjmcneill { 147, "dsialp" },
159cfee7739Sjmcneill { 148, "dsiblp" },
160cfee7739Sjmcneill { 149, "entropy" },
161cfee7739Sjmcneill { 150, "dds" },
162cfee7739Sjmcneill { 152, "dp2" },
163cfee7739Sjmcneill { 153, "amx" },
164cfee7739Sjmcneill { 154, "adx" },
165cfee7739Sjmcneill { 156, "xusb_ss" },
166cfee7739Sjmcneill { 166, "i2c6" },
167cfee7739Sjmcneill { 171, "vim2_clk" },
168cfee7739Sjmcneill { 176, "hdmi_audio" },
169cfee7739Sjmcneill { 177, "clk72mhz" },
170cfee7739Sjmcneill { 178, "vic03" },
171cfee7739Sjmcneill { 180, "adx1" },
172cfee7739Sjmcneill { 181, "dpaux" },
173cfee7739Sjmcneill { 182, "sor0" },
174cfee7739Sjmcneill { 184, "gpu" },
175cfee7739Sjmcneill { 185, "amx1" },
176cfee7739Sjmcneill { 192, "uartb" },
177cfee7739Sjmcneill { 193, "vfir" },
178cfee7739Sjmcneill { 194, "spdif_in" },
179cfee7739Sjmcneill { 195, "spdif_out" },
180cfee7739Sjmcneill { 196, "vi" },
181cfee7739Sjmcneill { 197, "vi_sensor" },
182cfee7739Sjmcneill { 198, "fuse" },
183cfee7739Sjmcneill { 199, "fuse_burn" },
184cfee7739Sjmcneill { 200, "clk_32k" },
185cfee7739Sjmcneill { 201, "clk_m" },
186cfee7739Sjmcneill { 202, "clk_m_div2" },
187cfee7739Sjmcneill { 203, "clk_m_div4" },
188cfee7739Sjmcneill { 204, "pll_ref" },
189cfee7739Sjmcneill { 205, "pll_c" },
190cfee7739Sjmcneill { 206, "pll_c_out1" },
191cfee7739Sjmcneill { 207, "pll_c2" },
192cfee7739Sjmcneill { 208, "pll_c3" },
193cfee7739Sjmcneill { 209, "pll_m" },
194cfee7739Sjmcneill { 210, "pll_m_out1" },
1952f49bee0Sjmcneill { 211, "pll_p_out0" },
196cfee7739Sjmcneill { 212, "pll_p_out1" },
197cfee7739Sjmcneill { 213, "pll_p_out2" },
198cfee7739Sjmcneill { 214, "pll_p_out3" },
199cfee7739Sjmcneill { 215, "pll_p_out4" },
200cfee7739Sjmcneill { 216, "pll_a" },
201cfee7739Sjmcneill { 217, "pll_a_out0" },
202cfee7739Sjmcneill { 218, "pll_d" },
203cfee7739Sjmcneill { 219, "pll_d_out0" },
204cfee7739Sjmcneill { 220, "pll_d2" },
205cfee7739Sjmcneill { 221, "pll_d2_out0" },
206cfee7739Sjmcneill { 222, "pll_u" },
207cfee7739Sjmcneill { 223, "pll_u_480m" },
208cfee7739Sjmcneill { 224, "pll_u_60m" },
209cfee7739Sjmcneill { 225, "pll_u_48m" },
210cfee7739Sjmcneill { 226, "pll_u_12m" },
211cfee7739Sjmcneill { 229, "pll_re_vco" },
212cfee7739Sjmcneill { 230, "pll_re_out" },
213cfee7739Sjmcneill { 231, "pll_e" },
214cfee7739Sjmcneill { 232, "spdif_in_sync" },
215cfee7739Sjmcneill { 233, "i2s0_sync" },
216cfee7739Sjmcneill { 234, "i2s1_sync" },
217cfee7739Sjmcneill { 235, "i2s2_sync" },
218cfee7739Sjmcneill { 236, "i2s3_sync" },
219cfee7739Sjmcneill { 237, "i2s4_sync" },
220cfee7739Sjmcneill { 238, "vimclk_sync" },
221cfee7739Sjmcneill { 239, "audio0" },
222cfee7739Sjmcneill { 240, "audio1" },
223cfee7739Sjmcneill { 241, "audio2" },
224cfee7739Sjmcneill { 242, "audio3" },
225cfee7739Sjmcneill { 243, "audio4" },
226cfee7739Sjmcneill { 244, "spdif" },
227cfee7739Sjmcneill { 245, "clk_out_1" },
228cfee7739Sjmcneill { 246, "clk_out_2" },
229cfee7739Sjmcneill { 247, "clk_out_3" },
230cfee7739Sjmcneill { 248, "blink" },
231cfee7739Sjmcneill { 252, "xusb_host_src" },
232cfee7739Sjmcneill { 253, "xusb_falcon_src" },
233cfee7739Sjmcneill { 254, "xusb_fs_src" },
234cfee7739Sjmcneill { 255, "xusb_ss_src" },
235cfee7739Sjmcneill { 256, "xusb_dev_src" },
236cfee7739Sjmcneill { 257, "xusb_dev" },
237cfee7739Sjmcneill { 258, "xusb_hs_src" },
238cfee7739Sjmcneill { 259, "sclk" },
239cfee7739Sjmcneill { 260, "hclk" },
240cfee7739Sjmcneill { 261, "pclk" },
241cfee7739Sjmcneill { 264, "dfll_ref" },
242cfee7739Sjmcneill { 265, "dfll_soc" },
243cfee7739Sjmcneill { 266, "vi_sensor2" },
244cfee7739Sjmcneill { 267, "pll_p_out5" },
245cfee7739Sjmcneill { 268, "cml0" },
246cfee7739Sjmcneill { 269, "cml1" },
247cfee7739Sjmcneill { 270, "pll_c4" },
248cfee7739Sjmcneill { 271, "pll_dp" },
249cfee7739Sjmcneill { 272, "pll_e_mux" },
250cfee7739Sjmcneill { 273, "pll_d_dsi_out" },
251cfee7739Sjmcneill { 300, "audio0_mux" },
252cfee7739Sjmcneill { 301, "audio1_mux" },
253cfee7739Sjmcneill { 302, "audio2_mux" },
254cfee7739Sjmcneill { 303, "audio3_mux" },
255cfee7739Sjmcneill { 304, "audio4_mux" },
256cfee7739Sjmcneill { 305, "spdif_mux" },
257cfee7739Sjmcneill { 306, "clk_out_1_mux" },
258cfee7739Sjmcneill { 307, "clk_out_2_mux" },
259cfee7739Sjmcneill { 308, "clk_out_3_mux" },
260cfee7739Sjmcneill { 311, "sor0_lvds" },
261cfee7739Sjmcneill { 312, "xusb_ss_div2" },
262cfee7739Sjmcneill { 313, "pll_m_ud" },
263cfee7739Sjmcneill { 314, "pll_c_ud" },
264cfee7739Sjmcneill { 227, "pll_x" },
265cfee7739Sjmcneill { 228, "pll_x_out0" },
266cfee7739Sjmcneill { 262, "cclk_g" },
267cfee7739Sjmcneill { 263, "cclk_lp" },
268cfee7739Sjmcneill { 315, "clk_max" },
269cfee7739Sjmcneill };
270cfee7739Sjmcneill
271cfee7739Sjmcneill static struct clk *tegra124_car_clock_get(void *, const char *);
272cfee7739Sjmcneill static void tegra124_car_clock_put(void *, struct clk *);
273cfee7739Sjmcneill static u_int tegra124_car_clock_get_rate(void *, struct clk *);
274cfee7739Sjmcneill static int tegra124_car_clock_set_rate(void *, struct clk *, u_int);
275cfee7739Sjmcneill static int tegra124_car_clock_enable(void *, struct clk *);
276cfee7739Sjmcneill static int tegra124_car_clock_disable(void *, struct clk *);
277cfee7739Sjmcneill static int tegra124_car_clock_set_parent(void *, struct clk *,
278cfee7739Sjmcneill struct clk *);
279cfee7739Sjmcneill static struct clk *tegra124_car_clock_get_parent(void *, struct clk *);
280cfee7739Sjmcneill
281cfee7739Sjmcneill static const struct clk_funcs tegra124_car_clock_funcs = {
282cfee7739Sjmcneill .get = tegra124_car_clock_get,
283cfee7739Sjmcneill .put = tegra124_car_clock_put,
284cfee7739Sjmcneill .get_rate = tegra124_car_clock_get_rate,
285cfee7739Sjmcneill .set_rate = tegra124_car_clock_set_rate,
286cfee7739Sjmcneill .enable = tegra124_car_clock_enable,
287cfee7739Sjmcneill .disable = tegra124_car_clock_disable,
288cfee7739Sjmcneill .set_parent = tegra124_car_clock_set_parent,
289cfee7739Sjmcneill .get_parent = tegra124_car_clock_get_parent,
290cfee7739Sjmcneill };
291cfee7739Sjmcneill
292cfee7739Sjmcneill #define CLK_FIXED(_name, _rate) { \
293cfee7739Sjmcneill .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \
294cfee7739Sjmcneill .u = { .fixed = { .rate = (_rate) } } \
295cfee7739Sjmcneill }
296cfee7739Sjmcneill
297cfee7739Sjmcneill #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \
298cfee7739Sjmcneill .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \
299cfee7739Sjmcneill .parent = (_parent), \
300cfee7739Sjmcneill .u = { \
301cfee7739Sjmcneill .pll = { \
302cfee7739Sjmcneill .base_reg = (_base), \
303cfee7739Sjmcneill .divm_mask = (_divm), \
304cfee7739Sjmcneill .divn_mask = (_divn), \
305cfee7739Sjmcneill .divp_mask = (_divp), \
306cfee7739Sjmcneill } \
307cfee7739Sjmcneill } \
308cfee7739Sjmcneill }
309cfee7739Sjmcneill
310cfee7739Sjmcneill #define CLK_MUX(_name, _reg, _bits, _p) { \
311cfee7739Sjmcneill .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \
312cfee7739Sjmcneill .u = { \
313cfee7739Sjmcneill .mux = { \
314cfee7739Sjmcneill .nparents = __arraycount(_p), \
315cfee7739Sjmcneill .parents = (_p), \
316cfee7739Sjmcneill .reg = (_reg), \
317cfee7739Sjmcneill .bits = (_bits) \
318cfee7739Sjmcneill } \
319cfee7739Sjmcneill } \
320cfee7739Sjmcneill }
321cfee7739Sjmcneill
322cfee7739Sjmcneill #define CLK_FIXED_DIV(_name, _parent, _div) { \
323cfee7739Sjmcneill .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \
324cfee7739Sjmcneill .parent = (_parent), \
325cfee7739Sjmcneill .u = { \
326cfee7739Sjmcneill .fixed_div = { \
327cfee7739Sjmcneill .div = (_div) \
328cfee7739Sjmcneill } \
329cfee7739Sjmcneill } \
330cfee7739Sjmcneill }
331cfee7739Sjmcneill
332cfee7739Sjmcneill #define CLK_DIV(_name, _parent, _reg, _bits) { \
333cfee7739Sjmcneill .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \
334cfee7739Sjmcneill .parent = (_parent), \
335cfee7739Sjmcneill .u = { \
336cfee7739Sjmcneill .div = { \
337cfee7739Sjmcneill .reg = (_reg), \
338cfee7739Sjmcneill .bits = (_bits) \
339cfee7739Sjmcneill } \
340cfee7739Sjmcneill } \
341cfee7739Sjmcneill }
342cfee7739Sjmcneill
343cfee7739Sjmcneill #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \
344cfee7739Sjmcneill .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
345cfee7739Sjmcneill .type = TEGRA_CLK_GATE, \
346cfee7739Sjmcneill .parent = (_parent), \
347cfee7739Sjmcneill .u = { \
348cfee7739Sjmcneill .gate = { \
349cfee7739Sjmcneill .set_reg = (_set), \
350cfee7739Sjmcneill .clr_reg = (_clr), \
351cfee7739Sjmcneill .bits = (_bits), \
352cfee7739Sjmcneill } \
353cfee7739Sjmcneill } \
354cfee7739Sjmcneill }
355cfee7739Sjmcneill
356cfee7739Sjmcneill #define CLK_GATE_L(_name, _parent, _bits) \
357cfee7739Sjmcneill CLK_GATE(_name, _parent, \
358cfee7739Sjmcneill CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \
359cfee7739Sjmcneill _bits)
360cfee7739Sjmcneill
361cfee7739Sjmcneill #define CLK_GATE_H(_name, _parent, _bits) \
362cfee7739Sjmcneill CLK_GATE(_name, _parent, \
363cfee7739Sjmcneill CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \
364cfee7739Sjmcneill _bits)
365cfee7739Sjmcneill
366cfee7739Sjmcneill #define CLK_GATE_U(_name, _parent, _bits) \
367cfee7739Sjmcneill CLK_GATE(_name, _parent, \
368cfee7739Sjmcneill CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \
369cfee7739Sjmcneill _bits)
370cfee7739Sjmcneill
371cfee7739Sjmcneill #define CLK_GATE_V(_name, _parent, _bits) \
372cfee7739Sjmcneill CLK_GATE(_name, _parent, \
373cfee7739Sjmcneill CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \
374cfee7739Sjmcneill _bits)
375cfee7739Sjmcneill
376cfee7739Sjmcneill #define CLK_GATE_W(_name, _parent, _bits) \
377cfee7739Sjmcneill CLK_GATE(_name, _parent, \
378cfee7739Sjmcneill CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \
379cfee7739Sjmcneill _bits)
380cfee7739Sjmcneill
381cfee7739Sjmcneill #define CLK_GATE_X(_name, _parent, _bits) \
382cfee7739Sjmcneill CLK_GATE(_name, _parent, \
383cfee7739Sjmcneill CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \
384cfee7739Sjmcneill _bits)
385cfee7739Sjmcneill
386cfee7739Sjmcneill #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \
387cfee7739Sjmcneill CLK_GATE(_name, _parent, _reg, _reg, _bits)
388cfee7739Sjmcneill
389cfee7739Sjmcneill static const char *mux_uart_p[] =
390cfee7739Sjmcneill { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
391cfee7739Sjmcneill "pll_m_out0", NULL, "clk_m" };
392cfee7739Sjmcneill static const char *mux_sdmmc_p[] =
393cfee7739Sjmcneill { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
394cfee7739Sjmcneill "pll_m_out0", "pll_e_out0", "clk_m" };
395cfee7739Sjmcneill static const char *mux_i2c_p[] =
396cfee7739Sjmcneill { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
397cfee7739Sjmcneill "pll_m_out0", NULL, "clk_m" };
3984e889696Sjakllsch static const char *mux_spi_p[] =
3994e889696Sjakllsch { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
4004e889696Sjakllsch "pll_m_out0", NULL, "clk_m" };
401cfee7739Sjmcneill static const char *mux_sata_p[] =
402cfee7739Sjmcneill { "pll_p_out0", NULL, "pll_c_out0", NULL, "pll_m_out0", NULL, "clk_m" };
403cfee7739Sjmcneill static const char *mux_hda_p[] =
404cfee7739Sjmcneill { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
405cfee7739Sjmcneill "pll_m_out0", NULL, "clk_m" };
406b44ae13aSjakllsch static const char *mux_mselect_p[] =
407b44ae13aSjakllsch { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
408b44ae13aSjakllsch "pll_m_out0", "clk_s", "clk_m" };
409cfee7739Sjmcneill static const char *mux_tsensor_p[] =
410cfee7739Sjmcneill { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", "clk_m",
411cfee7739Sjmcneill NULL, "clk_s" };
412cfee7739Sjmcneill static const char *mux_soc_therm_p[] =
413cfee7739Sjmcneill { "pll_m_out0", "pll_c_out0", "pll_p_out0", "pll_a_out0", "pll_c2_out0",
414cfee7739Sjmcneill "pll_c3_out0" };
415cfee7739Sjmcneill static const char *mux_host1x_p[] =
416cfee7739Sjmcneill { "pll_m_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
417cfee7739Sjmcneill "pll_p_out0", NULL, "pll_a_out0" };
418cfee7739Sjmcneill static const char *mux_disp_p[] =
419cfee7739Sjmcneill { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0",
420cfee7739Sjmcneill "pll_d2_out0", "clk_m" };
421cfee7739Sjmcneill static const char *mux_hdmi_p[] =
422cfee7739Sjmcneill { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0",
423cfee7739Sjmcneill "pll_d2_out0", "clk_m" };
424137a7d5aSjakllsch static const char *mux_xusb_host_p[] =
425137a7d5aSjakllsch { "clk_m", "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
426137a7d5aSjakllsch "pll_re_out" };
427137a7d5aSjakllsch static const char *mux_xusb_ss_p[] =
428137a7d5aSjakllsch { "clk_m", "pll_re_out", "clk_s", "pll_u_480",
429137a7d5aSjakllsch "pll_c_out0", "pll_c2_out0", "pll_c3_out0", NULL };
430137a7d5aSjakllsch static const char *mux_xusb_fs_p[] =
431137a7d5aSjakllsch { "clk_m", NULL, "pll_u_48", NULL, "pll_p_out0", NULL, "pll_u_480" };
432cfee7739Sjmcneill
433cfee7739Sjmcneill static struct tegra_clk tegra124_car_clocks[] = {
434c47fe736Sjmcneill CLK_FIXED("clk_m", TEGRA124_REF_FREQ),
435cfee7739Sjmcneill
436cfee7739Sjmcneill CLK_PLL("pll_p", "clk_m", CAR_PLLP_BASE_REG,
437cfee7739Sjmcneill CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP),
438cfee7739Sjmcneill CLK_PLL("pll_c", "clk_m", CAR_PLLC_BASE_REG,
439cfee7739Sjmcneill CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP),
440cfee7739Sjmcneill CLK_PLL("pll_u", "clk_m", CAR_PLLU_BASE_REG,
441cfee7739Sjmcneill CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_VCO_FREQ),
442cfee7739Sjmcneill CLK_PLL("pll_x", "clk_m", CAR_PLLX_BASE_REG,
443cfee7739Sjmcneill CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP),
444cfee7739Sjmcneill CLK_PLL("pll_e", "clk_m", CAR_PLLE_BASE_REG,
445cfee7739Sjmcneill CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML),
446cfee7739Sjmcneill CLK_PLL("pll_d", "clk_m", CAR_PLLD_BASE_REG,
447cfee7739Sjmcneill CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP),
448cfee7739Sjmcneill CLK_PLL("pll_d2", "clk_m", CAR_PLLD2_BASE_REG,
449cfee7739Sjmcneill CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP),
450137a7d5aSjakllsch CLK_PLL("pll_re", "clk_m", CAR_PLLREFE_BASE_REG,
451137a7d5aSjakllsch CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP),
452cfee7739Sjmcneill
453cfee7739Sjmcneill CLK_FIXED_DIV("pll_p_out0", "pll_p", 1),
454cfee7739Sjmcneill CLK_FIXED_DIV("pll_u_480", "pll_u", 1),
455cfee7739Sjmcneill CLK_FIXED_DIV("pll_u_60", "pll_u", 8),
456cfee7739Sjmcneill CLK_FIXED_DIV("pll_u_48", "pll_u", 10),
457cfee7739Sjmcneill CLK_FIXED_DIV("pll_u_12", "pll_u", 40),
458cfee7739Sjmcneill CLK_FIXED_DIV("pll_d_out", "pll_d", 1),
459cfee7739Sjmcneill CLK_FIXED_DIV("pll_d_out0", "pll_d", 2),
460cfee7739Sjmcneill CLK_FIXED_DIV("pll_d2_out0", "pll_d2", 1),
461137a7d5aSjakllsch CLK_FIXED_DIV("pll_re_out", "pll_re", 1),
462cfee7739Sjmcneill
463cfee7739Sjmcneill CLK_MUX("mux_uarta", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC,
464cfee7739Sjmcneill mux_uart_p),
465cfee7739Sjmcneill CLK_MUX("mux_uartb", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC,
466cfee7739Sjmcneill mux_uart_p),
467cfee7739Sjmcneill CLK_MUX("mux_uartc", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC,
468cfee7739Sjmcneill mux_uart_p),
469cfee7739Sjmcneill CLK_MUX("mux_uartd", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC,
470cfee7739Sjmcneill mux_uart_p),
471cfee7739Sjmcneill CLK_MUX("mux_sdmmc1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC,
472cfee7739Sjmcneill mux_sdmmc_p),
473cfee7739Sjmcneill CLK_MUX("mux_sdmmc2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC,
474cfee7739Sjmcneill mux_sdmmc_p),
475cfee7739Sjmcneill CLK_MUX("mux_sdmmc3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC,
476cfee7739Sjmcneill mux_sdmmc_p),
477cfee7739Sjmcneill CLK_MUX("mux_sdmmc4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC,
478cfee7739Sjmcneill mux_sdmmc_p),
479cfee7739Sjmcneill CLK_MUX("mux_i2c1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
480cfee7739Sjmcneill CLK_MUX("mux_i2c2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
481cfee7739Sjmcneill CLK_MUX("mux_i2c3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
482cfee7739Sjmcneill CLK_MUX("mux_i2c4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
483cfee7739Sjmcneill CLK_MUX("mux_i2c5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
484cfee7739Sjmcneill CLK_MUX("mux_i2c6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
4854e889696Sjakllsch CLK_MUX("mux_spi1", CAR_CLKSRC_SPI1_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p),
4864e889696Sjakllsch CLK_MUX("mux_spi2", CAR_CLKSRC_SPI2_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p),
4874e889696Sjakllsch CLK_MUX("mux_spi3", CAR_CLKSRC_SPI3_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p),
4884e889696Sjakllsch CLK_MUX("mux_spi4", CAR_CLKSRC_SPI4_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p),
4894e889696Sjakllsch CLK_MUX("mux_spi5", CAR_CLKSRC_SPI5_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p),
4904e889696Sjakllsch CLK_MUX("mux_spi6", CAR_CLKSRC_SPI6_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p),
491cfee7739Sjmcneill CLK_MUX("mux_sata_oob",
492cfee7739Sjmcneill CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_SRC, mux_sata_p),
493cfee7739Sjmcneill CLK_MUX("mux_sata",
494cfee7739Sjmcneill CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_SRC, mux_sata_p),
495cfee7739Sjmcneill CLK_MUX("mux_hda2codec_2x",
496cfee7739Sjmcneill CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_SRC,
497cfee7739Sjmcneill mux_hda_p),
498cfee7739Sjmcneill CLK_MUX("mux_hda",
499cfee7739Sjmcneill CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_SRC, mux_hda_p),
500cfee7739Sjmcneill CLK_MUX("mux_soc_therm",
501cfee7739Sjmcneill CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_SRC,
502cfee7739Sjmcneill mux_soc_therm_p),
503b44ae13aSjakllsch CLK_MUX("mux_mselect",
504b44ae13aSjakllsch CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_SRC,
505b44ae13aSjakllsch mux_mselect_p),
506cfee7739Sjmcneill CLK_MUX("mux_tsensor",
507cfee7739Sjmcneill CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_SRC,
508cfee7739Sjmcneill mux_tsensor_p),
509cfee7739Sjmcneill CLK_MUX("mux_host1x",
510cfee7739Sjmcneill CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_SRC,
511cfee7739Sjmcneill mux_host1x_p),
512cfee7739Sjmcneill CLK_MUX("mux_disp1",
513cfee7739Sjmcneill CAR_CLKSRC_DISP1_REG, CAR_CLKSRC_DISP_SRC,
514cfee7739Sjmcneill mux_disp_p),
515cfee7739Sjmcneill CLK_MUX("mux_disp2",
516cfee7739Sjmcneill CAR_CLKSRC_DISP2_REG, CAR_CLKSRC_DISP_SRC,
517cfee7739Sjmcneill mux_disp_p),
518cfee7739Sjmcneill CLK_MUX("mux_hdmi",
519cfee7739Sjmcneill CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_SRC,
520cfee7739Sjmcneill mux_hdmi_p),
521137a7d5aSjakllsch CLK_MUX("mux_xusb_host",
522137a7d5aSjakllsch CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC,
523137a7d5aSjakllsch mux_xusb_host_p),
524137a7d5aSjakllsch CLK_MUX("mux_xusb_falcon",
525137a7d5aSjakllsch CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC,
526137a7d5aSjakllsch mux_xusb_host_p),
527137a7d5aSjakllsch CLK_MUX("mux_xusb_ss",
528137a7d5aSjakllsch CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC,
529137a7d5aSjakllsch mux_xusb_ss_p),
530137a7d5aSjakllsch CLK_MUX("mux_xusb_fs",
531137a7d5aSjakllsch CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC,
532137a7d5aSjakllsch mux_xusb_fs_p),
533cfee7739Sjmcneill
534cfee7739Sjmcneill CLK_DIV("div_uarta", "mux_uarta",
535cfee7739Sjmcneill CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV),
536cfee7739Sjmcneill CLK_DIV("div_uartb", "mux_uartb",
537cfee7739Sjmcneill CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV),
538cfee7739Sjmcneill CLK_DIV("div_uartc", "mux_uartc",
539cfee7739Sjmcneill CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV),
540cfee7739Sjmcneill CLK_DIV("div_uartd", "mux_uartd",
541cfee7739Sjmcneill CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV),
542cfee7739Sjmcneill CLK_DIV("div_sdmmc1", "mux_sdmmc1",
543cfee7739Sjmcneill CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV),
544cfee7739Sjmcneill CLK_DIV("div_sdmmc2", "mux_sdmmc2",
545cfee7739Sjmcneill CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV),
546cfee7739Sjmcneill CLK_DIV("div_sdmmc3", "mux_sdmmc3",
547cfee7739Sjmcneill CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV),
548cfee7739Sjmcneill CLK_DIV("div_sdmmc4", "mux_sdmmc4",
549cfee7739Sjmcneill CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV),
550cfee7739Sjmcneill CLK_DIV("div_i2c1", "mux_i2c1",
551cfee7739Sjmcneill CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV),
552cfee7739Sjmcneill CLK_DIV("div_i2c2", "mux_i2c2",
553cfee7739Sjmcneill CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV),
554cfee7739Sjmcneill CLK_DIV("div_i2c3", "mux_i2c3",
555cfee7739Sjmcneill CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV),
556cfee7739Sjmcneill CLK_DIV("div_i2c4", "mux_i2c4",
557cfee7739Sjmcneill CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV),
558cfee7739Sjmcneill CLK_DIV("div_i2c5", "mux_i2c5",
559cfee7739Sjmcneill CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV),
560cfee7739Sjmcneill CLK_DIV("div_i2c6", "mux_i2c6",
561cfee7739Sjmcneill CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV),
5624e889696Sjakllsch CLK_DIV("div_spi1", "mux_spi1",
5634e889696Sjakllsch CAR_CLKSRC_SPI1_REG, CAR_CLKSRC_SPI_DIV),
5644e889696Sjakllsch CLK_DIV("div_spi2", "mux_spi2",
5654e889696Sjakllsch CAR_CLKSRC_SPI2_REG, CAR_CLKSRC_SPI_DIV),
5664e889696Sjakllsch CLK_DIV("div_spi3", "mux_spi3",
5674e889696Sjakllsch CAR_CLKSRC_SPI3_REG, CAR_CLKSRC_SPI_DIV),
5684e889696Sjakllsch CLK_DIV("div_spi4", "mux_spi4",
5694e889696Sjakllsch CAR_CLKSRC_SPI4_REG, CAR_CLKSRC_SPI_DIV),
5704e889696Sjakllsch CLK_DIV("div_spi5", "mux_spi5",
5714e889696Sjakllsch CAR_CLKSRC_SPI5_REG, CAR_CLKSRC_SPI_DIV),
5724e889696Sjakllsch CLK_DIV("div_spi6", "mux_spi6",
5734e889696Sjakllsch CAR_CLKSRC_SPI6_REG, CAR_CLKSRC_SPI_DIV),
574cfee7739Sjmcneill CLK_DIV("div_sata_oob", "mux_sata_oob",
575cfee7739Sjmcneill CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_DIV),
576cfee7739Sjmcneill CLK_DIV("div_sata", "mux_sata",
577cfee7739Sjmcneill CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_DIV),
578cfee7739Sjmcneill CLK_DIV("div_hda2codec_2x", "mux_hda2codec_2x",
579cfee7739Sjmcneill CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_DIV),
580cfee7739Sjmcneill CLK_DIV("div_hda", "mux_hda",
581cfee7739Sjmcneill CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV),
582cfee7739Sjmcneill CLK_DIV("div_soc_therm", "mux_soc_therm",
583cfee7739Sjmcneill CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_DIV),
584b44ae13aSjakllsch CLK_DIV("div_mselect", "mux_mselect",
585b44ae13aSjakllsch CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_DIV),
586cfee7739Sjmcneill CLK_DIV("div_tsensor", "mux_tsensor",
587cfee7739Sjmcneill CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_DIV),
588cfee7739Sjmcneill CLK_DIV("div_host1x", "mux_host1x",
589cfee7739Sjmcneill CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_CLK_DIVISOR),
590cfee7739Sjmcneill CLK_DIV("div_hdmi", "mux_hdmi",
591cfee7739Sjmcneill CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_DIV),
592cfee7739Sjmcneill CLK_DIV("div_pll_p_out5", "pll_p",
593cfee7739Sjmcneill CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_RATIO),
594137a7d5aSjakllsch CLK_DIV("xusb_host_src", "mux_xusb_host",
595137a7d5aSjakllsch CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV),
596137a7d5aSjakllsch CLK_DIV("xusb_ss_src", "mux_xusb_ss",
597137a7d5aSjakllsch CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV),
598137a7d5aSjakllsch CLK_DIV("xusb_fs_src", "mux_xusb_fs",
599137a7d5aSjakllsch CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV),
600137a7d5aSjakllsch CLK_DIV("xusb_falcon_src", "mux_xusb_falcon",
601137a7d5aSjakllsch CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV),
602cfee7739Sjmcneill
603cfee7739Sjmcneill CLK_GATE_L("uarta", "div_uarta", CAR_DEV_L_UARTA),
604cfee7739Sjmcneill CLK_GATE_L("uartb", "div_uartb", CAR_DEV_L_UARTB),
605cfee7739Sjmcneill CLK_GATE_H("uartc", "div_uartc", CAR_DEV_H_UARTC),
606cfee7739Sjmcneill CLK_GATE_U("uartd", "div_uartd", CAR_DEV_U_UARTD),
607cfee7739Sjmcneill CLK_GATE_L("sdmmc1", "div_sdmmc1", CAR_DEV_L_SDMMC1),
608cfee7739Sjmcneill CLK_GATE_L("sdmmc2", "div_sdmmc2", CAR_DEV_L_SDMMC2),
609cfee7739Sjmcneill CLK_GATE_U("sdmmc3", "div_sdmmc3", CAR_DEV_U_SDMMC3),
610cfee7739Sjmcneill CLK_GATE_L("sdmmc4", "div_sdmmc4", CAR_DEV_L_SDMMC4),
611cfee7739Sjmcneill CLK_GATE_L("i2c1", "div_i2c1", CAR_DEV_L_I2C1),
612cfee7739Sjmcneill CLK_GATE_H("i2c2", "div_i2c2", CAR_DEV_H_I2C2),
613cfee7739Sjmcneill CLK_GATE_U("i2c3", "div_i2c3", CAR_DEV_U_I2C3),
614cfee7739Sjmcneill CLK_GATE_V("i2c4", "div_i2c4", CAR_DEV_V_I2C4),
615cfee7739Sjmcneill CLK_GATE_H("i2c5", "div_i2c5", CAR_DEV_H_I2C5),
616cfee7739Sjmcneill CLK_GATE_X("i2c6", "div_i2c6", CAR_DEV_X_I2C6),
6174e889696Sjakllsch CLK_GATE_H("spi1", "div_spi1", CAR_DEV_H_SPI1),
6184e889696Sjakllsch CLK_GATE_H("spi2", "div_spi2", CAR_DEV_H_SPI2),
6194e889696Sjakllsch CLK_GATE_H("spi3", "div_spi3", CAR_DEV_H_SPI3),
6204e889696Sjakllsch CLK_GATE_U("spi4", "div_spi4", CAR_DEV_U_SPI4),
6214e889696Sjakllsch CLK_GATE_V("spi5", "div_spi5", CAR_DEV_V_SPI5),
6224e889696Sjakllsch CLK_GATE_V("spi6", "div_spi6", CAR_DEV_V_SPI6),
623cfee7739Sjmcneill CLK_GATE_L("usbd", "pll_u_480", CAR_DEV_L_USBD),
624cfee7739Sjmcneill CLK_GATE_H("usb2", "pll_u_480", CAR_DEV_H_USB2),
625cfee7739Sjmcneill CLK_GATE_H("usb3", "pll_u_480", CAR_DEV_H_USB3),
626cfee7739Sjmcneill CLK_GATE_V("sata_oob", "div_sata_oob", CAR_DEV_V_SATA_OOB),
627cfee7739Sjmcneill CLK_GATE_V("sata", "div_sata", CAR_DEV_V_SATA),
628cfee7739Sjmcneill CLK_GATE_SIMPLE("cml0", "pll_e",
629cfee7739Sjmcneill CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN),
630cfee7739Sjmcneill CLK_GATE_SIMPLE("cml1", "pll_e",
631cfee7739Sjmcneill CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN),
632cfee7739Sjmcneill CLK_GATE_V("hda2codec_2x", "div_hda2codec_2x", CAR_DEV_V_HDA2CODEC_2X),
633cfee7739Sjmcneill CLK_GATE_V("hda", "div_hda", CAR_DEV_V_HDA),
634cfee7739Sjmcneill CLK_GATE_W("hda2hdmi", "clk_m", CAR_DEV_W_HDA2HDMICODEC),
6359ad6de64Sjmcneill CLK_GATE_W("cec", "clk_m", CAR_DEV_W_CEC),
636cfee7739Sjmcneill CLK_GATE_H("fuse", "clk_m", CAR_DEV_H_FUSE),
637cfee7739Sjmcneill CLK_GATE_U("soc_therm", "div_soc_therm", CAR_DEV_U_SOC_THERM),
638b44ae13aSjakllsch CLK_GATE_V("mselect", "div_mselect", CAR_DEV_V_MSELECT),
639cfee7739Sjmcneill CLK_GATE_V("tsensor", "div_tsensor", CAR_DEV_V_TSENSOR),
640cfee7739Sjmcneill CLK_GATE_L("host1x", "div_host1x", CAR_DEV_L_HOST1X),
641cfee7739Sjmcneill CLK_GATE_L("disp1", "mux_disp1", CAR_DEV_L_DISP1),
642cfee7739Sjmcneill CLK_GATE_L("disp2", "mux_disp2", CAR_DEV_L_DISP2),
643cfee7739Sjmcneill CLK_GATE_H("hdmi", "div_hdmi", CAR_DEV_H_HDMI),
644405d9ce8Sjakllsch CLK_GATE_SIMPLE("pll_p_out5", "div_pll_p_out5",
645cfee7739Sjmcneill CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_CLKEN),
646137a7d5aSjakllsch CLK_GATE_U("xusb_host", "xusb_host_src", CAR_DEV_U_XUSB_HOST),
647137a7d5aSjakllsch CLK_GATE_W("xusb_ss", "xusb_ss_src", CAR_DEV_W_XUSB_SS),
648dc19b2baSjmcneill CLK_GATE_X("gpu", "pll_ref", CAR_DEV_X_GPU),
64908fcf657Sjmcneill CLK_GATE_H("apbdma", "clk_m", CAR_DEV_H_APBDMA),
650b44ae13aSjakllsch CLK_GATE_U("pcie", "mselect", CAR_DEV_U_PCIE),
651b44ae13aSjakllsch CLK_GATE_U("afi", "mselect", CAR_DEV_U_AFI),
652cfee7739Sjmcneill };
653cfee7739Sjmcneill
654579ba339Sjmcneill struct tegra124_init_parent {
655579ba339Sjmcneill const char *clock;
656579ba339Sjmcneill const char *parent;
657579ba339Sjmcneill } tegra124_init_parents[] = {
658579ba339Sjmcneill { "sata_oob", "pll_p_out0" },
659579ba339Sjmcneill { "sata", "pll_p_out0" },
660579ba339Sjmcneill { "hda", "pll_p_out0" },
661579ba339Sjmcneill { "hda2codec_2x", "pll_p_out0" },
662579ba339Sjmcneill { "soc_therm", "pll_p_out0" },
663579ba339Sjmcneill { "tsensor", "clk_m" },
664579ba339Sjmcneill { "xusb_host_src", "pll_p_out0" },
665579ba339Sjmcneill { "xusb_falcon_src", "pll_p_out0" },
666579ba339Sjmcneill { "xusb_ss_src", "pll_u_480" },
667579ba339Sjmcneill { "xusb_fs_src", "pll_u_48" },
66864dce7b7Sjmcneill { "host1x", "pll_p_out0" },
669579ba339Sjmcneill };
670579ba339Sjmcneill
671cfee7739Sjmcneill struct tegra124_car_rst {
672cfee7739Sjmcneill u_int set_reg;
673cfee7739Sjmcneill u_int clr_reg;
674cfee7739Sjmcneill u_int mask;
675cfee7739Sjmcneill };
676cfee7739Sjmcneill
677cfee7739Sjmcneill static struct tegra124_car_reset_reg {
678cfee7739Sjmcneill u_int set_reg;
679cfee7739Sjmcneill u_int clr_reg;
680cfee7739Sjmcneill } tegra124_car_reset_regs[] = {
681cfee7739Sjmcneill { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG },
682cfee7739Sjmcneill { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG },
683cfee7739Sjmcneill { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG },
684cfee7739Sjmcneill { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG },
685cfee7739Sjmcneill { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG },
686cfee7739Sjmcneill { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG },
687cfee7739Sjmcneill };
688cfee7739Sjmcneill
689cfee7739Sjmcneill static void * tegra124_car_reset_acquire(device_t, const void *, size_t);
690cfee7739Sjmcneill static void tegra124_car_reset_release(device_t, void *);
691cfee7739Sjmcneill static int tegra124_car_reset_assert(device_t, void *);
692cfee7739Sjmcneill static int tegra124_car_reset_deassert(device_t, void *);
693cfee7739Sjmcneill
694cfee7739Sjmcneill static const struct fdtbus_reset_controller_func tegra124_car_fdtreset_funcs = {
695cfee7739Sjmcneill .acquire = tegra124_car_reset_acquire,
696cfee7739Sjmcneill .release = tegra124_car_reset_release,
697cfee7739Sjmcneill .reset_assert = tegra124_car_reset_assert,
698cfee7739Sjmcneill .reset_deassert = tegra124_car_reset_deassert,
699cfee7739Sjmcneill };
700cfee7739Sjmcneill
701cfee7739Sjmcneill struct tegra124_car_softc {
702cfee7739Sjmcneill device_t sc_dev;
703cfee7739Sjmcneill bus_space_tag_t sc_bst;
704cfee7739Sjmcneill bus_space_handle_t sc_bsh;
705cfee7739Sjmcneill
706579ba339Sjmcneill struct clk_domain sc_clkdom;
707579ba339Sjmcneill
708cfee7739Sjmcneill u_int sc_clock_cells;
709cfee7739Sjmcneill u_int sc_reset_cells;
710cfee7739Sjmcneill
711cfee7739Sjmcneill krndsource_t sc_rndsource;
712cfee7739Sjmcneill };
713cfee7739Sjmcneill
714cfee7739Sjmcneill static void tegra124_car_init(struct tegra124_car_softc *);
715cfee7739Sjmcneill static void tegra124_car_utmip_init(struct tegra124_car_softc *);
716137a7d5aSjakllsch static void tegra124_car_xusb_init(struct tegra124_car_softc *);
717579ba339Sjmcneill static void tegra124_car_watchdog_init(struct tegra124_car_softc *);
718579ba339Sjmcneill static void tegra124_car_parent_init(struct tegra124_car_softc *);
719cfee7739Sjmcneill
720cfee7739Sjmcneill static void tegra124_car_rnd_attach(device_t);
721cfee7739Sjmcneill static void tegra124_car_rnd_callback(size_t, void *);
722cfee7739Sjmcneill
723cfee7739Sjmcneill CFATTACH_DECL_NEW(tegra124_car, sizeof(struct tegra124_car_softc),
724cfee7739Sjmcneill tegra124_car_match, tegra124_car_attach, NULL, NULL);
725cfee7739Sjmcneill
7268e90f9edSthorpej static const struct device_compatible_entry compat_data[] = {
7278e90f9edSthorpej { .compat = "nvidia,tegra124-car" },
7288e90f9edSthorpej DEVICE_COMPAT_EOL
7298e90f9edSthorpej };
7308e90f9edSthorpej
731cfee7739Sjmcneill static int
tegra124_car_match(device_t parent,cfdata_t cf,void * aux)732cfee7739Sjmcneill tegra124_car_match(device_t parent, cfdata_t cf, void *aux)
733cfee7739Sjmcneill {
734cfee7739Sjmcneill struct fdt_attach_args * const faa = aux;
735cfee7739Sjmcneill
736cfee7739Sjmcneill #if 0
7378e90f9edSthorpej return of_compatible_match(faa->faa_phandle, compat_data);
738cfee7739Sjmcneill #else
7398e90f9edSthorpej return of_compatible_match(faa->faa_phandle, compat_data) ? 999 : 0;
740cfee7739Sjmcneill #endif
741cfee7739Sjmcneill }
742cfee7739Sjmcneill
743cfee7739Sjmcneill static void
tegra124_car_attach(device_t parent,device_t self,void * aux)744cfee7739Sjmcneill tegra124_car_attach(device_t parent, device_t self, void *aux)
745cfee7739Sjmcneill {
746cfee7739Sjmcneill struct tegra124_car_softc * const sc = device_private(self);
747cfee7739Sjmcneill struct fdt_attach_args * const faa = aux;
748cfee7739Sjmcneill const int phandle = faa->faa_phandle;
749cfee7739Sjmcneill bus_addr_t addr;
750cfee7739Sjmcneill bus_size_t size;
751579ba339Sjmcneill int error, n;
752cfee7739Sjmcneill
753cfee7739Sjmcneill if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
754cfee7739Sjmcneill aprint_error(": couldn't get registers\n");
755cfee7739Sjmcneill return;
756cfee7739Sjmcneill }
757cfee7739Sjmcneill
758cfee7739Sjmcneill sc->sc_dev = self;
759cfee7739Sjmcneill sc->sc_bst = faa->faa_bst;
760cfee7739Sjmcneill error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
761cfee7739Sjmcneill if (error) {
762b2c5aa90Sskrll aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
763cfee7739Sjmcneill return;
764cfee7739Sjmcneill }
765cfee7739Sjmcneill if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells))
766cfee7739Sjmcneill sc->sc_clock_cells = 1;
767cfee7739Sjmcneill if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells))
768cfee7739Sjmcneill sc->sc_reset_cells = 1;
769cfee7739Sjmcneill
770cfee7739Sjmcneill aprint_naive("\n");
771cfee7739Sjmcneill aprint_normal(": CAR\n");
772cfee7739Sjmcneill
77327f90052Sjmcneill sc->sc_clkdom.name = device_xname(self);
774579ba339Sjmcneill sc->sc_clkdom.funcs = &tegra124_car_clock_funcs;
775579ba339Sjmcneill sc->sc_clkdom.priv = sc;
77627f90052Sjmcneill for (n = 0; n < __arraycount(tegra124_car_clocks); n++) {
777579ba339Sjmcneill tegra124_car_clocks[n].base.domain = &sc->sc_clkdom;
77827f90052Sjmcneill clk_attach(&tegra124_car_clocks[n].base);
77927f90052Sjmcneill }
780cfee7739Sjmcneill
781cfee7739Sjmcneill fdtbus_register_clock_controller(self, phandle,
782cfee7739Sjmcneill &tegra124_car_fdtclock_funcs);
783cfee7739Sjmcneill fdtbus_register_reset_controller(self, phandle,
784cfee7739Sjmcneill &tegra124_car_fdtreset_funcs);
785cfee7739Sjmcneill
786cfee7739Sjmcneill tegra124_car_init(sc);
787cfee7739Sjmcneill
788*799005bcSriastradh tegra124_car_rnd_attach(self);
789cfee7739Sjmcneill }
790cfee7739Sjmcneill
791cfee7739Sjmcneill static void
tegra124_car_init(struct tegra124_car_softc * sc)792cfee7739Sjmcneill tegra124_car_init(struct tegra124_car_softc *sc)
793cfee7739Sjmcneill {
794579ba339Sjmcneill tegra124_car_parent_init(sc);
795cfee7739Sjmcneill tegra124_car_utmip_init(sc);
796137a7d5aSjakllsch tegra124_car_xusb_init(sc);
797579ba339Sjmcneill tegra124_car_watchdog_init(sc);
798579ba339Sjmcneill }
799579ba339Sjmcneill
800579ba339Sjmcneill static void
tegra124_car_parent_init(struct tegra124_car_softc * sc)801579ba339Sjmcneill tegra124_car_parent_init(struct tegra124_car_softc *sc)
802579ba339Sjmcneill {
803579ba339Sjmcneill struct clk *clk, *clk_parent;
804579ba339Sjmcneill int error;
805579ba339Sjmcneill u_int n;
806579ba339Sjmcneill
807579ba339Sjmcneill for (n = 0; n < __arraycount(tegra124_init_parents); n++) {
808579ba339Sjmcneill clk = clk_get(&sc->sc_clkdom, tegra124_init_parents[n].clock);
809579ba339Sjmcneill KASSERT(clk != NULL);
810579ba339Sjmcneill clk_parent = clk_get(&sc->sc_clkdom,
811579ba339Sjmcneill tegra124_init_parents[n].parent);
812579ba339Sjmcneill KASSERT(clk_parent != NULL);
813579ba339Sjmcneill
814579ba339Sjmcneill error = clk_set_parent(clk, clk_parent);
815579ba339Sjmcneill if (error) {
816579ba339Sjmcneill aprint_error_dev(sc->sc_dev,
817579ba339Sjmcneill "couldn't set '%s' parent to '%s': %d\n",
818579ba339Sjmcneill clk->name, clk_parent->name, error);
819579ba339Sjmcneill }
820579ba339Sjmcneill clk_put(clk_parent);
821579ba339Sjmcneill clk_put(clk);
822579ba339Sjmcneill }
823cfee7739Sjmcneill }
824cfee7739Sjmcneill
825cfee7739Sjmcneill static void
tegra124_car_utmip_init(struct tegra124_car_softc * sc)826cfee7739Sjmcneill tegra124_car_utmip_init(struct tegra124_car_softc *sc)
827cfee7739Sjmcneill {
828cfee7739Sjmcneill bus_space_tag_t bst = sc->sc_bst;
829cfee7739Sjmcneill bus_space_handle_t bsh = sc->sc_bsh;
830cfee7739Sjmcneill
831cfee7739Sjmcneill const u_int enable_dly_count = 0x02;
832cfee7739Sjmcneill const u_int stable_count = 0x2f;
833cfee7739Sjmcneill const u_int active_dly_count = 0x04;
834cfee7739Sjmcneill const u_int xtal_freq_count = 0x76;
835cfee7739Sjmcneill
836cfee7739Sjmcneill tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG,
837cfee7739Sjmcneill __SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) |
838cfee7739Sjmcneill __SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT),
839cfee7739Sjmcneill CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN |
840cfee7739Sjmcneill CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN |
841cfee7739Sjmcneill CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN |
842cfee7739Sjmcneill CAR_UTMIP_PLL_CFG2_STABLE_COUNT |
843cfee7739Sjmcneill CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT);
844cfee7739Sjmcneill
845cfee7739Sjmcneill tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
846cfee7739Sjmcneill __SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) |
847cfee7739Sjmcneill __SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT),
848cfee7739Sjmcneill CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT |
849cfee7739Sjmcneill CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT);
850cfee7739Sjmcneill
851cfee7739Sjmcneill tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
852cfee7739Sjmcneill 0,
853cfee7739Sjmcneill CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN |
854cfee7739Sjmcneill CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN);
855cfee7739Sjmcneill
856cfee7739Sjmcneill }
857cfee7739Sjmcneill
858cfee7739Sjmcneill static void
tegra124_car_xusb_init(struct tegra124_car_softc * sc)859137a7d5aSjakllsch tegra124_car_xusb_init(struct tegra124_car_softc *sc)
860137a7d5aSjakllsch {
861137a7d5aSjakllsch const bus_space_tag_t bst = sc->sc_bst;
862137a7d5aSjakllsch const bus_space_handle_t bsh = sc->sc_bsh;
863137a7d5aSjakllsch uint32_t val;
864137a7d5aSjakllsch
865137a7d5aSjakllsch /* XXX do this all better */
866137a7d5aSjakllsch
867137a7d5aSjakllsch bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB);
868137a7d5aSjakllsch
869137a7d5aSjakllsch tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG,
870137a7d5aSjakllsch 0, CAR_PLLREFE_MISC_IDDQ);
871137a7d5aSjakllsch val = __SHIFTIN(25, CAR_PLLREFE_BASE_DIVN) |
872137a7d5aSjakllsch __SHIFTIN(1, CAR_PLLREFE_BASE_DIVM);
873137a7d5aSjakllsch bus_space_write_4(bst, bsh, CAR_PLLREFE_BASE_REG, val);
874137a7d5aSjakllsch
875137a7d5aSjakllsch tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG,
876137a7d5aSjakllsch 0, CAR_PLLREFE_MISC_LOCK_OVERRIDE);
877137a7d5aSjakllsch tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG,
878137a7d5aSjakllsch CAR_PLLREFE_BASE_ENABLE, 0);
879137a7d5aSjakllsch tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG,
880137a7d5aSjakllsch CAR_PLLREFE_MISC_LOCK_ENABLE, 0);
881137a7d5aSjakllsch
882137a7d5aSjakllsch do {
883137a7d5aSjakllsch delay(2);
884137a7d5aSjakllsch val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG);
885137a7d5aSjakllsch } while ((val & CAR_PLLREFE_MISC_LOCK) == 0);
886137a7d5aSjakllsch
887137a7d5aSjakllsch tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG,
888137a7d5aSjakllsch CAR_PLLE_MISC_IDDQ_SWCTL, CAR_PLLE_MISC_IDDQ_OVERRIDE);
889137a7d5aSjakllsch tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG,
890137a7d5aSjakllsch CAR_PLLE_BASE_ENABLE, 0);
891137a7d5aSjakllsch tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG,
892137a7d5aSjakllsch CAR_PLLE_MISC_LOCK_ENABLE, 0);
893137a7d5aSjakllsch
894137a7d5aSjakllsch do {
895137a7d5aSjakllsch delay(2);
896137a7d5aSjakllsch val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG);
897137a7d5aSjakllsch } while ((val & CAR_PLLE_MISC_LOCK) == 0);
898137a7d5aSjakllsch
899137a7d5aSjakllsch tegra_reg_set_clear(bst, bsh, CAR_CLKSRC_XUSB_SS_REG,
900137a7d5aSjakllsch CAR_CLKSRC_XUSB_SS_HS_CLK_BYPASS, 0);
901137a7d5aSjakllsch }
902137a7d5aSjakllsch
903137a7d5aSjakllsch static void
tegra124_car_watchdog_init(struct tegra124_car_softc * sc)904579ba339Sjmcneill tegra124_car_watchdog_init(struct tegra124_car_softc *sc)
905579ba339Sjmcneill {
906579ba339Sjmcneill const bus_space_tag_t bst = sc->sc_bst;
907579ba339Sjmcneill const bus_space_handle_t bsh = sc->sc_bsh;
908579ba339Sjmcneill
909579ba339Sjmcneill /* Enable watchdog timer reset for system */
910579ba339Sjmcneill tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG,
911579ba339Sjmcneill CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0);
912579ba339Sjmcneill }
913579ba339Sjmcneill
914579ba339Sjmcneill static void
tegra124_car_rnd_attach(device_t self)915cfee7739Sjmcneill tegra124_car_rnd_attach(device_t self)
916cfee7739Sjmcneill {
917cfee7739Sjmcneill struct tegra124_car_softc * const sc = device_private(self);
918cfee7739Sjmcneill
919cfee7739Sjmcneill rndsource_setcb(&sc->sc_rndsource, tegra124_car_rnd_callback, sc);
920cfee7739Sjmcneill rnd_attach_source(&sc->sc_rndsource, device_xname(sc->sc_dev),
921cfee7739Sjmcneill RND_TYPE_RNG, RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB);
922cfee7739Sjmcneill }
923cfee7739Sjmcneill
924cfee7739Sjmcneill static void
tegra124_car_rnd_callback(size_t bytes_wanted,void * priv)925cfee7739Sjmcneill tegra124_car_rnd_callback(size_t bytes_wanted, void *priv)
926cfee7739Sjmcneill {
927cfee7739Sjmcneill struct tegra124_car_softc * const sc = priv;
928c97056b4Sriastradh uint16_t buf[512];
929c97056b4Sriastradh uint32_t cnt;
930cfee7739Sjmcneill
931c97056b4Sriastradh while (bytes_wanted) {
932c97056b4Sriastradh const u_int nbytes = MIN(bytes_wanted, 1024);
933c97056b4Sriastradh for (cnt = 0; cnt < bytes_wanted / 2; cnt++) {
934c97056b4Sriastradh buf[cnt] = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
935c97056b4Sriastradh CAR_PLL_LFSR_REG) & 0xffff;
936cfee7739Sjmcneill }
937c97056b4Sriastradh rnd_add_data_sync(&sc->sc_rndsource, buf, nbytes,
938c97056b4Sriastradh nbytes * NBBY);
939c97056b4Sriastradh bytes_wanted -= MIN(bytes_wanted, nbytes);
940cfee7739Sjmcneill }
941c97056b4Sriastradh explicit_memset(buf, 0, sizeof(buf));
942cfee7739Sjmcneill }
943cfee7739Sjmcneill
944cfee7739Sjmcneill static struct tegra_clk *
tegra124_car_clock_find(const char * name)945cfee7739Sjmcneill tegra124_car_clock_find(const char *name)
946cfee7739Sjmcneill {
947cfee7739Sjmcneill u_int n;
948cfee7739Sjmcneill
949cfee7739Sjmcneill for (n = 0; n < __arraycount(tegra124_car_clocks); n++) {
950cfee7739Sjmcneill if (strcmp(tegra124_car_clocks[n].base.name, name) == 0) {
951cfee7739Sjmcneill return &tegra124_car_clocks[n];
952cfee7739Sjmcneill }
953cfee7739Sjmcneill }
954cfee7739Sjmcneill
955cfee7739Sjmcneill return NULL;
956cfee7739Sjmcneill }
957cfee7739Sjmcneill
958cfee7739Sjmcneill static struct tegra_clk *
tegra124_car_clock_find_by_id(u_int clock_id)959cfee7739Sjmcneill tegra124_car_clock_find_by_id(u_int clock_id)
960cfee7739Sjmcneill {
961cfee7739Sjmcneill u_int n;
962cfee7739Sjmcneill
963cfee7739Sjmcneill for (n = 0; n < __arraycount(tegra124_car_clock_ids); n++) {
964cfee7739Sjmcneill if (tegra124_car_clock_ids[n].id == clock_id) {
965cfee7739Sjmcneill const char *name = tegra124_car_clock_ids[n].name;
966cfee7739Sjmcneill return tegra124_car_clock_find(name);
967cfee7739Sjmcneill }
968cfee7739Sjmcneill }
969cfee7739Sjmcneill
970cfee7739Sjmcneill return NULL;
971cfee7739Sjmcneill }
972cfee7739Sjmcneill
973cfee7739Sjmcneill static struct clk *
tegra124_car_clock_decode(device_t dev,int cc_phandle,const void * data,size_t len)974cdeb425bSaymeric tegra124_car_clock_decode(device_t dev, int cc_phandle, const void *data,
975cdeb425bSaymeric size_t len)
976cfee7739Sjmcneill {
977cfee7739Sjmcneill struct tegra124_car_softc * const sc = device_private(dev);
978cfee7739Sjmcneill struct tegra_clk *tclk;
979cfee7739Sjmcneill
980cfee7739Sjmcneill if (len != sc->sc_clock_cells * 4) {
981cfee7739Sjmcneill return NULL;
982cfee7739Sjmcneill }
983cfee7739Sjmcneill
984cfee7739Sjmcneill const u_int clock_id = be32dec(data);
985cfee7739Sjmcneill
986cfee7739Sjmcneill tclk = tegra124_car_clock_find_by_id(clock_id);
987cfee7739Sjmcneill if (tclk)
988cfee7739Sjmcneill return TEGRA_CLK_BASE(tclk);
989cfee7739Sjmcneill
990cfee7739Sjmcneill return NULL;
991cfee7739Sjmcneill }
992cfee7739Sjmcneill
993cfee7739Sjmcneill static struct clk *
tegra124_car_clock_get(void * priv,const char * name)994cfee7739Sjmcneill tegra124_car_clock_get(void *priv, const char *name)
995cfee7739Sjmcneill {
996cfee7739Sjmcneill struct tegra_clk *tclk;
997cfee7739Sjmcneill
998cfee7739Sjmcneill tclk = tegra124_car_clock_find(name);
999cfee7739Sjmcneill if (tclk == NULL)
1000cfee7739Sjmcneill return NULL;
1001cfee7739Sjmcneill
1002cfee7739Sjmcneill atomic_inc_uint(&tclk->refcnt);
1003cfee7739Sjmcneill
1004cfee7739Sjmcneill return TEGRA_CLK_BASE(tclk);
1005cfee7739Sjmcneill }
1006cfee7739Sjmcneill
1007cfee7739Sjmcneill static void
tegra124_car_clock_put(void * priv,struct clk * clk)1008cfee7739Sjmcneill tegra124_car_clock_put(void *priv, struct clk *clk)
1009cfee7739Sjmcneill {
1010cfee7739Sjmcneill struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1011cfee7739Sjmcneill
1012cfee7739Sjmcneill KASSERT(tclk->refcnt > 0);
1013cfee7739Sjmcneill
1014cfee7739Sjmcneill atomic_dec_uint(&tclk->refcnt);
1015cfee7739Sjmcneill }
1016cfee7739Sjmcneill
1017cfee7739Sjmcneill static u_int
tegra124_car_clock_get_rate_pll(struct tegra124_car_softc * sc,struct tegra_clk * tclk)1018cfee7739Sjmcneill tegra124_car_clock_get_rate_pll(struct tegra124_car_softc *sc,
1019cfee7739Sjmcneill struct tegra_clk *tclk)
1020cfee7739Sjmcneill {
1021cfee7739Sjmcneill struct tegra_pll_clk *tpll = &tclk->u.pll;
1022cfee7739Sjmcneill struct tegra_clk *tclk_parent;
1023cfee7739Sjmcneill bus_space_tag_t bst = sc->sc_bst;
1024cfee7739Sjmcneill bus_space_handle_t bsh = sc->sc_bsh;
1025cfee7739Sjmcneill u_int divm, divn, divp;
1026cfee7739Sjmcneill uint64_t rate;
1027cfee7739Sjmcneill
1028cfee7739Sjmcneill KASSERT(tclk->type == TEGRA_CLK_PLL);
1029cfee7739Sjmcneill
1030cfee7739Sjmcneill tclk_parent = tegra124_car_clock_find(tclk->parent);
1031cfee7739Sjmcneill KASSERT(tclk_parent != NULL);
1032cfee7739Sjmcneill
1033cfee7739Sjmcneill const u_int rate_parent = tegra124_car_clock_get_rate(sc,
1034cfee7739Sjmcneill TEGRA_CLK_BASE(tclk_parent));
1035cfee7739Sjmcneill
1036cfee7739Sjmcneill const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg);
1037cfee7739Sjmcneill divm = __SHIFTOUT(base, tpll->divm_mask);
1038cfee7739Sjmcneill divn = __SHIFTOUT(base, tpll->divn_mask);
1039cfee7739Sjmcneill if (tpll->base_reg == CAR_PLLU_BASE_REG) {
1040cfee7739Sjmcneill divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1;
1041cfee7739Sjmcneill } else {
1042cfee7739Sjmcneill divp = __SHIFTOUT(base, tpll->divp_mask);
1043cfee7739Sjmcneill }
1044cfee7739Sjmcneill
1045cfee7739Sjmcneill rate = (uint64_t)rate_parent * divn;
1046cfee7739Sjmcneill return rate / (divm << divp);
1047cfee7739Sjmcneill }
1048cfee7739Sjmcneill
1049cfee7739Sjmcneill static int
tegra124_car_clock_set_rate_pll(struct tegra124_car_softc * sc,struct tegra_clk * tclk,u_int rate)1050cfee7739Sjmcneill tegra124_car_clock_set_rate_pll(struct tegra124_car_softc *sc,
1051cfee7739Sjmcneill struct tegra_clk *tclk, u_int rate)
1052cfee7739Sjmcneill {
1053cfee7739Sjmcneill struct tegra_pll_clk *tpll = &tclk->u.pll;
1054cfee7739Sjmcneill bus_space_tag_t bst = sc->sc_bst;
1055cfee7739Sjmcneill bus_space_handle_t bsh = sc->sc_bsh;
1056cfee7739Sjmcneill struct clk *clk_parent;
1057cfee7739Sjmcneill uint32_t bp, base;
1058cfee7739Sjmcneill
1059cfee7739Sjmcneill clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1060cfee7739Sjmcneill if (clk_parent == NULL)
1061cfee7739Sjmcneill return EIO;
1062cfee7739Sjmcneill const u_int rate_parent = tegra124_car_clock_get_rate(sc, clk_parent);
1063cfee7739Sjmcneill if (rate_parent == 0)
1064cfee7739Sjmcneill return EIO;
1065cfee7739Sjmcneill
1066cfee7739Sjmcneill if (tpll->base_reg == CAR_PLLX_BASE_REG) {
1067cfee7739Sjmcneill const u_int divm = 1;
1068cfee7739Sjmcneill const u_int divn = rate / rate_parent;
1069cfee7739Sjmcneill const u_int divp = 0;
1070cfee7739Sjmcneill
1071cfee7739Sjmcneill bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG);
1072cfee7739Sjmcneill bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE;
1073cfee7739Sjmcneill bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE,
1074cfee7739Sjmcneill CAR_CCLKG_BURST_POLICY_CPU_STATE);
1075cfee7739Sjmcneill bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE;
1076cfee7739Sjmcneill bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM,
1077cfee7739Sjmcneill CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE);
1078cfee7739Sjmcneill bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp);
1079cfee7739Sjmcneill
1080cfee7739Sjmcneill base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG);
1081cfee7739Sjmcneill base &= ~CAR_PLLX_BASE_DIVM;
1082cfee7739Sjmcneill base &= ~CAR_PLLX_BASE_DIVN;
1083cfee7739Sjmcneill base &= ~CAR_PLLX_BASE_DIVP;
1084cfee7739Sjmcneill base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM);
1085cfee7739Sjmcneill base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN);
1086cfee7739Sjmcneill base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP);
1087cfee7739Sjmcneill bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base);
1088cfee7739Sjmcneill
1089cfee7739Sjmcneill tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG,
1090cfee7739Sjmcneill CAR_PLLX_MISC_LOCK_ENABLE, 0);
1091cfee7739Sjmcneill do {
1092cfee7739Sjmcneill delay(2);
1093cfee7739Sjmcneill base = bus_space_read_4(bst, bsh, tpll->base_reg);
1094cfee7739Sjmcneill } while ((base & CAR_PLLX_BASE_LOCK) == 0);
1095cfee7739Sjmcneill delay(100);
1096cfee7739Sjmcneill
1097cfee7739Sjmcneill bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE;
1098cfee7739Sjmcneill bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN,
1099cfee7739Sjmcneill CAR_CCLKG_BURST_POLICY_CPU_STATE);
1100cfee7739Sjmcneill bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE;
1101cfee7739Sjmcneill bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ,
1102cfee7739Sjmcneill CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE);
1103cfee7739Sjmcneill bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp);
1104cfee7739Sjmcneill
1105cfee7739Sjmcneill return 0;
1106cfee7739Sjmcneill } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) {
1107cfee7739Sjmcneill const u_int divm = 1;
1108cfee7739Sjmcneill const u_int pldiv = 1;
1109cfee7739Sjmcneill const u_int divn = (rate << pldiv) / rate_parent;
1110cfee7739Sjmcneill
1111cfee7739Sjmcneill /* Set frequency */
1112cfee7739Sjmcneill tegra_reg_set_clear(bst, bsh, tpll->base_reg,
1113cfee7739Sjmcneill __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) |
1114cfee7739Sjmcneill __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) |
1115cfee7739Sjmcneill __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP),
1116cfee7739Sjmcneill CAR_PLLD2_BASE_REF_SRC_SEL |
1117cfee7739Sjmcneill CAR_PLLD2_BASE_DIVM |
1118cfee7739Sjmcneill CAR_PLLD2_BASE_DIVN |
1119cfee7739Sjmcneill CAR_PLLD2_BASE_DIVP);
1120cfee7739Sjmcneill
1121cfee7739Sjmcneill return 0;
1122cfee7739Sjmcneill } else {
1123cfee7739Sjmcneill /* TODO */
1124cfee7739Sjmcneill return EOPNOTSUPP;
1125cfee7739Sjmcneill }
1126cfee7739Sjmcneill }
1127cfee7739Sjmcneill
1128cfee7739Sjmcneill static int
tegra124_car_clock_set_parent_mux(struct tegra124_car_softc * sc,struct tegra_clk * tclk,struct tegra_clk * tclk_parent)1129cfee7739Sjmcneill tegra124_car_clock_set_parent_mux(struct tegra124_car_softc *sc,
1130cfee7739Sjmcneill struct tegra_clk *tclk, struct tegra_clk *tclk_parent)
1131cfee7739Sjmcneill {
1132cfee7739Sjmcneill struct tegra_mux_clk *tmux = &tclk->u.mux;
1133cfee7739Sjmcneill bus_space_tag_t bst = sc->sc_bst;
1134cfee7739Sjmcneill bus_space_handle_t bsh = sc->sc_bsh;
1135cfee7739Sjmcneill uint32_t v;
1136cfee7739Sjmcneill u_int src;
1137cfee7739Sjmcneill
1138cfee7739Sjmcneill KASSERT(tclk->type == TEGRA_CLK_MUX);
1139cfee7739Sjmcneill
1140cfee7739Sjmcneill for (src = 0; src < tmux->nparents; src++) {
1141cfee7739Sjmcneill if (tmux->parents[src] == NULL) {
1142cfee7739Sjmcneill continue;
1143cfee7739Sjmcneill }
1144cfee7739Sjmcneill if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) {
1145cfee7739Sjmcneill break;
1146cfee7739Sjmcneill }
1147cfee7739Sjmcneill }
1148cfee7739Sjmcneill if (src == tmux->nparents) {
1149cfee7739Sjmcneill return EINVAL;
1150cfee7739Sjmcneill }
1151cfee7739Sjmcneill
1152cfee7739Sjmcneill if (tmux->reg == CAR_CLKSRC_HDMI_REG &&
1153cfee7739Sjmcneill src == CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0) {
1154cfee7739Sjmcneill /* Change IDDQ from 1 to 0 */
1155cfee7739Sjmcneill tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
1156cfee7739Sjmcneill 0, CAR_PLLD2_BASE_IDDQ);
1157cfee7739Sjmcneill delay(2);
1158cfee7739Sjmcneill
1159cfee7739Sjmcneill /* Enable lock */
1160cfee7739Sjmcneill tegra_reg_set_clear(bst, bsh, CAR_PLLD2_MISC_REG,
1161cfee7739Sjmcneill CAR_PLLD2_MISC_LOCK_ENABLE, 0);
1162cfee7739Sjmcneill
1163cfee7739Sjmcneill /* Enable PLLD2 */
1164cfee7739Sjmcneill tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
1165cfee7739Sjmcneill CAR_PLLD2_BASE_ENABLE, 0);
1166cfee7739Sjmcneill
1167cfee7739Sjmcneill /* Wait for lock */
1168cfee7739Sjmcneill do {
1169cfee7739Sjmcneill delay(2);
1170cfee7739Sjmcneill v = bus_space_read_4(bst, bsh, CAR_PLLD2_BASE_REG);
1171cfee7739Sjmcneill } while ((v & CAR_PLLD2_BASE_LOCK) == 0);
1172cfee7739Sjmcneill
1173cfee7739Sjmcneill delay(200);
1174cfee7739Sjmcneill }
1175cfee7739Sjmcneill
1176cfee7739Sjmcneill v = bus_space_read_4(bst, bsh, tmux->reg);
1177cfee7739Sjmcneill v &= ~tmux->bits;
1178cfee7739Sjmcneill v |= __SHIFTIN(src, tmux->bits);
1179cfee7739Sjmcneill bus_space_write_4(bst, bsh, tmux->reg, v);
1180cfee7739Sjmcneill
1181cfee7739Sjmcneill return 0;
1182cfee7739Sjmcneill }
1183cfee7739Sjmcneill
1184cfee7739Sjmcneill static struct tegra_clk *
tegra124_car_clock_get_parent_mux(struct tegra124_car_softc * sc,struct tegra_clk * tclk)1185cfee7739Sjmcneill tegra124_car_clock_get_parent_mux(struct tegra124_car_softc *sc,
1186cfee7739Sjmcneill struct tegra_clk *tclk)
1187cfee7739Sjmcneill {
1188cfee7739Sjmcneill struct tegra_mux_clk *tmux = &tclk->u.mux;
1189cfee7739Sjmcneill bus_space_tag_t bst = sc->sc_bst;
1190cfee7739Sjmcneill bus_space_handle_t bsh = sc->sc_bsh;
1191cfee7739Sjmcneill
1192cfee7739Sjmcneill KASSERT(tclk->type == TEGRA_CLK_MUX);
1193cfee7739Sjmcneill
1194cfee7739Sjmcneill const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg);
1195cfee7739Sjmcneill const u_int src = __SHIFTOUT(v, tmux->bits);
1196cfee7739Sjmcneill
1197cfee7739Sjmcneill KASSERT(src < tmux->nparents);
1198cfee7739Sjmcneill
1199cfee7739Sjmcneill if (tmux->parents[src] == NULL) {
1200cfee7739Sjmcneill return NULL;
1201cfee7739Sjmcneill }
1202cfee7739Sjmcneill
1203cfee7739Sjmcneill return tegra124_car_clock_find(tmux->parents[src]);
1204cfee7739Sjmcneill }
1205cfee7739Sjmcneill
1206cfee7739Sjmcneill static u_int
tegra124_car_clock_get_rate_fixed_div(struct tegra124_car_softc * sc,struct tegra_clk * tclk)1207cfee7739Sjmcneill tegra124_car_clock_get_rate_fixed_div(struct tegra124_car_softc *sc,
1208cfee7739Sjmcneill struct tegra_clk *tclk)
1209cfee7739Sjmcneill {
1210cfee7739Sjmcneill struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div;
1211cfee7739Sjmcneill struct clk *clk_parent;
1212cfee7739Sjmcneill
1213cfee7739Sjmcneill clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1214cfee7739Sjmcneill if (clk_parent == NULL)
1215cfee7739Sjmcneill return 0;
1216cfee7739Sjmcneill const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent);
1217cfee7739Sjmcneill
1218cfee7739Sjmcneill return parent_rate / tfixed_div->div;
1219cfee7739Sjmcneill }
1220cfee7739Sjmcneill
1221cfee7739Sjmcneill static u_int
tegra124_car_clock_calc_rate_frac_div(u_int rate,u_int raw_div)1222242e729bSjmcneill tegra124_car_clock_calc_rate_frac_div(u_int rate, u_int raw_div)
1223242e729bSjmcneill {
1224242e729bSjmcneill raw_div += 2;
1225242e729bSjmcneill rate *= 2;
1226242e729bSjmcneill rate += raw_div - 1;
1227242e729bSjmcneill rate /= raw_div;
1228242e729bSjmcneill return rate;
1229242e729bSjmcneill }
1230242e729bSjmcneill
1231242e729bSjmcneill static u_int
tegra124_car_clock_get_rate_div(struct tegra124_car_softc * sc,struct tegra_clk * tclk)1232cfee7739Sjmcneill tegra124_car_clock_get_rate_div(struct tegra124_car_softc *sc,
1233cfee7739Sjmcneill struct tegra_clk *tclk)
1234cfee7739Sjmcneill {
1235cfee7739Sjmcneill struct tegra_div_clk *tdiv = &tclk->u.div;
1236cfee7739Sjmcneill bus_space_tag_t bst = sc->sc_bst;
1237cfee7739Sjmcneill bus_space_handle_t bsh = sc->sc_bsh;
1238cfee7739Sjmcneill struct clk *clk_parent;
12390a244862Sjakllsch u_int rate;
1240cfee7739Sjmcneill
1241cfee7739Sjmcneill KASSERT(tclk->type == TEGRA_CLK_DIV);
1242cfee7739Sjmcneill
1243cfee7739Sjmcneill clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1244cfee7739Sjmcneill const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent);
1245cfee7739Sjmcneill
1246cfee7739Sjmcneill const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg);
1247cfee7739Sjmcneill const u_int raw_div = __SHIFTOUT(v, tdiv->bits);
1248cfee7739Sjmcneill
1249cfee7739Sjmcneill switch (tdiv->reg) {
12500a244862Sjakllsch case CAR_CLKSRC_I2C1_REG:
12510a244862Sjakllsch case CAR_CLKSRC_I2C2_REG:
12520a244862Sjakllsch case CAR_CLKSRC_I2C3_REG:
12530a244862Sjakllsch case CAR_CLKSRC_I2C4_REG:
12540a244862Sjakllsch case CAR_CLKSRC_I2C5_REG:
12550a244862Sjakllsch case CAR_CLKSRC_I2C6_REG:
12560a244862Sjakllsch rate = parent_rate * 1 / (raw_div + 1);
12570a244862Sjakllsch break;
1258cfee7739Sjmcneill case CAR_CLKSRC_UARTA_REG:
1259cfee7739Sjmcneill case CAR_CLKSRC_UARTB_REG:
1260cfee7739Sjmcneill case CAR_CLKSRC_UARTC_REG:
1261cfee7739Sjmcneill case CAR_CLKSRC_UARTD_REG:
1262cfee7739Sjmcneill if (v & CAR_CLKSRC_UART_DIV_ENB) {
1263242e729bSjmcneill rate = tegra124_car_clock_calc_rate_frac_div(
1264242e729bSjmcneill parent_rate, raw_div);
1265cfee7739Sjmcneill } else {
12660a244862Sjakllsch rate = parent_rate;
1267cfee7739Sjmcneill }
1268cfee7739Sjmcneill break;
1269cfee7739Sjmcneill default:
1270242e729bSjmcneill rate = tegra124_car_clock_calc_rate_frac_div(parent_rate,
1271242e729bSjmcneill raw_div);
1272cfee7739Sjmcneill break;
1273cfee7739Sjmcneill }
1274cfee7739Sjmcneill
12750a244862Sjakllsch return rate;
1276cfee7739Sjmcneill }
1277cfee7739Sjmcneill
1278cfee7739Sjmcneill static int
tegra124_car_clock_set_rate_div(struct tegra124_car_softc * sc,struct tegra_clk * tclk,u_int rate)1279cfee7739Sjmcneill tegra124_car_clock_set_rate_div(struct tegra124_car_softc *sc,
1280cfee7739Sjmcneill struct tegra_clk *tclk, u_int rate)
1281cfee7739Sjmcneill {
1282cfee7739Sjmcneill struct tegra_div_clk *tdiv = &tclk->u.div;
1283cfee7739Sjmcneill bus_space_tag_t bst = sc->sc_bst;
1284cfee7739Sjmcneill bus_space_handle_t bsh = sc->sc_bsh;
1285cfee7739Sjmcneill struct clk *clk_parent;
12862f49bee0Sjmcneill u_int raw_div;
1287cfee7739Sjmcneill uint32_t v;
1288cfee7739Sjmcneill
1289cfee7739Sjmcneill KASSERT(tclk->type == TEGRA_CLK_DIV);
1290cfee7739Sjmcneill
1291cfee7739Sjmcneill clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1292cfee7739Sjmcneill if (clk_parent == NULL)
1293cfee7739Sjmcneill return EINVAL;
1294cfee7739Sjmcneill const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent);
1295cfee7739Sjmcneill
1296cfee7739Sjmcneill v = bus_space_read_4(bst, bsh, tdiv->reg);
1297cfee7739Sjmcneill
12980a244862Sjakllsch raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits);
12990a244862Sjakllsch
1300cfee7739Sjmcneill switch (tdiv->reg) {
1301cfee7739Sjmcneill case CAR_CLKSRC_UARTA_REG:
1302cfee7739Sjmcneill case CAR_CLKSRC_UARTB_REG:
1303cfee7739Sjmcneill case CAR_CLKSRC_UARTC_REG:
1304cfee7739Sjmcneill case CAR_CLKSRC_UARTD_REG:
1305cfee7739Sjmcneill if (rate == parent_rate) {
1306cfee7739Sjmcneill v &= ~CAR_CLKSRC_UART_DIV_ENB;
1307cfee7739Sjmcneill } else {
1308cfee7739Sjmcneill v |= CAR_CLKSRC_UART_DIV_ENB;
13090a244862Sjakllsch raw_div = (parent_rate * 2) / rate - 2;
1310cfee7739Sjmcneill }
1311cfee7739Sjmcneill break;
1312cfee7739Sjmcneill case CAR_CLKSRC_SATA_REG:
1313cfee7739Sjmcneill if (rate) {
1314cfee7739Sjmcneill tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
1315cfee7739Sjmcneill 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL);
1316cfee7739Sjmcneill v |= CAR_CLKSRC_SATA_AUX_CLK_ENB;
13170a244862Sjakllsch raw_div = (parent_rate * 2) / rate - 2;
1318cfee7739Sjmcneill } else {
1319cfee7739Sjmcneill v &= ~CAR_CLKSRC_SATA_AUX_CLK_ENB;
1320cfee7739Sjmcneill }
1321cfee7739Sjmcneill break;
13220a244862Sjakllsch case CAR_CLKSRC_I2C1_REG:
13230a244862Sjakllsch case CAR_CLKSRC_I2C2_REG:
13240a244862Sjakllsch case CAR_CLKSRC_I2C3_REG:
13250a244862Sjakllsch case CAR_CLKSRC_I2C4_REG:
13260a244862Sjakllsch case CAR_CLKSRC_I2C5_REG:
13270a244862Sjakllsch case CAR_CLKSRC_I2C6_REG:
13280a244862Sjakllsch if (rate)
13290a244862Sjakllsch raw_div = parent_rate / rate - 1;
13300a244862Sjakllsch break;
1331242e729bSjmcneill case CAR_CLKSRC_SDMMC1_REG:
1332242e729bSjmcneill case CAR_CLKSRC_SDMMC2_REG:
1333242e729bSjmcneill case CAR_CLKSRC_SDMMC3_REG:
1334242e729bSjmcneill case CAR_CLKSRC_SDMMC4_REG:
1335242e729bSjmcneill if (rate) {
1336242e729bSjmcneill for (raw_div = 0x00; raw_div <= 0xff; raw_div++) {
1337242e729bSjmcneill u_int calc_rate =
1338242e729bSjmcneill tegra124_car_clock_calc_rate_frac_div(
1339242e729bSjmcneill parent_rate, raw_div);
1340242e729bSjmcneill if (calc_rate <= rate)
1341242e729bSjmcneill break;
1342242e729bSjmcneill }
1343242e729bSjmcneill if (raw_div == 0x100)
1344242e729bSjmcneill return EINVAL;
1345242e729bSjmcneill }
1346242e729bSjmcneill break;
13470a244862Sjakllsch default:
13480a244862Sjakllsch if (rate)
13492f49bee0Sjmcneill raw_div = (parent_rate * 2) / rate - 2;
13500a244862Sjakllsch break;
13512f49bee0Sjmcneill }
1352cfee7739Sjmcneill
1353cfee7739Sjmcneill v &= ~tdiv->bits;
1354cfee7739Sjmcneill v |= __SHIFTIN(raw_div, tdiv->bits);
1355cfee7739Sjmcneill
1356cfee7739Sjmcneill bus_space_write_4(bst, bsh, tdiv->reg, v);
1357cfee7739Sjmcneill
1358cfee7739Sjmcneill return 0;
1359cfee7739Sjmcneill }
1360cfee7739Sjmcneill
1361cfee7739Sjmcneill static int
tegra124_car_clock_enable_gate(struct tegra124_car_softc * sc,struct tegra_clk * tclk,bool enable)1362cfee7739Sjmcneill tegra124_car_clock_enable_gate(struct tegra124_car_softc *sc,
1363cfee7739Sjmcneill struct tegra_clk *tclk, bool enable)
1364cfee7739Sjmcneill {
1365cfee7739Sjmcneill struct tegra_gate_clk *tgate = &tclk->u.gate;
1366cfee7739Sjmcneill bus_space_tag_t bst = sc->sc_bst;
1367cfee7739Sjmcneill bus_space_handle_t bsh = sc->sc_bsh;
1368cfee7739Sjmcneill bus_size_t reg;
1369cfee7739Sjmcneill
1370cfee7739Sjmcneill KASSERT(tclk->type == TEGRA_CLK_GATE);
1371cfee7739Sjmcneill
1372cfee7739Sjmcneill if (tgate->set_reg == tgate->clr_reg) {
1373cfee7739Sjmcneill uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg);
1374cfee7739Sjmcneill if (enable) {
1375cfee7739Sjmcneill v |= tgate->bits;
1376cfee7739Sjmcneill } else {
1377cfee7739Sjmcneill v &= ~tgate->bits;
1378cfee7739Sjmcneill }
1379cfee7739Sjmcneill bus_space_write_4(bst, bsh, tgate->set_reg, v);
1380cfee7739Sjmcneill } else {
1381cfee7739Sjmcneill if (enable) {
1382cfee7739Sjmcneill reg = tgate->set_reg;
1383cfee7739Sjmcneill } else {
1384cfee7739Sjmcneill reg = tgate->clr_reg;
1385cfee7739Sjmcneill }
1386cfee7739Sjmcneill
1387cfee7739Sjmcneill if (reg == CAR_CLK_ENB_V_SET_REG &&
1388cfee7739Sjmcneill tgate->bits == CAR_DEV_V_SATA) {
1389cfee7739Sjmcneill /* De-assert reset to SATA PADPLL */
1390cfee7739Sjmcneill tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
1391cfee7739Sjmcneill 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE);
1392cfee7739Sjmcneill delay(15);
1393cfee7739Sjmcneill }
1394cfee7739Sjmcneill bus_space_write_4(bst, bsh, reg, tgate->bits);
1395cfee7739Sjmcneill }
1396cfee7739Sjmcneill
1397cfee7739Sjmcneill return 0;
1398cfee7739Sjmcneill }
1399cfee7739Sjmcneill
1400cfee7739Sjmcneill static u_int
tegra124_car_clock_get_rate(void * priv,struct clk * clk)1401cfee7739Sjmcneill tegra124_car_clock_get_rate(void *priv, struct clk *clk)
1402cfee7739Sjmcneill {
1403cfee7739Sjmcneill struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1404cfee7739Sjmcneill struct clk *clk_parent;
1405cfee7739Sjmcneill
1406cfee7739Sjmcneill switch (tclk->type) {
1407cfee7739Sjmcneill case TEGRA_CLK_FIXED:
1408cfee7739Sjmcneill return tclk->u.fixed.rate;
1409cfee7739Sjmcneill case TEGRA_CLK_PLL:
1410cfee7739Sjmcneill return tegra124_car_clock_get_rate_pll(priv, tclk);
1411cfee7739Sjmcneill case TEGRA_CLK_MUX:
1412cfee7739Sjmcneill case TEGRA_CLK_GATE:
1413cfee7739Sjmcneill clk_parent = tegra124_car_clock_get_parent(priv, clk);
1414cfee7739Sjmcneill if (clk_parent == NULL)
1415cfee7739Sjmcneill return EINVAL;
1416cfee7739Sjmcneill return tegra124_car_clock_get_rate(priv, clk_parent);
1417cfee7739Sjmcneill case TEGRA_CLK_FIXED_DIV:
1418cfee7739Sjmcneill return tegra124_car_clock_get_rate_fixed_div(priv, tclk);
1419cfee7739Sjmcneill case TEGRA_CLK_DIV:
1420cfee7739Sjmcneill return tegra124_car_clock_get_rate_div(priv, tclk);
1421cfee7739Sjmcneill default:
1422cfee7739Sjmcneill panic("tegra124: unknown tclk type %d", tclk->type);
1423cfee7739Sjmcneill }
1424cfee7739Sjmcneill }
1425cfee7739Sjmcneill
1426cfee7739Sjmcneill static int
tegra124_car_clock_set_rate(void * priv,struct clk * clk,u_int rate)1427cfee7739Sjmcneill tegra124_car_clock_set_rate(void *priv, struct clk *clk, u_int rate)
1428cfee7739Sjmcneill {
1429cfee7739Sjmcneill struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1430cfee7739Sjmcneill struct clk *clk_parent;
1431cfee7739Sjmcneill
1432cfee7739Sjmcneill KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0);
1433cfee7739Sjmcneill
1434cfee7739Sjmcneill switch (tclk->type) {
1435cfee7739Sjmcneill case TEGRA_CLK_FIXED:
1436cfee7739Sjmcneill case TEGRA_CLK_MUX:
1437cfee7739Sjmcneill return EIO;
1438cfee7739Sjmcneill case TEGRA_CLK_FIXED_DIV:
1439cfee7739Sjmcneill clk_parent = tegra124_car_clock_get_parent(priv, clk);
1440cfee7739Sjmcneill if (clk_parent == NULL)
1441cfee7739Sjmcneill return EIO;
1442cfee7739Sjmcneill return tegra124_car_clock_set_rate(priv, clk_parent,
1443cfee7739Sjmcneill rate * tclk->u.fixed_div.div);
1444cfee7739Sjmcneill case TEGRA_CLK_GATE:
1445cfee7739Sjmcneill return EINVAL;
1446cfee7739Sjmcneill case TEGRA_CLK_PLL:
1447cfee7739Sjmcneill return tegra124_car_clock_set_rate_pll(priv, tclk, rate);
1448cfee7739Sjmcneill case TEGRA_CLK_DIV:
1449cfee7739Sjmcneill return tegra124_car_clock_set_rate_div(priv, tclk, rate);
1450cfee7739Sjmcneill default:
1451cfee7739Sjmcneill panic("tegra124: unknown tclk type %d", tclk->type);
1452cfee7739Sjmcneill }
1453cfee7739Sjmcneill }
1454cfee7739Sjmcneill
1455cfee7739Sjmcneill static int
tegra124_car_clock_enable(void * priv,struct clk * clk)1456cfee7739Sjmcneill tegra124_car_clock_enable(void *priv, struct clk *clk)
1457cfee7739Sjmcneill {
1458cfee7739Sjmcneill struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1459cfee7739Sjmcneill struct clk *clk_parent;
1460cfee7739Sjmcneill
1461cfee7739Sjmcneill if (tclk->type != TEGRA_CLK_GATE) {
1462cfee7739Sjmcneill clk_parent = tegra124_car_clock_get_parent(priv, clk);
1463cfee7739Sjmcneill if (clk_parent == NULL)
1464cfee7739Sjmcneill return 0;
1465cfee7739Sjmcneill return tegra124_car_clock_enable(priv, clk_parent);
1466cfee7739Sjmcneill }
1467cfee7739Sjmcneill
1468cfee7739Sjmcneill return tegra124_car_clock_enable_gate(priv, tclk, true);
1469cfee7739Sjmcneill }
1470cfee7739Sjmcneill
1471cfee7739Sjmcneill static int
tegra124_car_clock_disable(void * priv,struct clk * clk)1472cfee7739Sjmcneill tegra124_car_clock_disable(void *priv, struct clk *clk)
1473cfee7739Sjmcneill {
1474cfee7739Sjmcneill struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1475cfee7739Sjmcneill
1476cfee7739Sjmcneill if (tclk->type != TEGRA_CLK_GATE)
1477cfee7739Sjmcneill return EINVAL;
1478cfee7739Sjmcneill
1479cfee7739Sjmcneill return tegra124_car_clock_enable_gate(priv, tclk, false);
1480cfee7739Sjmcneill }
1481cfee7739Sjmcneill
1482cfee7739Sjmcneill static int
tegra124_car_clock_set_parent(void * priv,struct clk * clk,struct clk * clk_parent)1483cfee7739Sjmcneill tegra124_car_clock_set_parent(void *priv, struct clk *clk,
1484cfee7739Sjmcneill struct clk *clk_parent)
1485cfee7739Sjmcneill {
1486cfee7739Sjmcneill struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1487cfee7739Sjmcneill struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent);
1488cfee7739Sjmcneill struct clk *nclk_parent;
1489cfee7739Sjmcneill
1490cfee7739Sjmcneill if (tclk->type != TEGRA_CLK_MUX) {
1491cfee7739Sjmcneill nclk_parent = tegra124_car_clock_get_parent(priv, clk);
1492cfee7739Sjmcneill if (nclk_parent == clk_parent || nclk_parent == NULL)
1493cfee7739Sjmcneill return EINVAL;
1494cfee7739Sjmcneill return tegra124_car_clock_set_parent(priv, nclk_parent,
1495cfee7739Sjmcneill clk_parent);
1496cfee7739Sjmcneill }
1497cfee7739Sjmcneill
1498cfee7739Sjmcneill return tegra124_car_clock_set_parent_mux(priv, tclk, tclk_parent);
1499cfee7739Sjmcneill }
1500cfee7739Sjmcneill
1501cfee7739Sjmcneill static struct clk *
tegra124_car_clock_get_parent(void * priv,struct clk * clk)1502cfee7739Sjmcneill tegra124_car_clock_get_parent(void *priv, struct clk *clk)
1503cfee7739Sjmcneill {
1504cfee7739Sjmcneill struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1505cfee7739Sjmcneill struct tegra_clk *tclk_parent = NULL;
1506cfee7739Sjmcneill
1507cfee7739Sjmcneill switch (tclk->type) {
1508cfee7739Sjmcneill case TEGRA_CLK_FIXED:
1509cfee7739Sjmcneill case TEGRA_CLK_PLL:
1510cfee7739Sjmcneill case TEGRA_CLK_FIXED_DIV:
1511cfee7739Sjmcneill case TEGRA_CLK_DIV:
1512cfee7739Sjmcneill case TEGRA_CLK_GATE:
1513cfee7739Sjmcneill if (tclk->parent) {
1514cfee7739Sjmcneill tclk_parent = tegra124_car_clock_find(tclk->parent);
1515cfee7739Sjmcneill }
1516cfee7739Sjmcneill break;
1517cfee7739Sjmcneill case TEGRA_CLK_MUX:
1518cfee7739Sjmcneill tclk_parent = tegra124_car_clock_get_parent_mux(priv, tclk);
1519cfee7739Sjmcneill break;
1520cfee7739Sjmcneill }
1521cfee7739Sjmcneill
1522cfee7739Sjmcneill if (tclk_parent == NULL)
1523cfee7739Sjmcneill return NULL;
1524cfee7739Sjmcneill
1525cfee7739Sjmcneill return TEGRA_CLK_BASE(tclk_parent);
1526cfee7739Sjmcneill }
1527cfee7739Sjmcneill
1528cfee7739Sjmcneill static void *
tegra124_car_reset_acquire(device_t dev,const void * data,size_t len)1529cfee7739Sjmcneill tegra124_car_reset_acquire(device_t dev, const void *data, size_t len)
1530cfee7739Sjmcneill {
1531cfee7739Sjmcneill struct tegra124_car_softc * const sc = device_private(dev);
1532cfee7739Sjmcneill struct tegra124_car_rst *rst;
1533cfee7739Sjmcneill
1534cfee7739Sjmcneill if (len != sc->sc_reset_cells * 4)
1535cfee7739Sjmcneill return NULL;
1536cfee7739Sjmcneill
1537cfee7739Sjmcneill const u_int reset_id = be32dec(data);
1538cfee7739Sjmcneill
1539307bee4dSmaya if (reset_id >= __arraycount(tegra124_car_reset_regs) * 32)
1540cfee7739Sjmcneill return NULL;
1541cfee7739Sjmcneill
1542cfee7739Sjmcneill const u_int reg = reset_id / 32;
1543cfee7739Sjmcneill
1544cfee7739Sjmcneill rst = kmem_alloc(sizeof(*rst), KM_SLEEP);
1545cfee7739Sjmcneill rst->set_reg = tegra124_car_reset_regs[reg].set_reg;
1546cfee7739Sjmcneill rst->clr_reg = tegra124_car_reset_regs[reg].clr_reg;
1547cfee7739Sjmcneill rst->mask = __BIT(reset_id % 32);
1548cfee7739Sjmcneill
1549cfee7739Sjmcneill return rst;
1550cfee7739Sjmcneill }
1551cfee7739Sjmcneill
1552cfee7739Sjmcneill static void
tegra124_car_reset_release(device_t dev,void * priv)1553cfee7739Sjmcneill tegra124_car_reset_release(device_t dev, void *priv)
1554cfee7739Sjmcneill {
1555cfee7739Sjmcneill struct tegra124_car_rst *rst = priv;
1556cfee7739Sjmcneill
1557cfee7739Sjmcneill kmem_free(rst, sizeof(*rst));
1558cfee7739Sjmcneill }
1559cfee7739Sjmcneill
1560cfee7739Sjmcneill static int
tegra124_car_reset_assert(device_t dev,void * priv)1561cfee7739Sjmcneill tegra124_car_reset_assert(device_t dev, void *priv)
1562cfee7739Sjmcneill {
1563cfee7739Sjmcneill struct tegra124_car_softc * const sc = device_private(dev);
1564cfee7739Sjmcneill struct tegra124_car_rst *rst = priv;
1565cfee7739Sjmcneill
1566cfee7739Sjmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask);
1567cfee7739Sjmcneill
1568cfee7739Sjmcneill return 0;
1569cfee7739Sjmcneill }
1570cfee7739Sjmcneill
1571cfee7739Sjmcneill static int
tegra124_car_reset_deassert(device_t dev,void * priv)1572cfee7739Sjmcneill tegra124_car_reset_deassert(device_t dev, void *priv)
1573cfee7739Sjmcneill {
1574cfee7739Sjmcneill struct tegra124_car_softc * const sc = device_private(dev);
1575cfee7739Sjmcneill struct tegra124_car_rst *rst = priv;
1576cfee7739Sjmcneill
1577cfee7739Sjmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask);
1578cfee7739Sjmcneill
1579cfee7739Sjmcneill return 0;
1580cfee7739Sjmcneill }
1581