1*8e90f9edSthorpej /* $NetBSD: tegra_lic.c,v 1.8 2021/01/27 03:10:19 thorpej Exp $ */
2c52d9763Sjmcneill
3c52d9763Sjmcneill /*-
4c52d9763Sjmcneill * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5c52d9763Sjmcneill * All rights reserved.
6c52d9763Sjmcneill *
7c52d9763Sjmcneill * Redistribution and use in source and binary forms, with or without
8c52d9763Sjmcneill * modification, are permitted provided that the following conditions
9c52d9763Sjmcneill * are met:
10c52d9763Sjmcneill * 1. Redistributions of source code must retain the above copyright
11c52d9763Sjmcneill * notice, this list of conditions and the following disclaimer.
12c52d9763Sjmcneill * 2. Redistributions in binary form must reproduce the above copyright
13c52d9763Sjmcneill * notice, this list of conditions and the following disclaimer in the
14c52d9763Sjmcneill * documentation and/or other materials provided with the distribution.
15c52d9763Sjmcneill *
16c52d9763Sjmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17c52d9763Sjmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18c52d9763Sjmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19c52d9763Sjmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20c52d9763Sjmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21c52d9763Sjmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22c52d9763Sjmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23c52d9763Sjmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24c52d9763Sjmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25c52d9763Sjmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26c52d9763Sjmcneill * SUCH DAMAGE.
27c52d9763Sjmcneill */
28c52d9763Sjmcneill
29c52d9763Sjmcneill #include <sys/cdefs.h>
30*8e90f9edSthorpej __KERNEL_RCSID(0, "$NetBSD: tegra_lic.c,v 1.8 2021/01/27 03:10:19 thorpej Exp $");
31c52d9763Sjmcneill
32c52d9763Sjmcneill #include <sys/param.h>
33c52d9763Sjmcneill #include <sys/bus.h>
34c52d9763Sjmcneill #include <sys/device.h>
35c52d9763Sjmcneill #include <sys/intr.h>
36c52d9763Sjmcneill #include <sys/systm.h>
37c52d9763Sjmcneill #include <sys/kernel.h>
38c52d9763Sjmcneill #include <sys/kmem.h>
39c52d9763Sjmcneill
40c52d9763Sjmcneill #include <arm/nvidia/tegra_reg.h>
41c52d9763Sjmcneill #include <arm/nvidia/tegra_var.h>
42c52d9763Sjmcneill
43c52d9763Sjmcneill #include <arm/cortex/gic_intr.h>
44c52d9763Sjmcneill
45c52d9763Sjmcneill #include <dev/fdt/fdtvar.h>
46c52d9763Sjmcneill
474dc7dbdeSjmcneill #define LIC_CPU_IER_CLR_REG 0x28
484dc7dbdeSjmcneill #define LIC_CPU_IEP_CLASS_REG 0x2c
494dc7dbdeSjmcneill
50c52d9763Sjmcneill static int tegra_lic_match(device_t, cfdata_t, void *);
51c52d9763Sjmcneill static void tegra_lic_attach(device_t, device_t, void *);
52c52d9763Sjmcneill
5311ffa746Smarty static void * tegra_lic_establish(device_t, u_int *, int, int,
54366e5a5bSjmcneill int (*)(void *), void *, const char *);
55c52d9763Sjmcneill static void tegra_lic_disestablish(device_t, void *);
5611ffa746Smarty static bool tegra_lic_intrstr(device_t, u_int *, char *, size_t);
57c52d9763Sjmcneill
58c52d9763Sjmcneill struct fdtbus_interrupt_controller_func tegra_lic_funcs = {
59c52d9763Sjmcneill .establish = tegra_lic_establish,
60c52d9763Sjmcneill .disestablish = tegra_lic_disestablish,
61c52d9763Sjmcneill .intrstr = tegra_lic_intrstr
62c52d9763Sjmcneill };
63c52d9763Sjmcneill
64c52d9763Sjmcneill struct tegra_lic_softc {
65c52d9763Sjmcneill device_t sc_dev;
66c52d9763Sjmcneill int sc_phandle;
67c52d9763Sjmcneill };
68c52d9763Sjmcneill
69c52d9763Sjmcneill CFATTACH_DECL_NEW(tegra_lic, sizeof(struct tegra_lic_softc),
70c52d9763Sjmcneill tegra_lic_match, tegra_lic_attach, NULL, NULL);
71c52d9763Sjmcneill
72*8e90f9edSthorpej static const struct device_compatible_entry compat_data[] = {
73*8e90f9edSthorpej { .compat = "nvidia,tegra210-ictlr" },
74*8e90f9edSthorpej { .compat = "nvidia,tegra124-ictlr" },
75*8e90f9edSthorpej DEVICE_COMPAT_EOL
76*8e90f9edSthorpej };
77*8e90f9edSthorpej
78c52d9763Sjmcneill static int
tegra_lic_match(device_t parent,cfdata_t cf,void * aux)79c52d9763Sjmcneill tegra_lic_match(device_t parent, cfdata_t cf, void *aux)
80c52d9763Sjmcneill {
81c52d9763Sjmcneill struct fdt_attach_args * const faa = aux;
82c52d9763Sjmcneill
83*8e90f9edSthorpej return of_compatible_match(faa->faa_phandle, compat_data);
84c52d9763Sjmcneill }
85c52d9763Sjmcneill
86c52d9763Sjmcneill static void
tegra_lic_attach(device_t parent,device_t self,void * aux)87c52d9763Sjmcneill tegra_lic_attach(device_t parent, device_t self, void *aux)
88c52d9763Sjmcneill {
89c52d9763Sjmcneill struct tegra_lic_softc * const sc = device_private(self);
90c52d9763Sjmcneill struct fdt_attach_args * const faa = aux;
914dc7dbdeSjmcneill bus_space_tag_t bst;
924dc7dbdeSjmcneill bus_space_handle_t bsh;
934dc7dbdeSjmcneill bus_addr_t addr;
944dc7dbdeSjmcneill bus_size_t size;
954dc7dbdeSjmcneill int error, index;
96c52d9763Sjmcneill
97c52d9763Sjmcneill sc->sc_dev = self;
98c52d9763Sjmcneill sc->sc_phandle = faa->faa_phandle;
99c52d9763Sjmcneill
100c52d9763Sjmcneill error = fdtbus_register_interrupt_controller(self, faa->faa_phandle,
101c52d9763Sjmcneill &tegra_lic_funcs);
102c52d9763Sjmcneill if (error) {
103c52d9763Sjmcneill aprint_error(": couldn't register with fdtbus: %d\n", error);
104c52d9763Sjmcneill return;
105c52d9763Sjmcneill }
106c52d9763Sjmcneill
107c52d9763Sjmcneill aprint_naive("\n");
108c52d9763Sjmcneill aprint_normal(": LIC\n");
1094dc7dbdeSjmcneill
1104dc7dbdeSjmcneill bst = faa->faa_bst;
1114dc7dbdeSjmcneill for (index = 0; ; index++) {
1124dc7dbdeSjmcneill error = fdtbus_get_reg(faa->faa_phandle, index, &addr, &size);
1134dc7dbdeSjmcneill if (error != 0)
1144dc7dbdeSjmcneill break;
1154dc7dbdeSjmcneill error = bus_space_map(bst, addr, size, 0, &bsh);
1164dc7dbdeSjmcneill if (error) {
1174dc7dbdeSjmcneill aprint_error_dev(self, "can't map IC#%d: %d\n",
1184dc7dbdeSjmcneill index, error);
1194dc7dbdeSjmcneill continue;
1204dc7dbdeSjmcneill }
1214dc7dbdeSjmcneill
1224dc7dbdeSjmcneill /* Clear interrupt enable for CPU */
1234dc7dbdeSjmcneill bus_space_write_4(bst, bsh, LIC_CPU_IER_CLR_REG, 0xffffffff);
1244dc7dbdeSjmcneill
1254dc7dbdeSjmcneill /* Route to IRQ */
1264dc7dbdeSjmcneill bus_space_write_4(bst, bsh, LIC_CPU_IEP_CLASS_REG, 0);
1274dc7dbdeSjmcneill
1284dc7dbdeSjmcneill bus_space_unmap(bst, bsh, size);
1294dc7dbdeSjmcneill }
130c52d9763Sjmcneill }
131c52d9763Sjmcneill
132c52d9763Sjmcneill static void *
tegra_lic_establish(device_t dev,u_int * specifier,int ipl,int flags,int (* func)(void *),void * arg,const char * xname)13311ffa746Smarty tegra_lic_establish(device_t dev, u_int *specifier, int ipl, int flags,
134366e5a5bSjmcneill int (*func)(void *), void *arg, const char *xname)
135c52d9763Sjmcneill {
136c52d9763Sjmcneill int iflags = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0;
137c52d9763Sjmcneill
138c52d9763Sjmcneill /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */
139c52d9763Sjmcneill /* 2nd cell is the interrupt number */
140c52d9763Sjmcneill /* 3rd cell is flags */
141c52d9763Sjmcneill
14211ffa746Smarty const u_int type = be32toh(specifier[0]);
14311ffa746Smarty const u_int intr = be32toh(specifier[1]);
144c52d9763Sjmcneill const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr);
14511ffa746Smarty const u_int trig = be32toh(specifier[2]) & 0xf;
14628a4eb56Sthorpej const u_int level = (trig & FDT_INTR_TYPE_DOUBLE_EDGE)
14728a4eb56Sthorpej ? IST_EDGE : IST_LEVEL;
148c52d9763Sjmcneill
149366e5a5bSjmcneill return intr_establish_xname(irq, ipl, level | iflags, func, arg,
150366e5a5bSjmcneill xname);
151c52d9763Sjmcneill }
152c52d9763Sjmcneill
153c52d9763Sjmcneill static void
tegra_lic_disestablish(device_t dev,void * ih)154c52d9763Sjmcneill tegra_lic_disestablish(device_t dev, void *ih)
155c52d9763Sjmcneill {
156c52d9763Sjmcneill intr_disestablish(ih);
157c52d9763Sjmcneill }
158c52d9763Sjmcneill
159c52d9763Sjmcneill static bool
tegra_lic_intrstr(device_t dev,u_int * specifier,char * buf,size_t buflen)16011ffa746Smarty tegra_lic_intrstr(device_t dev, u_int *specifier, char *buf,
161c52d9763Sjmcneill size_t buflen)
162c52d9763Sjmcneill {
163c52d9763Sjmcneill /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */
164c52d9763Sjmcneill /* 2nd cell is the interrupt number */
165c52d9763Sjmcneill /* 3rd cell is flags */
166c52d9763Sjmcneill
16711ffa746Smarty const u_int type = be32toh(specifier[0]);
16811ffa746Smarty const u_int intr = be32toh(specifier[1]);
169c52d9763Sjmcneill const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr);
170c52d9763Sjmcneill
1714dc7dbdeSjmcneill snprintf(buf, buflen, "irq %d", irq);
172c52d9763Sjmcneill
173c52d9763Sjmcneill return true;
174c52d9763Sjmcneill }
175