1 /*- 2 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Paul Fleischer <paul@xpg.dk> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* Derived from s3c2410_intr.c */ 31 /* 32 * Copyright (c) 2003 Genetec corporation. All rights reserved. 33 * Written by Hiroyuki Bessho for Genetec corporation. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. The name of Genetec corporation may not be used to endorse 44 * or promote products derived from this software without specific prior 45 * written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 49 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 50 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 51 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 52 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 53 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 54 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 55 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 56 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 57 * POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * IRQ handler for Samsung S3C2440 processor. 62 * It has integrated interrupt controller. 63 */ 64 65 #include <sys/cdefs.h> 66 __KERNEL_RCSID(0, "$NetBSD: s3c2440_intr.c,v 1.1 2012/01/30 03:28:33 nisimura Exp $"); 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/malloc.h> 71 #include <sys/atomic.h> 72 #include <sys/bus.h> 73 #include <machine/intr.h> 74 #include <arm/cpufunc.h> 75 76 #include <arm/s3c2xx0/s3c2440reg.h> 77 #include <arm/s3c2xx0/s3c2440var.h> 78 79 /* 80 * interrupt dispatch table. 81 */ 82 83 struct s3c2xx0_intr_dispatch handler[ICU_LEN]; 84 85 86 volatile int intr_mask; 87 #ifdef __HAVE_FAST_SOFTINTS 88 volatile int softint_pending; 89 volatile int soft_intr_mask; 90 #endif 91 volatile int global_intr_mask = 0; /* mask some interrupts at all spl level */ 92 93 /* interrupt masks for each level */ 94 int s3c2xx0_imask[NIPL]; 95 int s3c2xx0_ilevel[ICU_LEN]; 96 #ifdef __HAVE_FAST_SOFTINTS 97 int s3c24x0_soft_imask[NIPL]; 98 #endif 99 100 vaddr_t intctl_base; /* interrupt controller registers */ 101 #define icreg(offset) \ 102 (*(volatile uint32_t *)(intctl_base+(offset))) 103 104 #ifdef __HAVE_FAST_SOFTINTS 105 /* 106 * Map a software interrupt queue to an interrupt priority level. 107 */ 108 static const int si_to_ipl[] = { 109 [SI_SOFTBIO] = IPL_SOFTBIO, 110 [SI_SOFTCLOCK] = IPL_SOFTCLOCK, 111 [SI_SOFTNET] = IPL_SOFTNET, 112 [SI_SOFTSERIAL] = IPL_SOFTSERIAL, 113 }; 114 #endif 115 116 #define PENDING_CLEAR_MASK (~0) 117 118 /* 119 * called from irq_entry. 120 */ 121 void s3c2440_irq_handler(struct clockframe *); 122 void 123 s3c2440_irq_handler(struct clockframe *frame) 124 { 125 uint32_t irqbits; 126 int irqno; 127 int saved_spl_level; 128 struct cpu_info * const ci = curcpu(); 129 130 saved_spl_level = curcpl(); 131 132 #ifdef DIAGNOSTIC 133 if (curcpu()->ci_intr_depth > 10) 134 panic("nested intr too deep"); 135 #endif 136 137 while ((irqbits = icreg(INTCTL_INTPND)) != 0) { 138 /* Note: Only one bit in INTPND register is set */ 139 140 irqno = icreg(INTCTL_INTOFFSET); 141 142 #ifdef DIAGNOSTIC 143 if (__predict_false((irqbits & (1<<irqno)) == 0)) { 144 /* This shouldn't happen */ 145 printf("INTOFFSET=%d, INTPND=%x\n", irqno, irqbits); 146 break; 147 } 148 #endif 149 /* raise spl to stop interrupts of lower priorities */ 150 if (saved_spl_level < handler[irqno].level) 151 s3c2xx0_setipl(handler[irqno].level); 152 153 /* clear pending bit */ 154 icreg(INTCTL_SRCPND) = PENDING_CLEAR_MASK & (1 << irqno); 155 icreg(INTCTL_INTPND) = PENDING_CLEAR_MASK & (1 << irqno); 156 157 handler[irqno].ev.ev_count++; 158 ci->ci_data.cpu_nintr++; 159 160 enable_interrupts(I32_bit); /* allow nested interrupts */ 161 162 (*handler[irqno].func) ( 163 handler[irqno].cookie == 0 164 ? frame : handler[irqno].cookie); 165 166 disable_interrupts(I32_bit); 167 168 /* restore spl to that was when this interrupt happen */ 169 s3c2xx0_setipl(saved_spl_level); 170 171 } 172 173 #ifdef __HAVE_FAST_SOFTINTS 174 cpu_dosoftints(); 175 #endif 176 } 177 178 /* 179 * Handler for main IRQ of cascaded interrupts. 180 */ 181 static int 182 cascade_irq_handler(void *cookie) 183 { 184 int index = (int)cookie - 1; 185 uint32_t irqbits; 186 int irqno, i; 187 int save = disable_interrupts(I32_bit); 188 189 KASSERT(0 <= index && index <= 3); 190 191 irqbits = icreg(INTCTL_SUBSRCPND) & 192 ~icreg(INTCTL_INTSUBMSK) & (0x07 << (3*index)); 193 194 for (irqno = 3*index; irqbits; ++irqno) { 195 if ((irqbits & (1<<irqno)) == 0) 196 continue; 197 198 /* clear pending bit */ 199 irqbits &= ~(1<<irqno); 200 icreg(INTCTL_SUBSRCPND) = (1 << irqno); 201 202 /* allow nested interrupts. SPL is already set 203 * correctly by main handler. */ 204 restore_interrupts(save); 205 206 i = S3C2440_SUBIRQ_MIN + irqno; 207 (* handler[i].func)(handler[i].cookie); 208 209 disable_interrupts(I32_bit); 210 } 211 212 return 1; 213 } 214 215 216 static const uint8_t subirq_to_main[] = { 217 S3C2440_INT_UART0, 218 S3C2440_INT_UART0, 219 S3C2440_INT_UART0, 220 S3C2440_INT_UART1, 221 S3C2440_INT_UART1, 222 S3C2440_INT_UART1, 223 S3C2440_INT_UART2, 224 S3C2440_INT_UART2, 225 S3C2440_INT_UART2, 226 S3C24X0_INT_ADCTC, 227 S3C24X0_INT_ADCTC, 228 }; 229 230 void * 231 s3c24x0_intr_establish(int irqno, int level, int type, 232 int (* func) (void *), void *cookie) 233 { 234 int save; 235 236 if (irqno < 0 || irqno >= ICU_LEN || 237 type < IST_NONE || IST_EDGE_BOTH < type) 238 panic("intr_establish: bogus irq or type"); 239 240 save = disable_interrupts(I32_bit); 241 242 handler[irqno].cookie = cookie; 243 handler[irqno].func = func; 244 handler[irqno].level = level; 245 246 if (irqno >= S3C2440_SUBIRQ_MIN) { 247 /* cascaded interrupts. */ 248 int main_irqno; 249 int i = (irqno - S3C2440_SUBIRQ_MIN); 250 251 main_irqno = subirq_to_main[i]; 252 253 /* establish main irq if first time 254 * be careful that cookie shouldn't be 0 */ 255 if (handler[main_irqno].func != cascade_irq_handler) 256 s3c24x0_intr_establish(main_irqno, level, type, 257 cascade_irq_handler, (void *)((i/3) + 1)); 258 259 /* unmask it in submask register */ 260 icreg(INTCTL_INTSUBMSK) &= ~(1<<i); 261 262 restore_interrupts(save); 263 return &handler[irqno]; 264 } 265 266 s3c2xx0_update_intr_masks(irqno, level); 267 268 /* 269 * set trigger type for external interrupts 0..3 270 */ 271 if (irqno <= S3C24X0_INT_EXT(3)) { 272 /* 273 * Update external interrupt control 274 */ 275 s3c2440_setup_extint(irqno, type); 276 } 277 278 s3c2xx0_setipl(curcpl()); 279 280 restore_interrupts(save); 281 282 return &handler[irqno]; 283 } 284 285 286 static void 287 init_interrupt_masks(void) 288 { 289 int i; 290 291 for (i=0; i < NIPL; ++i) 292 s3c2xx0_imask[i] = 0; 293 294 #ifdef __HAVE_FAST_SOFTINTS 295 s3c24x0_soft_imask[IPL_NONE] = SI_TO_IRQBIT(SI_SOFTSERIAL) | 296 SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK) | 297 SI_TO_IRQBIT(SI_SOFT); 298 299 s3c24x0_soft_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFTSERIAL) | 300 SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK); 301 302 /* 303 * splsoftclock() is the only interface that users of the 304 * generic software interrupt facility have to block their 305 * soft intrs, so splsoftclock() must also block IPL_SOFT. 306 */ 307 s3c24x0_soft_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTSERIAL) | 308 SI_TO_IRQBIT(SI_SOFTNET); 309 310 /* 311 * splsoftnet() must also block splsoftclock(), since we don't 312 * want timer-driven network events to occur while we're 313 * processing incoming packets. 314 */ 315 s3c24x0_soft_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTSERIAL); 316 317 for (i = IPL_BIO; i < IPL_SOFTSERIAL; ++i) 318 s3c24x0_soft_imask[i] = SI_TO_IRQBIT(SI_SOFTSERIAL); 319 #endif 320 } 321 322 void 323 s3c2440_intr_init(struct s3c24x0_softc *sc) 324 { 325 intctl_base = (vaddr_t) bus_space_vaddr(sc->sc_sx.sc_iot, 326 sc->sc_sx.sc_intctl_ioh); 327 328 s3c2xx0_intr_mask_reg = (uint32_t *)(intctl_base + INTCTL_INTMSK); 329 330 /* clear all pending interrupt */ 331 icreg(INTCTL_SRCPND) = ~0; 332 icreg(INTCTL_INTPND) = ~0; 333 334 /* mask all sub interrupts */ 335 icreg(INTCTL_INTSUBMSK) = 0x7ff; 336 337 init_interrupt_masks(); 338 339 s3c2xx0_intr_init(handler, ICU_LEN); 340 341 } 342 343 344 /* 345 * mask/unmask sub interrupts 346 */ 347 void 348 s3c2440_mask_subinterrupts(int bits) 349 { 350 int psw = disable_interrupts(IF32_bits); 351 icreg(INTCTL_INTSUBMSK) |= bits; 352 restore_interrupts(psw); 353 354 } 355 356 void 357 s3c2440_unmask_subinterrupts(int bits) 358 { 359 int psw = disable_interrupts(IF32_bits); 360 icreg(INTCTL_INTSUBMSK) &= ~bits; 361 restore_interrupts(psw); 362 363 } 364 365 /* 366 * Update external interrupt control 367 */ 368 static const u_char s3c24x0_ist[] = { 369 EXTINTR_LOW, /* NONE */ 370 EXTINTR_FALLING, /* PULSE */ 371 EXTINTR_FALLING, /* EDGE */ 372 EXTINTR_LOW, /* LEVEL */ 373 EXTINTR_HIGH, 374 EXTINTR_RISING, 375 EXTINTR_BOTH, 376 }; 377 378 void 379 s3c2440_setup_extint(int extint, int type) 380 { 381 uint32_t reg; 382 u_int trig; 383 int i = extint % 8; 384 int regidx = extint/8; /* GPIO_EXTINT[0:2] */ 385 int save; 386 uint32_t gpio; 387 uint32_t offset; 388 389 trig = s3c24x0_ist[type]; 390 391 save = disable_interrupts(I32_bit); 392 393 reg = bus_space_read_4(s3c2xx0_softc->sc_iot, 394 s3c2xx0_softc->sc_gpio_ioh, 395 GPIO_EXTINT(regidx)); 396 397 reg = reg & ~(0x07 << (4*i)); 398 reg |= trig << (4*i); 399 400 bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh, 401 GPIO_EXTINT(regidx), reg); 402 403 /* Setup GPIO-pin to serve as interrupt */ 404 if (extint < 8 ) { 405 gpio = GPIO_PFCON; 406 offset = extint; 407 } else { 408 gpio = GPIO_PGCON; 409 offset = 8-extint; 410 } 411 reg = bus_space_read_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh, 412 gpio); 413 reg = GPIO_SET_FUNC(reg, offset, 2); 414 bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh, 415 gpio, reg); 416 417 418 restore_interrupts(save); 419 } 420